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authorNiels Ole Salscheider <niels_ole@salscheider-online.de>2013-05-18 15:19:23 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-05-20 10:44:57 -0400
commitfc986034540102cd090237bf3f70262e1ae80d9c (patch)
tree4698f43fab9c2ba576525c7734cee6e63344e62d
parent6ab7631014d0648e916f674c4bce0518739a2142 (diff)
drm/radeon: Fix VRAM size calculation for VRAM >= 4GB
Add ULL prefix to avoid overflow. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c2
-rw-r--r--drivers/gpu/drm/radeon/si.c4
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 105bafb6c29d..06c261bed289 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3405,8 +3405,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
3405 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 3405 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3406 } else { 3406 } else {
3407 /* size in MB on evergreen/cayman/tn */ 3407 /* size in MB on evergreen/cayman/tn */
3408 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3408 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3409 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3409 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3410 } 3410 }
3411 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3411 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3412 r700_vram_gtt_location(rdev, &rdev->mc); 3412 r700_vram_gtt_location(rdev, &rdev->mc);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 93f760e27a92..6c0ce8915fac 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -726,7 +726,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
726 return r; 726 return r;
727 } 727 }
728 DRM_INFO("radeon: %uM of VRAM memory ready\n", 728 DRM_INFO("radeon: %uM of VRAM memory ready\n",
729 (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); 729 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
730 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 730 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
731 rdev->mc.gtt_size >> PAGE_SHIFT); 731 rdev->mc.gtt_size >> PAGE_SHIFT);
732 if (r) { 732 if (r) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f0b6c2f87c4d..113ed9f1f0d1 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3397,8 +3397,8 @@ static int si_mc_init(struct radeon_device *rdev)
3397 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 3397 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3398 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 3398 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3399 /* size in MB on si */ 3399 /* size in MB on si */
3400 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3400 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3401 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3401 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3402 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3402 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3403 si_vram_gtt_location(rdev, &rdev->mc); 3403 si_vram_gtt_location(rdev, &rdev->mc);
3404 radeon_update_bandwidth_info(rdev); 3404 radeon_update_bandwidth_info(rdev);