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authorH Hartley Sweeten <hsweeten@visionengravers.com>2013-04-12 16:40:12 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-04-15 13:55:58 -0400
commitfc09ec34f6a5f4b05f34eef1e2f3601b0f9c138f (patch)
treef6d25e1fec79d462d3c7bb5311712a06bc364a8a
parent926848220e601338c918bdbde1d3fe7e63c8c04d (diff)
staging: comedi: adl_pci9111: use plx9052.h defines
Use the PLX 9052 register defines in plx9052.h instead of duplicating the defines locally in this driver. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/staging/comedi/drivers/adl_pci9111.c48
1 files changed, 21 insertions, 27 deletions
diff --git a/drivers/staging/comedi/drivers/adl_pci9111.c b/drivers/staging/comedi/drivers/adl_pci9111.c
index 99bce7c74af7..6247fdcedcbf 100644
--- a/drivers/staging/comedi/drivers/adl_pci9111.c
+++ b/drivers/staging/comedi/drivers/adl_pci9111.c
@@ -75,6 +75,7 @@ TODO:
75#include "../comedidev.h" 75#include "../comedidev.h"
76 76
77#include "8253.h" 77#include "8253.h"
78#include "plx9052.h"
78#include "comedi_fc.h" 79#include "comedi_fc.h"
79 80
80#define PCI9111_DRIVER_NAME "adl_pci9111" 81#define PCI9111_DRIVER_NAME "adl_pci9111"
@@ -120,6 +121,14 @@ TODO:
120#define PCI9111_8254_BASE_REG 0x40 121#define PCI9111_8254_BASE_REG 0x40
121#define PCI9111_INT_CLR_REG 0x48 122#define PCI9111_INT_CLR_REG 0x48
122 123
124/* PLX 9052 Local Interrupt 1 enabled and active */
125#define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \
126 PLX9052_INTCSR_LI1STAT)
127
128/* PLX 9052 Local Interrupt 2 enabled and active */
129#define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \
130 PLX9052_INTCSR_LI2STAT)
131
123static const struct comedi_lrange pci9111_ai_range = { 132static const struct comedi_lrange pci9111_ai_range = {
124 5, 133 5,
125 { 134 {
@@ -150,17 +159,6 @@ struct pci9111_private_data {
150 short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE]; 159 short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE];
151}; 160};
152 161
153#define PLX9050_REGISTER_INTERRUPT_CONTROL 0x4c
154
155#define PLX9050_LINTI1_ENABLE (1 << 0)
156#define PLX9050_LINTI1_ACTIVE_HIGH (1 << 1)
157#define PLX9050_LINTI1_STATUS (1 << 2)
158#define PLX9050_LINTI2_ENABLE (1 << 3)
159#define PLX9050_LINTI2_ACTIVE_HIGH (1 << 4)
160#define PLX9050_LINTI2_STATUS (1 << 5)
161#define PLX9050_PCI_INTERRUPT_ENABLE (1 << 6)
162#define PLX9050_SOFTWARE_INTERRUPT (1 << 7)
163
164static void plx9050_interrupt_control(unsigned long io_base, 162static void plx9050_interrupt_control(unsigned long io_base,
165 bool LINTi1_enable, 163 bool LINTi1_enable,
166 bool LINTi1_active_high, 164 bool LINTi1_active_high,
@@ -171,18 +169,18 @@ static void plx9050_interrupt_control(unsigned long io_base,
171 int flags = 0; 169 int flags = 0;
172 170
173 if (LINTi1_enable) 171 if (LINTi1_enable)
174 flags |= PLX9050_LINTI1_ENABLE; 172 flags |= PLX9052_INTCSR_LI1ENAB;
175 if (LINTi1_active_high) 173 if (LINTi1_active_high)
176 flags |= PLX9050_LINTI1_ACTIVE_HIGH; 174 flags |= PLX9052_INTCSR_LI1POL;
177 if (LINTi2_enable) 175 if (LINTi2_enable)
178 flags |= PLX9050_LINTI2_ENABLE; 176 flags |= PLX9052_INTCSR_LI2ENAB;
179 if (LINTi2_active_high) 177 if (LINTi2_active_high)
180 flags |= PLX9050_LINTI2_ACTIVE_HIGH; 178 flags |= PLX9052_INTCSR_LI2POL;
181 179
182 if (interrupt_enable) 180 if (interrupt_enable)
183 flags |= PLX9050_PCI_INTERRUPT_ENABLE; 181 flags |= PLX9052_INTCSR_PCIENAB;
184 182
185 outb(flags, io_base + PLX9050_REGISTER_INTERRUPT_CONTROL); 183 outb(flags, io_base + PLX9052_INTCSR);
186} 184}
187 185
188static void pci9111_timer_set(struct comedi_device *dev) 186static void pci9111_timer_set(struct comedi_device *dev)
@@ -607,21 +605,17 @@ static irqreturn_t pci9111_interrupt(int irq, void *p_device)
607 spin_lock_irqsave(&dev->spinlock, irq_flags); 605 spin_lock_irqsave(&dev->spinlock, irq_flags);
608 606
609 /* Check if we are source of interrupt */ 607 /* Check if we are source of interrupt */
610 intcsr = inb(dev_private->lcr_io_base + 608 intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR);
611 PLX9050_REGISTER_INTERRUPT_CONTROL); 609 if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) &&
612 if (!(((intcsr & PLX9050_PCI_INTERRUPT_ENABLE) != 0) 610 (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) ||
613 && (((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) 611 ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) {
614 == (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS))
615 || ((intcsr & (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS))
616 == (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS))))) {
617 /* Not the source of the interrupt. */ 612 /* Not the source of the interrupt. */
618 /* (N.B. not using PLX9050_SOFTWARE_INTERRUPT) */ 613 /* (N.B. not using PLX9052_INTCSR_SOFTINT) */
619 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 614 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
620 return IRQ_NONE; 615 return IRQ_NONE;
621 } 616 }
622 617
623 if ((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) == 618 if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) {
624 (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) {
625 /* Interrupt comes from fifo_half-full signal */ 619 /* Interrupt comes from fifo_half-full signal */
626 620
627 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); 621 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);