diff options
| author | Imre Deak <imre.deak@intel.com> | 2013-02-13 10:27:34 -0500 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-09-24 08:33:15 -0400 |
| commit | fbdcb06880bf414afafd4053d0d9906725f8b117 (patch) | |
| tree | fe29b594b9c49f0804426a5f9340dd34bd1f48dd | |
| parent | 8a8b009d133714c0856ee08f7c68b908103e8383 (diff) | |
drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+
The following sets the AsyncFlip performance mode for everything above
Gen6:
commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Jan 20 16:11:20 2013 +0000
drm/i915: Disable AsyncFlip performance optimisations
Starting from Gen9 the MI_MODE register layout changes and doesn't
include the above bit.
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 109de2eeb9a8..a6a64aee8f74 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
| @@ -823,7 +823,7 @@ static int init_render_ring(struct intel_engine_cs *ring) | |||
| 823 | * | 823 | * |
| 824 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | 824 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
| 825 | */ | 825 | */ |
| 826 | if (INTEL_INFO(dev)->gen >= 6) | 826 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
| 827 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | 827 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 828 | 828 | ||
| 829 | /* Required for the hardware to program scanline values for waiting */ | 829 | /* Required for the hardware to program scanline values for waiting */ |