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authorOlof Johansson <olof@lixom.net>2015-01-23 17:44:16 -0500
committerOlof Johansson <olof@lixom.net>2015-01-23 17:44:16 -0500
commitfba31105a41574b5b45a570d51b3a5475dbb31a5 (patch)
tree13fb74c4adea67ba076075c215f78e1d59951555
parentc6b4916460e66fc6250d3a3c04ef23e2c178736f (diff)
parent16baf8ddd84b36e6880092da777a67de362f8677 (diff)
Merge tag 'imx-dt-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Merge "ARM: imx: device tree changes for 3.20" from Shawn Guo: The i.MX device tree update for 3.20: - Update i.MX6 operating-points setting in device tree to match the latest i.MX6 data sheet - Add i.MX6SX sabreauto board support - Add imx6dl-udoo board support based off imx6q-udoo - Update sabrelite board to include I2C and HDMI support - Update the VPU compatible strings to also use cnm,coda<model> - Remove the ocram clock from the VPU node, as the clock is already provided inside the ocram node - Add system reset controller and syscon-reboot for VF610 - Update VF610 device tree to use zero based naming for GPIO nodes, so that the number scheme matches hardware manual - A number of random device additions like watchdog for VF610, sahara for i.MX53, QSPI for imx6sx-sdb board, etc. Note: the branch imx/soc was merged into imx/dt because the SNVS device tree node needs to refer to the new clock ID added by the imx/soc patch. * tag 'imx-dt-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits) ARM: dts: imx28-evk: remove duplicate property ARM: vf610: use zero based naming for GPIO nodes ARM: dts: imx6q: enable dma for ecspi5 ARM: dts: vfxxx: Add SNVS node ARM: imx: clk-vf610: Add clock for SNVS ARM: imx: clk-vf610: Add clock for UART4 and UART5 ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sx ARM: dts: imx6dl-udoo: Add board support based off imx6q-udoo ARM: imx: support arm power off in cpuidle for i.mx6sx ARM: imx: remove unnecessary setting for DSM ARM: dts: imx6sx: add i.mx6sx sabreauto board support ARM: dts: imx6sx-sdb: Add QSPI support ARM: dts: imx6qdl: Remove OCRAM clock from VPU node ARM: imx: apf51dev: add gpio-backlight support ARM: imx: correct the hardware clock gate setting for shared nodes ARM: imx: pllv3: add shift for frequency multiplier ARM vf610: add compatibilty strings of supported Vybrid SoC's ARM: i.MX53: dts: add sahara module ARM: dts: imx6dl: correct cpufreq volt/freq table ARM: dts: imx6q: update cpufreq volt/freq table ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt12
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts21
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts14
-rw-r--r--arch/arm/boot/dts/imx53.dtsi11
-rw-r--r--arch/arm/boot/dts/imx6dl-udoo.dts18
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts124
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi33
-rw-r--r--arch/arm/boot/dts/imx6qdl-udoo.dtsi134
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6sx-sabreauto.dts146
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts39
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi2
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi3
-rw-r--r--arch/arm/boot/dts/vf500.dtsi23
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts2
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi48
-rw-r--r--arch/arm/mach-imx/Makefile3
-rw-r--r--arch/arm/mach-imx/clk-gate2.c23
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c10
-rw-r--r--arch/arm/mach-imx/clk-vf610.c8
-rw-r--r--arch/arm/mach-imx/clk.h1
-rw-r--r--arch/arm/mach-imx/common.h4
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6sx.c105
-rw-r--r--arch/arm/mach-imx/cpuidle.h5
-rw-r--r--arch/arm/mach-imx/gpc.c25
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c2
-rw-r--r--arch/arm/mach-imx/mach-vf610.c5
-rw-r--r--arch/arm/mach-imx/pm-imx6.c7
-rw-r--r--include/dt-bindings/clock/vf610-clock.h3
34 files changed, 677 insertions, 170 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 4e8b7df7fc62..c830b5b65882 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -75,6 +75,18 @@ i.MX6q generic board
75Required root node properties: 75Required root node properties:
76 - compatible = "fsl,imx6q"; 76 - compatible = "fsl,imx6q";
77 77
78Freescale Vybrid Platform Device Tree Bindings
79----------------------------------------------
80
81For the Vybrid SoC familiy all variants with DDR controller are supported,
82which is the VF5xx and VF6xx series. Out of historical reasons, in most
83places the kernel uses vf610 to refer to the whole familiy.
84
85Required root node compatible property (one of them):
86 - compatible = "fsl,vf500";
87 - compatible = "fsl,vf510";
88 - compatible = "fsl,vf600";
89 - compatible = "fsl,vf610";
78 90
79Freescale LS1021A Platform Device Tree Bindings 91Freescale LS1021A Platform Device Tree Bindings
80------------------------------------------------ 92------------------------------------------------
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 89b732b6d6cf..38e1ec7a81ff 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -273,6 +273,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
273 imx6dl-tx6dl-comtft.dtb \ 273 imx6dl-tx6dl-comtft.dtb \
274 imx6dl-tx6u-801x.dtb \ 274 imx6dl-tx6u-801x.dtb \
275 imx6dl-tx6u-811x.dtb \ 275 imx6dl-tx6u-811x.dtb \
276 imx6dl-udoo.dtb \
276 imx6dl-wandboard.dtb \ 277 imx6dl-wandboard.dtb \
277 imx6dl-wandboard-revb1.dtb \ 278 imx6dl-wandboard-revb1.dtb \
278 imx6q-arm2.dtb \ 279 imx6q-arm2.dtb \
@@ -307,6 +308,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
307dtb-$(CONFIG_SOC_IMX6SL) += \ 308dtb-$(CONFIG_SOC_IMX6SL) += \
308 imx6sl-evk.dtb 309 imx6sl-evk.dtb
309dtb-$(CONFIG_SOC_IMX6SX) += \ 310dtb-$(CONFIG_SOC_IMX6SX) += \
311 imx6sx-sabreauto.dtb \
310 imx6sx-sdb.dtb 312 imx6sx-sdb.dtb
311dtb-$(CONFIG_SOC_LS1021A) += \ 313dtb-$(CONFIG_SOC_LS1021A) += \
312 ls1021a-qds.dtb \ 314 ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index da306c5dd678..bba3f41b89ef 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -59,6 +59,21 @@
59 linux,default-trigger = "heartbeat"; 59 linux,default-trigger = "heartbeat";
60 }; 60 };
61 }; 61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 reg_max5821: regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "max5821-reg";
72 regulator-min-microvolt = <2500000>;
73 regulator-max-microvolt = <2500000>;
74 regulator-always-on;
75 };
76 };
62}; 77};
63 78
64&cspi1 { 79&cspi1 {
@@ -107,6 +122,12 @@
107 compatible = "dallas,ds1374"; 122 compatible = "dallas,ds1374";
108 reg = <0x68>; 123 reg = <0x68>;
109 }; 124 };
125
126 max5821@38 {
127 compatible = "maxim,max5821";
128 reg = <0x38>;
129 vref-supply = <&reg_max5821>;
130 };
110}; 131};
111 132
112&i2c2 { 133&i2c2 {
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 107d713e1cbe..4b063b68db44 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -464,7 +464,7 @@
464 }; 464 };
465 465
466 coda: coda@10023000 { 466 coda: coda@10023000 {
467 compatible = "fsl,imx27-vpu"; 467 compatible = "fsl,imx27-vpu", "cnm,codadx6";
468 reg = <0x10023000 0x0200>; 468 reg = <0x10023000 0x0200>;
469 interrupts = <53>; 469 interrupts = <53>;
470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, 470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 0e13b4b10a92..279249b8c3f3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -182,7 +182,6 @@
182 }; 182 };
183 183
184 lradc@80050000 { 184 lradc@80050000 {
185 fsl,lradc-touchscreen-wires = <4>;
186 status = "okay"; 185 status = "okay";
187 fsl,lradc-touchscreen-wires = <4>; 186 fsl,lradc-touchscreen-wires = <4>;
188 fsl,ave-ctrl = <4>; 187 fsl,ave-ctrl = <4>;
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index c5a9a24c280a..93d3ea12328c 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -16,6 +16,14 @@
16 model = "Armadeus Systems APF51Dev docking/development board"; 16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18 18
19 backlight@bl1{
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_backlight>;
22 compatible = "gpio-backlight";
23 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
24 default-on;
25 };
26
19 display@di1 { 27 display@di1 {
20 compatible = "fsl,imx-parallel-display"; 28 compatible = "fsl,imx-parallel-display";
21 interface-pix-fmt = "bgr666"; 29 interface-pix-fmt = "bgr666";
@@ -114,6 +122,12 @@
114 pinctrl-0 = <&pinctrl_hog>; 122 pinctrl-0 = <&pinctrl_hog>;
115 123
116 imx51-apf51dev { 124 imx51-apf51dev {
125 pinctrl_backlight: bl1grp {
126 fsl,pins = <
127 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
128 >;
129 };
130
117 pinctrl_hog: hoggrp { 131 pinctrl_hog: hoggrp {
118 fsl,pins = < 132 fsl,pins = <
119 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 133 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a30bddfdbdb6..ff4fa7ecacd8 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -756,7 +756,7 @@
756 }; 756 };
757 757
758 vpu: vpu@63ff4000 { 758 vpu: vpu@63ff4000 {
759 compatible = "fsl,imx53-vpu"; 759 compatible = "fsl,imx53-vpu", "cnm,coda7541";
760 reg = <0x63ff4000 0x1000>; 760 reg = <0x63ff4000 0x1000>;
761 interrupts = <9>; 761 interrupts = <9>;
762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
@@ -765,6 +765,15 @@
765 resets = <&src 1>; 765 resets = <&src 1>;
766 iram = <&ocram>; 766 iram = <&ocram>;
767 }; 767 };
768
769 sahara: crypto@63ff8000 {
770 compatible = "fsl,imx53-sahara";
771 reg = <0x63ff8000 0x4000>;
772 interrupts = <19 20>;
773 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
774 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
775 clock-names = "ipg", "ahb";
776 };
768 }; 777 };
769 778
770 ocram: sram@f8000000 { 779 ocram: sram@f8000000 {
diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/imx6dl-udoo.dts
new file mode 100644
index 000000000000..e3713f00e819
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-udoo.dts
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-udoo.dtsi"
14
15/ {
16 model = "Udoo i.MX6 Dual-lite Board";
17 compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
18};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ac2fe732867..f94bf72832af 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -28,7 +28,7 @@
28 next-level-cache = <&L2>; 28 next-level-cache = <&L2>;
29 operating-points = < 29 operating-points = <
30 /* kHz uV */ 30 /* kHz uV */
31 996000 1275000 31 996000 1250000
32 792000 1175000 32 792000 1175000
33 396000 1075000 33 396000 1075000
34 >; 34 >;
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index e3bff2ac00db..c3e64ff3d544 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -8,137 +8,15 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 */ 10 */
11
12/dts-v1/; 11/dts-v1/;
13#include "imx6q.dtsi" 12#include "imx6q.dtsi"
13#include "imx6qdl-udoo.dtsi"
14 14
15/ { 15/ {
16 model = "Udoo i.MX6 Quad Board"; 16 model = "Udoo i.MX6 Quad Board";
17 compatible = "udoo,imx6q-udoo", "fsl,imx6q"; 17 compatible = "udoo,imx6q-udoo", "fsl,imx6q";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 memory {
24 reg = <0x10000000 0x40000000>;
25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb_h1_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 reg = <0>;
35 regulator-name = "usb_h1_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 enable-active-high;
39 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
40 gpio = <&gpio7 12 0>;
41 };
42 };
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet>;
48 phy-mode = "rgmii";
49 status = "okay";
50};
51
52&hdmi {
53 ddc-i2c-bus = <&i2c2>;
54 status = "okay";
55};
56
57&i2c2 {
58 clock-frequency = <100000>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_i2c2>;
61 status = "okay";
62};
63
64&iomuxc {
65 imx6q-udoo {
66 pinctrl_enet: enetgrp {
67 fsl,pins = <
68 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
69 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
70 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
71 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
72 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
73 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
74 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
82 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
83 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
84 >;
85 };
86
87 pinctrl_i2c2: i2c2grp {
88 fsl,pins = <
89 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
90 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
91 >;
92 };
93
94 pinctrl_uart2: uart2grp {
95 fsl,pins = <
96 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
97 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
98 >;
99 };
100
101 pinctrl_usbh: usbhgrp {
102 fsl,pins = <
103 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
104 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
105 >;
106 };
107
108 pinctrl_usdhc3: usdhc3grp {
109 fsl,pins = <
110 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
111 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
112 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
113 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
114 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
115 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
116 >;
117 };
118 };
119}; 18};
120 19
121&sata { 20&sata {
122 status = "okay"; 21 status = "okay";
123}; 22};
124
125&uart2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_uart2>;
128 status = "okay";
129};
130
131&usbh1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh>;
134 vbus-supply = <&reg_usb_h1_vbus>;
135 clocks = <&clks 201>;
136 status = "okay";
137};
138
139&usdhc3 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_usdhc3>;
142 non-removable;
143 status = "okay";
144};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6b5bad..93ec79bb6b35 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -31,7 +31,7 @@
31 1200000 1275000 31 1200000 1275000
32 996000 1250000 32 996000 1250000
33 852000 1250000 33 852000 1250000
34 792000 1150000 34 792000 1175000
35 396000 975000 35 396000 975000
36 >; 36 >;
37 fsl,soc-operating-points = < 37 fsl,soc-operating-points = <
@@ -95,6 +95,8 @@
95 clocks = <&clks IMX6Q_CLK_ECSPI5>, 95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>; 96 <&clks IMX6Q_CLK_ECSPI5>;
97 clock-names = "ipg", "per"; 97 clock-names = "ipg", "per";
98 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
99 dma-names = "rx", "tx";
98 status = "disabled"; 100 status = "disabled";
99 }; 101 };
100 }; 102 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 0a36129152e0..0b28a9d5241e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -173,6 +173,11 @@
173 status = "okay"; 173 status = "okay";
174}; 174};
175 175
176&hdmi {
177 ddc-i2c-bus = <&i2c2>;
178 status = "okay";
179};
180
176&i2c1 { 181&i2c1 {
177 clock-frequency = <100000>; 182 clock-frequency = <100000>;
178 pinctrl-names = "default"; 183 pinctrl-names = "default";
@@ -188,6 +193,20 @@
188 }; 193 };
189}; 194};
190 195
196&i2c2 {
197 clock-frequency = <100000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_i2c2>;
200 status = "okay";
201};
202
203&i2c3 {
204 clock-frequency = <100000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c3>;
207 status = "okay";
208};
209
191&iomuxc { 210&iomuxc {
192 pinctrl-names = "default"; 211 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_hog>; 212 pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +284,20 @@
265 >; 284 >;
266 }; 285 };
267 286
287 pinctrl_i2c2: i2c2grp {
288 fsl,pins = <
289 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
290 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
291 >;
292 };
293
294 pinctrl_i2c3: i2c3grp {
295 fsl,pins = <
296 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
297 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
298 >;
299 };
300
268 pinctrl_pwm1: pwm1grp { 301 pinctrl_pwm1: pwm1grp {
269 fsl,pins = < 302 fsl,pins = <
270 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 303 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
new file mode 100644
index 000000000000..1211da894ee9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 chosen {
14 stdout-path = &uart2;
15 };
16
17 memory {
18 reg = <0x10000000 0x40000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_usb_h1_vbus: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 regulator-name = "usb_h1_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 enable-active-high;
33 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
34 gpio = <&gpio7 12 0>;
35 };
36 };
37};
38
39&fec {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_enet>;
42 phy-mode = "rgmii";
43 status = "okay";
44};
45
46&hdmi {
47 ddc-i2c-bus = <&i2c2>;
48 status = "okay";
49};
50
51&i2c2 {
52 clock-frequency = <100000>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c2>;
55 status = "okay";
56};
57
58&iomuxc {
59 imx6q-udoo {
60 pinctrl_enet: enetgrp {
61 fsl,pins = <
62 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
63 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
64 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
65 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
66 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
67 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
68 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
69 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
70 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
71 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
72 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
73 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
74 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
75 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
76 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
77 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
78 >;
79 };
80
81 pinctrl_i2c2: i2c2grp {
82 fsl,pins = <
83 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
84 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
85 >;
86 };
87
88 pinctrl_uart2: uart2grp {
89 fsl,pins = <
90 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
91 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
92 >;
93 };
94
95 pinctrl_usbh: usbhgrp {
96 fsl,pins = <
97 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
98 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
99 >;
100 };
101
102 pinctrl_usdhc3: usdhc3grp {
103 fsl,pins = <
104 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
105 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
106 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
107 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
108 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
109 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
110 >;
111 };
112 };
113};
114
115&uart2 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
118 status = "okay";
119};
120
121&usbh1 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usbh>;
124 vbus-supply = <&reg_usb_h1_vbus>;
125 clocks = <&clks 201>;
126 status = "okay";
127};
128
129&usdhc3 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_usdhc3>;
132 non-removable;
133 status = "okay";
134};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7f1cee..f6c6a6e1cf3d 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -339,9 +339,8 @@
339 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 12 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg"; 340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
343 <&clks IMX6QDL_CLK_OCRAM>; 343 clock-names = "per", "ahb";
344 clock-names = "per", "ahb", "ocram";
345 resets = <&src 1>; 344 resets = <&src 1>;
346 iram = <&ocram>; 345 iram = <&ocram>;
347 }; 346 };
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
new file mode 100644
index 000000000000..e3c0b63c2205
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -0,0 +1,146 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sx.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloX Sabre Auto Board";
15 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
16
17 memory {
18 reg = <0x80000000 0x80000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 vcc_sd3: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_vcc_sd3>;
31 regulator-name = "VCC_SD3";
32 regulator-min-microvolt = <3000000>;
33 regulator-max-microvolt = <3000000>;
34 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37 };
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_uart1>;
43 status = "okay";
44};
45
46&usdhc3 {
47 pinctrl-names = "default", "state_100mhz", "state_200mhz";
48 pinctrl-0 = <&pinctrl_usdhc3>;
49 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
50 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
51 bus-width = <8>;
52 cd-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
53 wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
54 keep-power-in-suspend;
55 enable-sdio-wakeup;
56 vmmc-supply = <&vcc_sd3>;
57 status = "okay";
58};
59
60&usdhc4 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_usdhc4>;
63 bus-width = <8>;
64 cd-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
65 no-1-8-v;
66 keep-power-in-suspend;
67 enable-sdio-wakup;
68 status = "okay";
69};
70
71&iomuxc {
72 imx6x-sabreauto {
73 pinctrl_uart1: uart1grp {
74 fsl,pins = <
75 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
76 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
77 >;
78 };
79
80 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = <
82 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
83 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
84 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
85 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
86 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
87 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
88 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
89 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
90 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
91 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
92 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
93 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
94 >;
95 };
96
97 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
98 fsl,pins = <
99 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
100 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
101 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
102 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
103 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
104 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
105 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
106 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
107 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
108 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
109 >;
110 };
111
112 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
113 fsl,pins = <
114 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
115 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
116 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
117 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
118 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
119 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
120 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
121 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
122 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
123 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
124 >;
125 };
126
127 pinctrl_usdhc4: usdhc4grp {
128 fsl,pins = <
129 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
130 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
131 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
132 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
133 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
134 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
135 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
136 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
137 >;
138 };
139
140 pinctrl_vcc_sd3: vccsd3grp {
141 fsl,pins = <
142 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
143 >;
144 };
145 };
146};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 1e6e5cc1c14c..cdffe8465c46 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -340,6 +340,28 @@
340 status = "okay"; 340 status = "okay";
341}; 341};
342 342
343&qspi2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_qspi2>;
346 status = "okay";
347
348 flash0: s25fl128s@0 {
349 reg = <0>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352 compatible = "spansion,s25fl128s";
353 spi-max-frequency = <66000000>;
354 };
355
356 flash1: s25fl128s@1 {
357 reg = <1>;
358 #address-cells = <1>;
359 #size-cells = <1>;
360 compatible = "spansion,s25fl128s";
361 spi-max-frequency = <66000000>;
362 };
363};
364
343&ssi2 { 365&ssi2 {
344 status = "okay"; 366 status = "okay";
345}; 367};
@@ -524,6 +546,23 @@
524 >; 546 >;
525 }; 547 };
526 548
549 pinctrl_qspi2: qspi2grp {
550 fsl,pins = <
551 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
552 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
553 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
554 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
555 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
556 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
557 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
558 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
559 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
560 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
561 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
562 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
563 >;
564 };
565
527 pinctrl_vcc_sd3: vccsd3grp { 566 pinctrl_vcc_sd3: vccsd3grp {
528 fsl,pins = < 567 fsl,pins = <
529 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 568 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 56a452bc326c..36cafbfa1bfa 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -35,7 +35,7 @@
35 regulator-name = "usbh_vbus"; 35 regulator-name = "usbh_vbus";
36 regulator-min-microvolt = <5000000>; 36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
39 vin-supply = <&sys_5v0_reg>; 39 vin-supply = <&sys_5v0_reg>;
40 }; 40 };
41 }; 41 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 82f5728be5c9..5c2b7320856d 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -31,7 +31,7 @@
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>; 32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>; 33 bus-width = <4>;
34 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 34 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
35}; 35};
36 36
37&fec1 { 37&fec1 {
@@ -121,6 +121,7 @@
121 121
122 pinctrl_fec1: fec1grp { 122 pinctrl_fec1: fec1grp {
123 fsl,pins = < 123 fsl,pins = <
124 VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
124 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 125 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
125 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 126 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
126 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 127 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index de6700542714..1dbf8d2d1ddf 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -94,23 +94,23 @@
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95}; 95};
96 96
97&gpio1 { 97&gpio0 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99}; 99};
100 100
101&gpio2 { 101&gpio1 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103}; 103};
104 104
105&gpio3 { 105&gpio2 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107}; 107};
108 108
109&gpio4 { 109&gpio3 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111}; 111};
112 112
113&gpio5 { 113&gpio4 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115}; 115};
116 116
@@ -130,6 +130,14 @@
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131}; 131};
132 132
133&snvsrtc {
134 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&src {
138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
139};
140
133&uart0 { 141&uart0 {
134 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
135}; 143};
@@ -169,3 +177,8 @@
169&usbphy1 { 177&usbphy1 {
170 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 178 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
171}; 179};
180
181&wdoga5 {
182 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
183 status = "okay";
184};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index a0f762159cb2..289fef20cd83 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -123,7 +123,7 @@
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1>; 124 pinctrl-0 = <&pinctrl_esdhc1>;
125 bus-width = <4>; 125 bus-width = <4>;
126 cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 126 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
127 status = "okay"; 127 status = "okay";
128}; 128};
129 129
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 505969ae8093..a29c7ce15eaf 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -22,11 +22,11 @@
22 serial3 = &uart3; 22 serial3 = &uart3;
23 serial4 = &uart4; 23 serial4 = &uart4;
24 serial5 = &uart5; 24 serial5 = &uart5;
25 gpio0 = &gpio1; 25 gpio0 = &gpio0;
26 gpio1 = &gpio2; 26 gpio1 = &gpio1;
27 gpio2 = &gpio3; 27 gpio2 = &gpio2;
28 gpio3 = &gpio4; 28 gpio3 = &gpio3;
29 gpio4 = &gpio5; 29 gpio4 = &gpio4;
30 usbphy0 = &usbphy0; 30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1; 31 usbphy1 = &usbphy1;
32 }; 32 };
@@ -43,6 +43,13 @@
43 clock-frequency = <32768>; 43 clock-frequency = <32768>;
44 }; 44 };
45 45
46 reboot: syscon-reboot {
47 compatible = "syscon-reboot";
48 regmap = <&src>;
49 offset = <0x0>;
50 mask = <0x1000>;
51 };
52
46 soc { 53 soc {
47 #address-cells = <1>; 54 #address-cells = <1>;
48 #size-cells = <1>; 55 #size-cells = <1>;
@@ -184,7 +191,7 @@
184 status = "disabled"; 191 status = "disabled";
185 }; 192 };
186 193
187 wdog@4003e000 { 194 wdoga5: wdog@4003e000 {
188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>; 196 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>; 197 clocks = <&clks VF610_CLK_WDT>;
@@ -209,7 +216,7 @@
209 #gpio-range-cells = <3>; 216 #gpio-range-cells = <3>;
210 }; 217 };
211 218
212 gpio1: gpio@40049000 { 219 gpio0: gpio@40049000 {
213 compatible = "fsl,vf610-gpio"; 220 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>; 221 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller; 222 gpio-controller;
@@ -219,7 +226,7 @@
219 gpio-ranges = <&iomuxc 0 0 32>; 226 gpio-ranges = <&iomuxc 0 0 32>;
220 }; 227 };
221 228
222 gpio2: gpio@4004a000 { 229 gpio1: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio"; 230 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 231 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller; 232 gpio-controller;
@@ -229,7 +236,7 @@
229 gpio-ranges = <&iomuxc 0 32 32>; 236 gpio-ranges = <&iomuxc 0 32 32>;
230 }; 237 };
231 238
232 gpio3: gpio@4004b000 { 239 gpio2: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio"; 240 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 241 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller; 242 gpio-controller;
@@ -239,7 +246,7 @@
239 gpio-ranges = <&iomuxc 0 64 32>; 246 gpio-ranges = <&iomuxc 0 64 32>;
240 }; 247 };
241 248
242 gpio4: gpio@4004c000 { 249 gpio3: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio"; 250 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller; 252 gpio-controller;
@@ -249,7 +256,7 @@
249 gpio-ranges = <&iomuxc 0 96 32>; 256 gpio-ranges = <&iomuxc 0 96 32>;
250 }; 257 };
251 258
252 gpio5: gpio@4004d000 { 259 gpio4: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio"; 260 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 261 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller; 262 gpio-controller;
@@ -318,6 +325,11 @@
318 clocks = <&clks VF610_CLK_USBC0>; 325 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled"; 326 status = "disabled";
320 }; 327 };
328
329 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>;
332 };
321 }; 333 };
322 334
323 aips1: aips-bus@40080000 { 335 aips1: aips-bus@40080000 {
@@ -339,6 +351,20 @@
339 status = "disabled"; 351 status = "disabled";
340 }; 352 };
341 353
354 snvs0: snvs@400a7000 {
355 compatible = "fsl,sec-v4.0-mon", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0x400a7000 0x2000>;
359
360 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>;
363 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc";
365 };
366 };
367
342 uart4: serial@400a9000 { 368 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart"; 369 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>; 370 reg = <0x400a9000 0x1000>;
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5ac685a29fc..8d1b10180908 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
32obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o 32obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
33obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o 33obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
34obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o 34obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
35# i.MX6SX reuses i.MX6Q cpuidle driver 35obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
36obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
37endif 36endif
38 37
39ifdef CONFIG_SND_IMX_SOC 38ifdef CONFIG_SND_IMX_SOC
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 5a75cdc81891..8935bff99fe7 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
96{ 96{
97 struct clk_gate2 *gate = to_clk_gate2(hw); 97 struct clk_gate2 *gate = to_clk_gate2(hw);
98 98
99 if (gate->share_count) 99 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
100 return !!__clk_get_enable_count(hw->clk); 100}
101 else 101
102 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); 102static void clk_gate2_disable_unused(struct clk_hw *hw)
103{
104 struct clk_gate2 *gate = to_clk_gate2(hw);
105 unsigned long flags = 0;
106 u32 reg;
107
108 spin_lock_irqsave(gate->lock, flags);
109
110 if (!gate->share_count || *gate->share_count == 0) {
111 reg = readl(gate->reg);
112 reg &= ~(3 << gate->bit_idx);
113 writel(reg, gate->reg);
114 }
115
116 spin_unlock_irqrestore(gate->lock, flags);
103} 117}
104 118
105static struct clk_ops clk_gate2_ops = { 119static struct clk_ops clk_gate2_ops = {
106 .enable = clk_gate2_enable, 120 .enable = clk_gate2_enable,
107 .disable = clk_gate2_disable, 121 .disable = clk_gate2_disable,
122 .disable_unused = clk_gate2_disable_unused,
108 .is_enabled = clk_gate2_is_enabled, 123 .is_enabled = clk_gate2_is_enabled,
109}; 124};
110 125
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 0ad6e5442fd8..641ebc508920 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,6 +31,7 @@
31 * @base: base address of PLL registers 31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL 32 * @powerup_set: set POWER bit to power up the PLL
33 * @div_mask: mask of divider bits 33 * @div_mask: mask of divider bits
34 * @div_shift: shift of divider bits
34 * 35 *
35 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
36 * is actually a multiplier, and always sits at bit 0. 37 * is actually a multiplier, and always sits at bit 0.
@@ -40,6 +41,7 @@ struct clk_pllv3 {
40 void __iomem *base; 41 void __iomem *base;
41 bool powerup_set; 42 bool powerup_set;
42 u32 div_mask; 43 u32 div_mask;
44 u32 div_shift;
43}; 45};
44 46
45#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 47#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
97 unsigned long parent_rate) 99 unsigned long parent_rate)
98{ 100{
99 struct clk_pllv3 *pll = to_clk_pllv3(hw); 101 struct clk_pllv3 *pll = to_clk_pllv3(hw);
100 u32 div = readl_relaxed(pll->base) & pll->div_mask; 102 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
101 103
102 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 104 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
103} 105}
@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
125 return -EINVAL; 127 return -EINVAL;
126 128
127 val = readl_relaxed(pll->base); 129 val = readl_relaxed(pll->base);
128 val &= ~pll->div_mask; 130 val &= ~(pll->div_mask << pll->div_shift);
129 val |= div; 131 val |= (div << pll->div_shift);
130 writel_relaxed(val, pll->base); 132 writel_relaxed(val, pll->base);
131 133
132 return clk_pllv3_wait_lock(pll); 134 return clk_pllv3_wait_lock(pll);
@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
295 case IMX_PLLV3_SYS: 297 case IMX_PLLV3_SYS:
296 ops = &clk_pllv3_sys_ops; 298 ops = &clk_pllv3_sys_ops;
297 break; 299 break;
300 case IMX_PLLV3_USB_VF610:
301 pll->div_shift = 1;
298 case IMX_PLLV3_USB: 302 case IMX_PLLV3_USB:
299 ops = &clk_pllv3_ops; 303 ops = &clk_pllv3_ops;
300 pll->powerup_set = true; 304 pll->powerup_set = true;
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index 5937ddee1a99..61876ed6e11e 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
172 172
173 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); 173 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
174 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); 174 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
175 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1); 175 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);
176 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); 176 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
177 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); 177 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
178 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); 178 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
179 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1); 179 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2);
180 180
181 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 181 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
182 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 182 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
@@ -267,6 +267,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
267 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); 267 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
268 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); 268 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
269 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); 269 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
270 clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9));
271 clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10));
270 272
271 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); 273 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
272 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); 274 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
@@ -380,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
380 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); 382 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
381 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); 383 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
382 384
385 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
386
383 imx_check_clocks(clk, ARRAY_SIZE(clk)); 387 imx_check_clocks(clk, ARRAY_SIZE(clk));
384 388
385 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); 389 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 5ef82e2f8fc5..6a07903a28bc 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -20,6 +20,7 @@ enum imx_pllv3_type {
20 IMX_PLLV3_GENERIC, 20 IMX_PLLV3_GENERIC,
21 IMX_PLLV3_SYS, 21 IMX_PLLV3_SYS,
22 IMX_PLLV3_USB, 22 IMX_PLLV3_USB,
23 IMX_PLLV3_USB_VF610,
23 IMX_PLLV3_AV, 24 IMX_PLLV3_AV,
24 IMX_PLLV3_ENET, 25 IMX_PLLV3_ENET,
25}; 26};
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cfcdb623d78f..1028b6c505c4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -70,6 +70,10 @@ void imx_set_soc_revision(unsigned int rev);
70unsigned int imx_get_soc_revision(void); 70unsigned int imx_get_soc_revision(void);
71void imx_init_revision_from_anatop(void); 71void imx_init_revision_from_anatop(void);
72struct device *imx_soc_device_init(void); 72struct device *imx_soc_device_init(void);
73void imx6_enable_rbc(bool enable);
74void imx_gpc_set_arm_power_in_lpm(bool power_off);
75void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
76void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
73 77
74enum mxc_cpu_pwr_mode { 78enum mxc_cpu_pwr_mode {
75 WAIT_CLOCKED, /* wfi only */ 79 WAIT_CLOCKED, /* wfi only */
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c
new file mode 100644
index 000000000000..5a36722b089d
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/cpuidle.h>
10#include <linux/cpu_pm.h>
11#include <linux/module.h>
12#include <asm/cpuidle.h>
13#include <asm/proc-fns.h>
14#include <asm/suspend.h>
15
16#include "common.h"
17#include "cpuidle.h"
18
19static int imx6sx_idle_finish(unsigned long val)
20{
21 cpu_do_idle();
22
23 return 0;
24}
25
26static int imx6sx_enter_wait(struct cpuidle_device *dev,
27 struct cpuidle_driver *drv, int index)
28{
29 imx6q_set_lpm(WAIT_UNCLOCKED);
30
31 switch (index) {
32 case 1:
33 cpu_do_idle();
34 break;
35 case 2:
36 imx6_enable_rbc(true);
37 imx_gpc_set_arm_power_in_lpm(true);
38 imx_set_cpu_jump(0, v7_cpu_resume);
39 /* Need to notify there is a cpu pm operation. */
40 cpu_pm_enter();
41 cpu_cluster_pm_enter();
42
43 cpu_suspend(0, imx6sx_idle_finish);
44
45 cpu_cluster_pm_exit();
46 cpu_pm_exit();
47 imx_gpc_set_arm_power_in_lpm(false);
48 imx6_enable_rbc(false);
49 break;
50 default:
51 break;
52 }
53
54 imx6q_set_lpm(WAIT_CLOCKED);
55
56 return index;
57}
58
59static struct cpuidle_driver imx6sx_cpuidle_driver = {
60 .name = "imx6sx_cpuidle",
61 .owner = THIS_MODULE,
62 .states = {
63 /* WFI */
64 ARM_CPUIDLE_WFI_STATE,
65 /* WAIT */
66 {
67 .exit_latency = 50,
68 .target_residency = 75,
69 .flags = CPUIDLE_FLAG_TIMER_STOP,
70 .enter = imx6sx_enter_wait,
71 .name = "WAIT",
72 .desc = "Clock off",
73 },
74 /* WAIT + ARM power off */
75 {
76 /*
77 * ARM gating 31us * 5 + RBC clear 65us
78 * and some margin for SW execution, here set it
79 * to 300us.
80 */
81 .exit_latency = 300,
82 .target_residency = 500,
83 .enter = imx6sx_enter_wait,
84 .name = "LOW-POWER-IDLE",
85 .desc = "ARM power off",
86 },
87 },
88 .state_count = 3,
89 .safe_state_index = 0,
90};
91
92int __init imx6sx_cpuidle_init(void)
93{
94 imx6_enable_rbc(false);
95 /*
96 * set ARM power up/down timing to the fastest,
97 * sw2iso and sw can be set to one 32K cycle = 31us
98 * except for power up sw2iso which need to be
99 * larger than LDO ramp up time.
100 */
101 imx_gpc_set_arm_power_up_timing(2, 1);
102 imx_gpc_set_arm_power_down_timing(1, 1);
103
104 return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
105}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index 24e33670417c..f9140128ba05 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -14,6 +14,7 @@
14extern int imx5_cpuidle_init(void); 14extern int imx5_cpuidle_init(void);
15extern int imx6q_cpuidle_init(void); 15extern int imx6q_cpuidle_init(void);
16extern int imx6sl_cpuidle_init(void); 16extern int imx6sl_cpuidle_init(void);
17extern int imx6sx_cpuidle_init(void);
17#else 18#else
18static inline int imx5_cpuidle_init(void) 19static inline int imx5_cpuidle_init(void)
19{ 20{
@@ -27,4 +28,8 @@ static inline int imx6sl_cpuidle_init(void)
27{ 28{
28 return 0; 29 return 0;
29} 30}
31static inline int imx6sx_cpuidle_init(void)
32{
33 return 0;
34}
30#endif 35#endif
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 5f3602ec74fa..745caa18ab2c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -20,6 +20,10 @@
20 20
21#define GPC_IMR1 0x008 21#define GPC_IMR1 0x008
22#define GPC_PGC_CPU_PDN 0x2a0 22#define GPC_PGC_CPU_PDN 0x2a0
23#define GPC_PGC_CPU_PUPSCR 0x2a4
24#define GPC_PGC_CPU_PDNSCR 0x2a8
25#define GPC_PGC_SW2ISO_SHIFT 0x8
26#define GPC_PGC_SW_SHIFT 0x0
23 27
24#define IMR_NUM 4 28#define IMR_NUM 4
25 29
@@ -27,6 +31,23 @@ static void __iomem *gpc_base;
27static u32 gpc_wake_irqs[IMR_NUM]; 31static u32 gpc_wake_irqs[IMR_NUM];
28static u32 gpc_saved_imrs[IMR_NUM]; 32static u32 gpc_saved_imrs[IMR_NUM];
29 33
34void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
35{
36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
37 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
38}
39
40void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
41{
42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
43 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
44}
45
46void imx_gpc_set_arm_power_in_lpm(bool power_off)
47{
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
49}
50
30void imx_gpc_pre_suspend(bool arm_power_off) 51void imx_gpc_pre_suspend(bool arm_power_off)
31{ 52{
32 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 53 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
@@ -34,7 +55,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
34 55
35 /* Tell GPC to power off ARM core when suspend */ 56 /* Tell GPC to power off ARM core when suspend */
36 if (arm_power_off) 57 if (arm_power_off)
37 writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); 58 imx_gpc_set_arm_power_in_lpm(arm_power_off);
38 59
39 for (i = 0; i < IMR_NUM; i++) { 60 for (i = 0; i < IMR_NUM; i++) {
40 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 61 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
@@ -48,7 +69,7 @@ void imx_gpc_post_resume(void)
48 int i; 69 int i;
49 70
50 /* Keep ARM core powered on for other low-power modes */ 71 /* Keep ARM core powered on for other low-power modes */
51 writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); 72 imx_gpc_set_arm_power_in_lpm(false);
52 73
53 for (i = 0; i < IMR_NUM; i++) 74 for (i = 0; i < IMR_NUM; i++)
54 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 75 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 7a96c6577234..66988eb6a3a4 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -90,7 +90,7 @@ static void __init imx6sx_init_irq(void)
90 90
91static void __init imx6sx_init_late(void) 91static void __init imx6sx_init_late(void)
92{ 92{
93 imx6q_cpuidle_init(); 93 imx6sx_cpuidle_init();
94 94
95 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) 95 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
96 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); 96 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index c11ab6a1dc87..2e7c75b66fe0 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -13,11 +13,14 @@
13#include <asm/hardware/cache-l2x0.h> 13#include <asm/hardware/cache-l2x0.h>
14 14
15static const char * const vf610_dt_compat[] __initconst = { 15static const char * const vf610_dt_compat[] __initconst = {
16 "fsl,vf500",
17 "fsl,vf510",
18 "fsl,vf600",
16 "fsl,vf610", 19 "fsl,vf610",
17 NULL, 20 NULL,
18}; 21};
19 22
20DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") 23DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
21 .l2c_aux_val = 0, 24 .l2c_aux_val = 0,
22 .l2c_aux_mask = ~0, 25 .l2c_aux_mask = ~0,
23 .dt_compat = vf610_dt_compat, 26 .dt_compat = vf610_dt_compat,
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 5d2c1bd5f5ef..46fd695203c7 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -205,7 +205,7 @@ void imx6q_set_int_mem_clk_lpm(bool enable)
205 writel_relaxed(val, ccm_base + CGPR); 205 writel_relaxed(val, ccm_base + CGPR);
206} 206}
207 207
208static void imx6q_enable_rbc(bool enable) 208void imx6_enable_rbc(bool enable)
209{ 209{
210 u32 val; 210 u32 val;
211 211
@@ -359,17 +359,16 @@ static int imx6q_pm_enter(suspend_state_t state)
359 * RBC setting, so we do NOT need to do that here. 359 * RBC setting, so we do NOT need to do that here.
360 */ 360 */
361 if (!imx6_suspend_in_ocram_fn) 361 if (!imx6_suspend_in_ocram_fn)
362 imx6q_enable_rbc(true); 362 imx6_enable_rbc(true);
363 imx_gpc_pre_suspend(true); 363 imx_gpc_pre_suspend(true);
364 imx_anatop_pre_suspend(); 364 imx_anatop_pre_suspend();
365 imx_set_cpu_jump(0, v7_cpu_resume);
366 /* Zzz ... */ 365 /* Zzz ... */
367 cpu_suspend(0, imx6q_suspend_finish); 366 cpu_suspend(0, imx6q_suspend_finish);
368 if (cpu_is_imx6q() || cpu_is_imx6dl()) 367 if (cpu_is_imx6q() || cpu_is_imx6dl())
369 imx_smp_prepare(); 368 imx_smp_prepare();
370 imx_anatop_post_resume(); 369 imx_anatop_post_resume();
371 imx_gpc_post_resume(); 370 imx_gpc_post_resume();
372 imx6q_enable_rbc(false); 371 imx6_enable_rbc(false);
373 imx6q_enable_wb(false); 372 imx6q_enable_wb(false);
374 imx6q_set_int_mem_clk_lpm(true); 373 imx6q_set_int_mem_clk_lpm(true);
375 imx6q_set_lpm(WAIT_CLOCKED); 374 imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 801c0ac50c47..979d24a6799f 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -192,6 +192,7 @@
192#define VF610_PLL5_BYPASS 179 192#define VF610_PLL5_BYPASS 179
193#define VF610_PLL6_BYPASS 180 193#define VF610_PLL6_BYPASS 180
194#define VF610_PLL7_BYPASS 181 194#define VF610_PLL7_BYPASS 181
195#define VF610_CLK_END 182 195#define VF610_CLK_SNVS 182
196#define VF610_CLK_END 183
196 197
197#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 198#endif /* __DT_BINDINGS_CLOCK_VF610_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 10:27:05 -0400