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authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2013-11-06 20:21:07 -0500
committerPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2013-11-08 10:22:12 -0500
commitfb8e34d561d58297af06b7350d9fdcafced8e1c5 (patch)
treee5455c0f9cd1ab19267233cd5ceb83e1b4e39606
parent5aac788323dfdd61a6be31734170d644e5d7cb4f (diff)
drm/gma500/mrst: Add aux register writes to SDVO
This turned out to be tricky. Writing to SDVOB on the primary vdc also writes to SDVOB on the aux vdc, but reading it back on the primary vdc always fails. Basically we never read from the primary vdc since we will end up trashing the aux vdc. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_sdvo.c59
1 files changed, 38 insertions, 21 deletions
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index 6f01cdf5e125..07d3a9e6d79b 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -228,24 +228,26 @@ static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u3
228{ 228{
229 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 229 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
230 u32 bval = val, cval = val; 230 u32 bval = val, cval = val;
231 int i; 231 int i, j;
232 int need_aux = IS_MRST(dev) ? 1 : 0;
232 233
233 if (psb_intel_sdvo->sdvo_reg == SDVOB) { 234 for (j = 0; j <= need_aux; j++) {
234 cval = REG_READ(SDVOC); 235 if (psb_intel_sdvo->sdvo_reg == SDVOB)
235 } else { 236 cval = REG_READ_WITH_AUX(SDVOC, j);
236 bval = REG_READ(SDVOB); 237 else
237 } 238 bval = REG_READ_WITH_AUX(SDVOB, j);
238 /* 239
239 * Write the registers twice for luck. Sometimes, 240 /*
240 * writing them only once doesn't appear to 'stick'. 241 * Write the registers twice for luck. Sometimes,
241 * The BIOS does this too. Yay, magic 242 * writing them only once doesn't appear to 'stick'.
242 */ 243 * The BIOS does this too. Yay, magic
243 for (i = 0; i < 2; i++) 244 */
244 { 245 for (i = 0; i < 2; i++) {
245 REG_WRITE(SDVOB, bval); 246 REG_WRITE_WITH_AUX(SDVOB, bval, j);
246 REG_READ(SDVOB); 247 REG_READ_WITH_AUX(SDVOB, j);
247 REG_WRITE(SDVOC, cval); 248 REG_WRITE_WITH_AUX(SDVOC, cval, j);
248 REG_READ(SDVOC); 249 REG_READ_WITH_AUX(SDVOC, j);
250 }
249 } 251 }
250} 252}
251 253
@@ -995,6 +997,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
995 struct psb_intel_sdvo_dtd input_dtd; 997 struct psb_intel_sdvo_dtd input_dtd;
996 int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode); 998 int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
997 int rate; 999 int rate;
1000 int need_aux = IS_MRST(dev) ? 1 : 0;
998 1001
999 if (!mode) 1002 if (!mode)
1000 return; 1003 return;
@@ -1060,7 +1063,11 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
1060 return; 1063 return;
1061 1064
1062 /* Set the SDVO control regs. */ 1065 /* Set the SDVO control regs. */
1063 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); 1066 if (need_aux)
1067 sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1068 else
1069 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
1070
1064 switch (psb_intel_sdvo->sdvo_reg) { 1071 switch (psb_intel_sdvo->sdvo_reg) {
1065 case SDVOB: 1072 case SDVOB:
1066 sdvox &= SDVOB_PRESERVE_MASK; 1073 sdvox &= SDVOB_PRESERVE_MASK;
@@ -1090,6 +1097,8 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1090 struct drm_device *dev = encoder->dev; 1097 struct drm_device *dev = encoder->dev;
1091 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 1098 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
1092 u32 temp; 1099 u32 temp;
1100 int i;
1101 int need_aux = IS_MRST(dev) ? 1 : 0;
1093 1102
1094 switch (mode) { 1103 switch (mode) {
1095 case DRM_MODE_DPMS_ON: 1104 case DRM_MODE_DPMS_ON:
@@ -1108,19 +1117,27 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1108 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); 1117 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
1109 1118
1110 if (mode == DRM_MODE_DPMS_OFF) { 1119 if (mode == DRM_MODE_DPMS_OFF) {
1111 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1120 if (need_aux)
1121 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1122 else
1123 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
1124
1112 if ((temp & SDVO_ENABLE) != 0) { 1125 if ((temp & SDVO_ENABLE) != 0) {
1113 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE); 1126 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
1114 } 1127 }
1115 } 1128 }
1116 } else { 1129 } else {
1117 bool input1, input2; 1130 bool input1, input2;
1118 int i;
1119 u8 status; 1131 u8 status;
1120 1132
1121 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1133 if (need_aux)
1134 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1135 else
1136 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
1137
1122 if ((temp & SDVO_ENABLE) == 0) 1138 if ((temp & SDVO_ENABLE) == 0)
1123 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); 1139 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
1140
1124 for (i = 0; i < 2; i++) 1141 for (i = 0; i < 2; i++)
1125 gma_wait_for_vblank(dev); 1142 gma_wait_for_vblank(dev);
1126 1143