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authorfrançois romieu <romieu@fr.zoreil.com>2013-02-27 08:01:57 -0500
committerDavid S. Miller <davem@davemloft.net>2013-02-28 15:37:29 -0500
commitfaf1e7857a1b87cd8baf48c3e962142e21ad417c (patch)
tree9e9a5c952312d31e124ad2e708b4ccce2a8e12b8
parent79ffef1fe213851f44bfccf037170a140e929f85 (diff)
r8169: honor jumbo settings when chipset is requested to start.
Some hardware start settings implicitely assume an usual 1500 bytes mtu that can't be guaranteed because changes of mtu may be requested both before and after the hardware is started. Reported-by: Tomi Orava <tomimo@ncircle.nullnet.fi> Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/realtek/r8169.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 8900398ba103..28fb50a1e9c3 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -4765,8 +4765,10 @@ static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4765 4765
4766 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 4766 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4767 4767
4768 rtl_tx_performance_tweak(pdev, 4768 if (tp->dev->mtu <= ETH_DATA_LEN) {
4769 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); 4769 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4770 PCI_EXP_DEVCTL_NOSNOOP_EN);
4771 }
4770} 4772}
4771 4773
4772static void rtl_hw_start_8168bef(struct rtl8169_private *tp) 4774static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
@@ -4789,7 +4791,8 @@ static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4789 4791
4790 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 4792 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4791 4793
4792 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4794 if (tp->dev->mtu <= ETH_DATA_LEN)
4795 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4793 4796
4794 rtl_disable_clock_request(pdev); 4797 rtl_disable_clock_request(pdev);
4795 4798
@@ -4822,7 +4825,8 @@ static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4822 4825
4823 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 4826 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4824 4827
4825 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4828 if (tp->dev->mtu <= ETH_DATA_LEN)
4829 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4826 4830
4827 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 4831 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4828} 4832}
@@ -4841,7 +4845,8 @@ static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4841 4845
4842 RTL_W8(MaxTxPacketSize, TxPacketMax); 4846 RTL_W8(MaxTxPacketSize, TxPacketMax);
4843 4847
4844 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4848 if (tp->dev->mtu <= ETH_DATA_LEN)
4849 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4845 4850
4846 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 4851 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4847} 4852}
@@ -4901,7 +4906,8 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4901 4906
4902 RTL_W8(MaxTxPacketSize, TxPacketMax); 4907 RTL_W8(MaxTxPacketSize, TxPacketMax);
4903 4908
4904 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4909 if (tp->dev->mtu <= ETH_DATA_LEN)
4910 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4905 4911
4906 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 4912 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4907} 4913}
@@ -4913,7 +4919,8 @@ static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4913 4919
4914 rtl_csi_access_enable_1(tp); 4920 rtl_csi_access_enable_1(tp);
4915 4921
4916 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4922 if (tp->dev->mtu <= ETH_DATA_LEN)
4923 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4917 4924
4918 RTL_W8(MaxTxPacketSize, TxPacketMax); 4925 RTL_W8(MaxTxPacketSize, TxPacketMax);
4919 4926
@@ -4972,7 +4979,8 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4972 4979
4973 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); 4980 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4974 4981
4975 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4982 if (tp->dev->mtu <= ETH_DATA_LEN)
4983 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4976 4984
4977 RTL_W8(MaxTxPacketSize, TxPacketMax); 4985 RTL_W8(MaxTxPacketSize, TxPacketMax);
4978 4986
@@ -4998,7 +5006,8 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4998 5006
4999 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); 5007 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5000 5008
5001 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 5009 if (tp->dev->mtu <= ETH_DATA_LEN)
5010 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5002 5011
5003 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); 5012 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5004 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); 5013 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);