diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-11-29 03:34:02 -0500 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-11-29 03:34:02 -0500 |
| commit | fa1f94979883aeef231fa023e5b9be971d459952 (patch) | |
| tree | d06f817560313c7ba1d1109fb3481dab7bdd42c7 | |
| parent | 0074120228496d6fceb75ba17d21dc0b7476f8c4 (diff) | |
| parent | 5a9c30a32dd187344cb966db3016861b6b385384 (diff) | |
Merge branch 'samsung-fb-next' of git://github.com/jingoo/linux into for-linus
Samsung Framebuffer changes for the 3.8 merge window.
- The bit definitions of header file are updated.
- Some minor typos are fixed.
- Some minor bugs of s3c_fb_check_var() are fixed.
* 'samsung-fb-next' of git://github.com/jingoo/linux:
video: s3c-fb: fix red offset and length for ARGB232 format
video: s3c-fb: return an error when bpp is invalid
video: s3c-fb: add "drop through" comment
video: s3c-fb: use dev_get_drvdata() instead of platform_get_drvdata()
video: s3c-fb: use FIMD_V8_VIDTCON0 for EXYNOS5 FIMD
video: s3c-fb: fix help message for FB_S3C_DEBUG_REGWRITE
video: s3c-fb: fix typo in comment
video: s3c-fb: add the bit definitions for VIDCON0_VIDOUT_WB
video: s3c-fb: move the bit definitions for DITHMODE register
video: s3c-fb: move the bit definitions for WINxMAP and WPALCON register
video: s3c-fb: move the bit definitions for VIDINTCON0 register
video: s3c-fb: move the address definition for VIDOSD register
video: s3c-fb: move the address definitions for VIDTCON registers
video: s3c-fb: clean the bit definition for WINCON register
| -rw-r--r-- | drivers/video/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/video/s3c-fb.c | 24 | ||||
| -rw-r--r-- | include/video/samsung_fimd.h | 168 |
3 files changed, 64 insertions, 130 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d08d7998a4aa..9018a90b4588 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
| @@ -2045,7 +2045,7 @@ config FB_S3C_DEBUG_REGWRITE | |||
| 2045 | bool "Debug register writes" | 2045 | bool "Debug register writes" |
| 2046 | depends on FB_S3C | 2046 | depends on FB_S3C |
| 2047 | ---help--- | 2047 | ---help--- |
| 2048 | Show all register writes via printk(KERN_DEBUG) | 2048 | Show all register writes via pr_debug() |
| 2049 | 2049 | ||
| 2050 | config FB_S3C2410 | 2050 | config FB_S3C2410 |
| 2051 | tristate "S3C2410 LCD framebuffer support" | 2051 | tristate "S3C2410 LCD framebuffer support" |
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 2ed7b633bbd9..1a00ad241edd 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c | |||
| @@ -189,7 +189,7 @@ struct s3c_fb_vsync { | |||
| 189 | 189 | ||
| 190 | /** | 190 | /** |
| 191 | * struct s3c_fb - overall hardware state of the hardware | 191 | * struct s3c_fb - overall hardware state of the hardware |
| 192 | * @slock: The spinlock protection for this data sturucture. | 192 | * @slock: The spinlock protection for this data structure. |
| 193 | * @dev: The device that we bound to, for printing, etc. | 193 | * @dev: The device that we bound to, for printing, etc. |
| 194 | * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk. | 194 | * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk. |
| 195 | * @lcd_clk: The clk (sclk) feeding pixclk. | 195 | * @lcd_clk: The clk (sclk) feeding pixclk. |
| @@ -268,10 +268,10 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var, | |||
| 268 | case 8: | 268 | case 8: |
| 269 | if (sfb->variant.palette[win->index] != 0) { | 269 | if (sfb->variant.palette[win->index] != 0) { |
| 270 | /* non palletised, A:1,R:2,G:3,B:2 mode */ | 270 | /* non palletised, A:1,R:2,G:3,B:2 mode */ |
| 271 | var->red.offset = 4; | 271 | var->red.offset = 5; |
| 272 | var->green.offset = 2; | 272 | var->green.offset = 2; |
| 273 | var->blue.offset = 0; | 273 | var->blue.offset = 0; |
| 274 | var->red.length = 5; | 274 | var->red.length = 2; |
| 275 | var->green.length = 3; | 275 | var->green.length = 3; |
| 276 | var->blue.length = 2; | 276 | var->blue.length = 2; |
| 277 | var->transp.offset = 7; | 277 | var->transp.offset = 7; |
| @@ -288,6 +288,7 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var, | |||
| 288 | /* 666 with one bit alpha/transparency */ | 288 | /* 666 with one bit alpha/transparency */ |
| 289 | var->transp.offset = 18; | 289 | var->transp.offset = 18; |
| 290 | var->transp.length = 1; | 290 | var->transp.length = 1; |
| 291 | /* drop through */ | ||
| 291 | case 18: | 292 | case 18: |
| 292 | var->bits_per_pixel = 32; | 293 | var->bits_per_pixel = 32; |
| 293 | 294 | ||
| @@ -329,6 +330,7 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var, | |||
| 329 | 330 | ||
| 330 | default: | 331 | default: |
| 331 | dev_err(sfb->dev, "invalid bpp\n"); | 332 | dev_err(sfb->dev, "invalid bpp\n"); |
| 333 | return -EINVAL; | ||
| 332 | } | 334 | } |
| 333 | 335 | ||
| 334 | dev_dbg(sfb->dev, "%s: verified parameters\n", __func__); | 336 | dev_dbg(sfb->dev, "%s: verified parameters\n", __func__); |
| @@ -1544,8 +1546,7 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev) | |||
| 1544 | #ifdef CONFIG_PM_SLEEP | 1546 | #ifdef CONFIG_PM_SLEEP |
| 1545 | static int s3c_fb_suspend(struct device *dev) | 1547 | static int s3c_fb_suspend(struct device *dev) |
| 1546 | { | 1548 | { |
| 1547 | struct platform_device *pdev = to_platform_device(dev); | 1549 | struct s3c_fb *sfb = dev_get_drvdata(dev); |
| 1548 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | ||
| 1549 | struct s3c_fb_win *win; | 1550 | struct s3c_fb_win *win; |
| 1550 | int win_no; | 1551 | int win_no; |
| 1551 | 1552 | ||
| @@ -1572,8 +1573,7 @@ static int s3c_fb_suspend(struct device *dev) | |||
| 1572 | 1573 | ||
| 1573 | static int s3c_fb_resume(struct device *dev) | 1574 | static int s3c_fb_resume(struct device *dev) |
| 1574 | { | 1575 | { |
| 1575 | struct platform_device *pdev = to_platform_device(dev); | 1576 | struct s3c_fb *sfb = dev_get_drvdata(dev); |
| 1576 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | ||
| 1577 | struct s3c_fb_platdata *pd = sfb->pdata; | 1577 | struct s3c_fb_platdata *pd = sfb->pdata; |
| 1578 | struct s3c_fb_win *win; | 1578 | struct s3c_fb_win *win; |
| 1579 | int win_no; | 1579 | int win_no; |
| @@ -1623,7 +1623,7 @@ static int s3c_fb_resume(struct device *dev) | |||
| 1623 | if (!win) | 1623 | if (!win) |
| 1624 | continue; | 1624 | continue; |
| 1625 | 1625 | ||
| 1626 | dev_dbg(&pdev->dev, "resuming window %d\n", win_no); | 1626 | dev_dbg(dev, "resuming window %d\n", win_no); |
| 1627 | s3c_fb_set_par(win->fbinfo); | 1627 | s3c_fb_set_par(win->fbinfo); |
| 1628 | } | 1628 | } |
| 1629 | 1629 | ||
| @@ -1636,8 +1636,7 @@ static int s3c_fb_resume(struct device *dev) | |||
| 1636 | #ifdef CONFIG_PM_RUNTIME | 1636 | #ifdef CONFIG_PM_RUNTIME |
| 1637 | static int s3c_fb_runtime_suspend(struct device *dev) | 1637 | static int s3c_fb_runtime_suspend(struct device *dev) |
| 1638 | { | 1638 | { |
| 1639 | struct platform_device *pdev = to_platform_device(dev); | 1639 | struct s3c_fb *sfb = dev_get_drvdata(dev); |
| 1640 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | ||
| 1641 | 1640 | ||
| 1642 | if (!sfb->variant.has_clksel) | 1641 | if (!sfb->variant.has_clksel) |
| 1643 | clk_disable_unprepare(sfb->lcd_clk); | 1642 | clk_disable_unprepare(sfb->lcd_clk); |
| @@ -1649,8 +1648,7 @@ static int s3c_fb_runtime_suspend(struct device *dev) | |||
| 1649 | 1648 | ||
| 1650 | static int s3c_fb_runtime_resume(struct device *dev) | 1649 | static int s3c_fb_runtime_resume(struct device *dev) |
| 1651 | { | 1650 | { |
| 1652 | struct platform_device *pdev = to_platform_device(dev); | 1651 | struct s3c_fb *sfb = dev_get_drvdata(dev); |
| 1653 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | ||
| 1654 | struct s3c_fb_platdata *pd = sfb->pdata; | 1652 | struct s3c_fb_platdata *pd = sfb->pdata; |
| 1655 | 1653 | ||
| 1656 | clk_prepare_enable(sfb->bus_clk); | 1654 | clk_prepare_enable(sfb->bus_clk); |
| @@ -1910,7 +1908,7 @@ static struct s3c_fb_driverdata s3c_fb_data_exynos4 = { | |||
| 1910 | static struct s3c_fb_driverdata s3c_fb_data_exynos5 = { | 1908 | static struct s3c_fb_driverdata s3c_fb_data_exynos5 = { |
| 1911 | .variant = { | 1909 | .variant = { |
| 1912 | .nr_windows = 5, | 1910 | .nr_windows = 5, |
| 1913 | .vidtcon = VIDTCON0, | 1911 | .vidtcon = FIMD_V8_VIDTCON0, |
| 1914 | .wincon = WINCON(0), | 1912 | .wincon = WINCON(0), |
| 1915 | .winmap = WINxMAP(0), | 1913 | .winmap = WINxMAP(0), |
| 1916 | .keycon = WKEYCON, | 1914 | .keycon = WKEYCON, |
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index 7ae6c07f2ef8..e7554486a2b7 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h | |||
| @@ -24,12 +24,15 @@ | |||
| 24 | 24 | ||
| 25 | #define VIDCON0 (0x00) | 25 | #define VIDCON0 (0x00) |
| 26 | #define VIDCON0_INTERLACE (1 << 29) | 26 | #define VIDCON0_INTERLACE (1 << 29) |
| 27 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | 27 | #define VIDCON0_VIDOUT_MASK (0x7 << 26) |
| 28 | #define VIDCON0_VIDOUT_SHIFT (26) | 28 | #define VIDCON0_VIDOUT_SHIFT (26) |
| 29 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | 29 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) |
| 30 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | 30 | #define VIDCON0_VIDOUT_TV (0x1 << 26) |
| 31 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | 31 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) |
| 32 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | 32 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) |
| 33 | #define VIDCON0_VIDOUT_WB_RGB (0x4 << 26) | ||
| 34 | #define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26) | ||
| 35 | #define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26) | ||
| 33 | 36 | ||
| 34 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | 37 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) |
| 35 | #define VIDCON0_L1_DATA_SHIFT (23) | 38 | #define VIDCON0_L1_DATA_SHIFT (23) |
| @@ -77,6 +80,7 @@ | |||
| 77 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | 80 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) |
| 78 | #define VIDCON1_LINECNT_SHIFT (16) | 81 | #define VIDCON1_LINECNT_SHIFT (16) |
| 79 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | 82 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) |
| 83 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
| 80 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | 84 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) |
| 81 | #define VIDCON1_VSTATUS_SHIFT (13) | 85 | #define VIDCON1_VSTATUS_SHIFT (13) |
| 82 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | 86 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) |
| @@ -116,6 +120,7 @@ | |||
| 116 | 120 | ||
| 117 | /* VIDTCON0 */ | 121 | /* VIDTCON0 */ |
| 118 | 122 | ||
| 123 | #define VIDTCON0 (0x10) | ||
| 119 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | 124 | #define VIDTCON0_VBPDE_MASK (0xff << 24) |
| 120 | #define VIDTCON0_VBPDE_SHIFT (24) | 125 | #define VIDTCON0_VBPDE_SHIFT (24) |
| 121 | #define VIDTCON0_VBPDE_LIMIT (0xff) | 126 | #define VIDTCON0_VBPDE_LIMIT (0xff) |
| @@ -138,6 +143,7 @@ | |||
| 138 | 143 | ||
| 139 | /* VIDTCON1 */ | 144 | /* VIDTCON1 */ |
| 140 | 145 | ||
| 146 | #define VIDTCON1 (0x14) | ||
| 141 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | 147 | #define VIDTCON1_VFPDE_MASK (0xff << 24) |
| 142 | #define VIDTCON1_VFPDE_SHIFT (24) | 148 | #define VIDTCON1_VFPDE_SHIFT (24) |
| 143 | #define VIDTCON1_VFPDE_LIMIT (0xff) | 149 | #define VIDTCON1_VFPDE_LIMIT (0xff) |
| @@ -159,6 +165,7 @@ | |||
| 159 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | 165 | #define VIDTCON1_HSPW(_x) ((_x) << 0) |
| 160 | 166 | ||
| 161 | #define VIDTCON2 (0x18) | 167 | #define VIDTCON2 (0x18) |
| 168 | #define VIDTCON2 (0x18) | ||
| 162 | #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) | 169 | #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) |
| 163 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | 170 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) |
| 164 | #define VIDTCON2_LINEVAL_SHIFT (11) | 171 | #define VIDTCON2_LINEVAL_SHIFT (11) |
| @@ -173,18 +180,27 @@ | |||
| 173 | 180 | ||
| 174 | /* WINCONx */ | 181 | /* WINCONx */ |
| 175 | 182 | ||
| 176 | 183 | #define WINCON(_win) (0x20 + ((_win) * 4)) | |
| 184 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
| 185 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
| 186 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
| 187 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
| 188 | #define WINCONx_ENLOCAL (1 << 22) | ||
| 189 | #define WINCONx_BUFSTATUS (1 << 21) | ||
| 190 | #define WINCONx_BUFSEL (1 << 20) | ||
| 191 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
| 177 | #define WINCONx_BITSWP (1 << 18) | 192 | #define WINCONx_BITSWP (1 << 18) |
| 178 | #define WINCONx_BYTSWP (1 << 17) | 193 | #define WINCONx_BYTSWP (1 << 17) |
| 179 | #define WINCONx_HAWSWP (1 << 16) | 194 | #define WINCONx_HAWSWP (1 << 16) |
| 180 | #define WINCONx_WSWP (1 << 15) | 195 | #define WINCONx_WSWP (1 << 15) |
| 196 | #define WINCONx_YCbCr (1 << 13) | ||
| 181 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) | 197 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) |
| 182 | #define WINCONx_BURSTLEN_SHIFT (9) | 198 | #define WINCONx_BURSTLEN_SHIFT (9) |
| 183 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | 199 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) |
| 184 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | 200 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) |
| 185 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | 201 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) |
| 186 | |||
| 187 | #define WINCONx_ENWIN (1 << 0) | 202 | #define WINCONx_ENWIN (1 << 0) |
| 203 | |||
| 188 | #define WINCON0_BPPMODE_MASK (0xf << 2) | 204 | #define WINCON0_BPPMODE_MASK (0xf << 2) |
| 189 | #define WINCON0_BPPMODE_SHIFT (2) | 205 | #define WINCON0_BPPMODE_SHIFT (2) |
| 190 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | 206 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) |
| @@ -196,9 +212,8 @@ | |||
| 196 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | 212 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) |
| 197 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | 213 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) |
| 198 | 214 | ||
| 215 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
| 199 | #define WINCON1_BLD_PIX (1 << 6) | 216 | #define WINCON1_BLD_PIX (1 << 6) |
| 200 | |||
| 201 | #define WINCON1_ALPHA_SEL (1 << 1) | ||
| 202 | #define WINCON1_BPPMODE_MASK (0xf << 2) | 217 | #define WINCON1_BPPMODE_MASK (0xf << 2) |
| 203 | #define WINCON1_BPPMODE_SHIFT (2) | 218 | #define WINCON1_BPPMODE_SHIFT (2) |
| 204 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | 219 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) |
| @@ -216,6 +231,7 @@ | |||
| 216 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | 231 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) |
| 217 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | 232 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) |
| 218 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | 233 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) |
| 234 | #define WINCON1_ALPHA_SEL (1 << 1) | ||
| 219 | 235 | ||
| 220 | /* S5PV210 */ | 236 | /* S5PV210 */ |
| 221 | #define SHADOWCON (0x34) | 237 | #define SHADOWCON (0x34) |
| @@ -225,6 +241,9 @@ | |||
| 225 | /* Local input channels (windows 0-2) */ | 241 | /* Local input channels (windows 0-2) */ |
| 226 | #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) | 242 | #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) |
| 227 | 243 | ||
| 244 | /* VIDOSDx */ | ||
| 245 | |||
| 246 | #define VIDOSD_BASE (0x40) | ||
| 228 | #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) | 247 | #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) |
| 229 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) | 248 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) |
| 230 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | 249 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) |
| @@ -293,6 +312,7 @@ | |||
| 293 | 312 | ||
| 294 | /* Interrupt controls and status */ | 313 | /* Interrupt controls and status */ |
| 295 | 314 | ||
| 315 | #define VIDINTCON0 (0x130) | ||
| 296 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) | 316 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) |
| 297 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | 317 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) |
| 298 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | 318 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) |
| @@ -321,6 +341,9 @@ | |||
| 321 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | 341 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) |
| 322 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | 342 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) |
| 323 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | 343 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) |
| 344 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
| 345 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
| 346 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
| 324 | 347 | ||
| 325 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | 348 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) |
| 326 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | 349 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) |
| @@ -357,16 +380,39 @@ | |||
| 357 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | 380 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) |
| 358 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | 381 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) |
| 359 | 382 | ||
| 383 | /* Dithering control */ | ||
| 384 | #define DITHMODE (0x170) | ||
| 385 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
| 386 | #define DITHMODE_R_POS_SHIFT (5) | ||
| 387 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
| 388 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
| 389 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
| 390 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
| 391 | #define DITHMODE_G_POS_SHIFT (3) | ||
| 392 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
| 393 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
| 394 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
| 395 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
| 396 | #define DITHMODE_B_POS_SHIFT (1) | ||
| 397 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
| 398 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
| 399 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
| 400 | #define DITHMODE_DITH_EN (1 << 0) | ||
| 360 | 401 | ||
| 361 | /* Window blanking (MAP) */ | 402 | /* Window blanking (MAP) */ |
| 362 | 403 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | |
| 363 | #define WINxMAP_MAP (1 << 24) | 404 | #define WINxMAP_MAP (1 << 24) |
| 364 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | 405 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) |
| 365 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | 406 | #define WINxMAP_MAP_COLOUR_SHIFT (0) |
| 366 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | 407 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) |
| 367 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | 408 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) |
| 368 | 409 | ||
| 410 | /* Winodw palette control */ | ||
| 411 | #define WPALCON (0x1A0) | ||
| 369 | #define WPALCON_PAL_UPDATE (1 << 9) | 412 | #define WPALCON_PAL_UPDATE (1 << 9) |
| 413 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
| 414 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
| 415 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
| 370 | #define WPALCON_W1PAL_MASK (0x7 << 3) | 416 | #define WPALCON_W1PAL_MASK (0x7 << 3) |
| 371 | #define WPALCON_W1PAL_SHIFT (3) | 417 | #define WPALCON_W1PAL_SHIFT (3) |
| 372 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | 418 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) |
| @@ -376,7 +422,6 @@ | |||
| 376 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | 422 | #define WPALCON_W1PAL_18BPP (0x4 << 3) |
| 377 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | 423 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) |
| 378 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | 424 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) |
| 379 | |||
| 380 | #define WPALCON_W0PAL_MASK (0x7 << 0) | 425 | #define WPALCON_W0PAL_MASK (0x7 << 0) |
| 381 | #define WPALCON_W0PAL_SHIFT (0) | 426 | #define WPALCON_W0PAL_SHIFT (0) |
| 382 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | 427 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) |
| @@ -394,115 +439,6 @@ | |||
| 394 | #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) | 439 | #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) |
| 395 | 440 | ||
| 396 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | 441 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ |
| 397 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
| 398 | |||
| 399 | /* Video timing controls */ | ||
| 400 | #define VIDTCON0 (0x10) | ||
| 401 | #define VIDTCON1 (0x14) | ||
| 402 | #define VIDTCON2 (0x18) | ||
| 403 | |||
| 404 | /* Window position controls */ | ||
| 405 | |||
| 406 | #define WINCON(_win) (0x20 + ((_win) * 4)) | ||
| 407 | |||
| 408 | /* OSD1 and OSD4 do not have register D */ | ||
| 409 | |||
| 410 | #define VIDOSD_BASE (0x40) | ||
| 411 | |||
| 412 | #define VIDINTCON0 (0x130) | ||
| 413 | |||
| 414 | /* WINCONx */ | ||
| 415 | |||
| 416 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
| 417 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
| 418 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
| 419 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
| 420 | |||
| 421 | #define WINCONx_ENLOCAL (1 << 22) | ||
| 422 | #define WINCONx_BUFSTATUS (1 << 21) | ||
| 423 | #define WINCONx_BUFSEL (1 << 20) | ||
| 424 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
| 425 | #define WINCONx_YCbCr (1 << 13) | ||
| 426 | |||
| 427 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
| 428 | |||
| 429 | #define WINCON2_LOCALSEL_CAMIF (1 << 23) | ||
| 430 | #define WINCON2_BLD_PIX (1 << 6) | ||
| 431 | |||
| 432 | #define WINCON2_ALPHA_SEL (1 << 1) | ||
| 433 | #define WINCON2_BPPMODE_MASK (0xf << 2) | ||
| 434 | #define WINCON2_BPPMODE_SHIFT (2) | ||
| 435 | #define WINCON2_BPPMODE_1BPP (0x0 << 2) | ||
| 436 | #define WINCON2_BPPMODE_2BPP (0x1 << 2) | ||
| 437 | #define WINCON2_BPPMODE_4BPP (0x2 << 2) | ||
| 438 | #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) | ||
| 439 | #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 440 | #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 441 | #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 442 | #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 443 | #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 444 | #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 445 | #define WINCON2_BPPMODE_24BPP_888 (0xb << 2) | ||
| 446 | #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 447 | #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 448 | #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 449 | |||
| 450 | #define WINCON3_BLD_PIX (1 << 6) | ||
| 451 | |||
| 452 | #define WINCON3_ALPHA_SEL (1 << 1) | ||
| 453 | #define WINCON3_BPPMODE_MASK (0xf << 2) | ||
| 454 | #define WINCON3_BPPMODE_SHIFT (2) | ||
| 455 | #define WINCON3_BPPMODE_1BPP (0x0 << 2) | ||
| 456 | #define WINCON3_BPPMODE_2BPP (0x1 << 2) | ||
| 457 | #define WINCON3_BPPMODE_4BPP (0x2 << 2) | ||
| 458 | #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 459 | #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 460 | #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 461 | #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 462 | #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 463 | #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 464 | #define WINCON3_BPPMODE_24BPP_888 (0xb << 2) | ||
| 465 | #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 466 | #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 467 | #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 468 | |||
| 469 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
| 470 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
| 471 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
| 472 | |||
| 473 | #define DITHMODE (0x170) | ||
| 474 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | ||
| 475 | |||
| 476 | |||
| 477 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
| 478 | #define DITHMODE_R_POS_SHIFT (5) | ||
| 479 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
| 480 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
| 481 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
| 482 | |||
| 483 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
| 484 | #define DITHMODE_G_POS_SHIFT (3) | ||
| 485 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
| 486 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
| 487 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
| 488 | |||
| 489 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
| 490 | #define DITHMODE_B_POS_SHIFT (1) | ||
| 491 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
| 492 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
| 493 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
| 494 | |||
| 495 | #define DITHMODE_DITH_EN (1 << 0) | ||
| 496 | |||
| 497 | #define WPALCON (0x1A0) | ||
| 498 | |||
| 499 | /* Palette control */ | ||
| 500 | /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), | ||
| 501 | * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ | ||
| 502 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
| 503 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
| 504 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
| 505 | |||
| 506 | 442 | ||
| 507 | /* Notes on per-window bpp settings | 443 | /* Notes on per-window bpp settings |
| 508 | * | 444 | * |
