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authorCarolyn Wyborny <carolyn.wyborny@intel.com>2012-04-06 19:25:19 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-05-12 16:17:13 -0400
commitf96a8a0b78548c0ec06b0b4b438db6ee895d67e9 (patch)
treeb1e6cc64dd55fc46cfb8877aa94db6a7940c1327
parentda02cde1c1ffb798df6159a2252653a9becea51a (diff)
igb: Add Support for new i210/i211 devices.
This patch adds new initialization functions and device support for i210 and i211 devices. Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/igb/Makefile3
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_82575.c182
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_82575.h3
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_defines.h33
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_hw.h14
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_i210.c603
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_i210.h76
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_mac.c1
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_nvm.c1
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_phy.c147
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_phy.h15
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_regs.h14
-rw-r--r--drivers/net/ethernet/intel/igb/igb.h9
-rw-r--r--drivers/net/ethernet/intel/igb/igb_ethtool.c103
-rw-r--r--drivers/net/ethernet/intel/igb/igb_main.c107
-rw-r--r--drivers/net/ethernet/intel/igb/igb_ptp.c4
16 files changed, 1205 insertions, 110 deletions
diff --git a/drivers/net/ethernet/intel/igb/Makefile b/drivers/net/ethernet/intel/igb/Makefile
index 4bd16e266414..97c197fd4a8e 100644
--- a/drivers/net/ethernet/intel/igb/Makefile
+++ b/drivers/net/ethernet/intel/igb/Makefile
@@ -33,6 +33,7 @@
33obj-$(CONFIG_IGB) += igb.o 33obj-$(CONFIG_IGB) += igb.o
34 34
35igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \ 35igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \
36 e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o 36 e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o \
37 e1000_i210.o
37 38
38igb-$(CONFIG_IGB_PTP) += igb_ptp.o 39igb-$(CONFIG_IGB_PTP) += igb_ptp.o
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
index b945992af9ef..e65083958421 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -36,6 +36,7 @@
36 36
37#include "e1000_mac.h" 37#include "e1000_mac.h"
38#include "e1000_82575.h" 38#include "e1000_82575.h"
39#include "e1000_i210.h"
39 40
40static s32 igb_get_invariants_82575(struct e1000_hw *); 41static s32 igb_get_invariants_82575(struct e1000_hw *);
41static s32 igb_acquire_phy_82575(struct e1000_hw *); 42static s32 igb_acquire_phy_82575(struct e1000_hw *);
@@ -98,6 +99,8 @@ static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
98 break; 99 break;
99 case e1000_82580: 100 case e1000_82580:
100 case e1000_i350: 101 case e1000_i350:
102 case e1000_i210:
103 case e1000_i211:
101 reg = rd32(E1000_MDICNFG); 104 reg = rd32(E1000_MDICNFG);
102 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 105 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
103 break; 106 break;
@@ -152,6 +155,17 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
152 case E1000_DEV_ID_I350_SGMII: 155 case E1000_DEV_ID_I350_SGMII:
153 mac->type = e1000_i350; 156 mac->type = e1000_i350;
154 break; 157 break;
158 case E1000_DEV_ID_I210_COPPER:
159 case E1000_DEV_ID_I210_COPPER_OEM1:
160 case E1000_DEV_ID_I210_COPPER_IT:
161 case E1000_DEV_ID_I210_FIBER:
162 case E1000_DEV_ID_I210_SERDES:
163 case E1000_DEV_ID_I210_SGMII:
164 mac->type = e1000_i210;
165 break;
166 case E1000_DEV_ID_I211_COPPER:
167 mac->type = e1000_i211;
168 break;
155 default: 169 default:
156 return -E1000_ERR_MAC_INIT; 170 return -E1000_ERR_MAC_INIT;
157 break; 171 break;
@@ -184,26 +198,44 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
184 /* Set mta register count */ 198 /* Set mta register count */
185 mac->mta_reg_count = 128; 199 mac->mta_reg_count = 128;
186 /* Set rar entry count */ 200 /* Set rar entry count */
187 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 201 switch (mac->type) {
188 if (mac->type == e1000_82576) 202 case e1000_82576:
189 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 203 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
190 if (mac->type == e1000_82580) 204 break;
205 case e1000_82580:
191 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 206 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
192 if (mac->type == e1000_i350) 207 break;
208 case e1000_i350:
209 case e1000_i210:
210 case e1000_i211:
193 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 211 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
212 break;
213 default:
214 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
215 break;
216 }
194 /* reset */ 217 /* reset */
195 if (mac->type >= e1000_82580) 218 if (mac->type >= e1000_82580)
196 mac->ops.reset_hw = igb_reset_hw_82580; 219 mac->ops.reset_hw = igb_reset_hw_82580;
197 else 220 else
198 mac->ops.reset_hw = igb_reset_hw_82575; 221 mac->ops.reset_hw = igb_reset_hw_82575;
222
223 if (mac->type >= e1000_i210) {
224 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
225 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
226 } else {
227 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
228 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
229 }
230
199 /* Set if part includes ASF firmware */ 231 /* Set if part includes ASF firmware */
200 mac->asf_firmware_present = true; 232 mac->asf_firmware_present = true;
201 /* Set if manageability features are enabled. */ 233 /* Set if manageability features are enabled. */
202 mac->arc_subsystem_valid = 234 mac->arc_subsystem_valid =
203 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 235 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
204 ? true : false; 236 ? true : false;
205 /* enable EEE on i350 parts */ 237 /* enable EEE on i350 parts and later parts */
206 if (mac->type == e1000_i350) 238 if (mac->type >= e1000_i350)
207 dev_spec->eee_disable = false; 239 dev_spec->eee_disable = false;
208 else 240 else
209 dev_spec->eee_disable = true; 241 dev_spec->eee_disable = true;
@@ -215,26 +247,6 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
215 247
216 /* NVM initialization */ 248 /* NVM initialization */
217 eecd = rd32(E1000_EECD); 249 eecd = rd32(E1000_EECD);
218
219 nvm->opcode_bits = 8;
220 nvm->delay_usec = 1;
221 switch (nvm->override) {
222 case e1000_nvm_override_spi_large:
223 nvm->page_size = 32;
224 nvm->address_bits = 16;
225 break;
226 case e1000_nvm_override_spi_small:
227 nvm->page_size = 8;
228 nvm->address_bits = 8;
229 break;
230 default:
231 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
232 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
233 break;
234 }
235
236 nvm->type = e1000_nvm_eeprom_spi;
237
238 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 250 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
239 E1000_EECD_SIZE_EX_SHIFT); 251 E1000_EECD_SIZE_EX_SHIFT);
240 252
@@ -244,6 +256,33 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
244 */ 256 */
245 size += NVM_WORD_SIZE_BASE_SHIFT; 257 size += NVM_WORD_SIZE_BASE_SHIFT;
246 258
259 nvm->word_size = 1 << size;
260 if (hw->mac.type < e1000_i210) {
261 nvm->opcode_bits = 8;
262 nvm->delay_usec = 1;
263 switch (nvm->override) {
264 case e1000_nvm_override_spi_large:
265 nvm->page_size = 32;
266 nvm->address_bits = 16;
267 break;
268 case e1000_nvm_override_spi_small:
269 nvm->page_size = 8;
270 nvm->address_bits = 8;
271 break;
272 default:
273 nvm->page_size = eecd
274 & E1000_EECD_ADDR_BITS ? 32 : 8;
275 nvm->address_bits = eecd
276 & E1000_EECD_ADDR_BITS ? 16 : 8;
277 break;
278 }
279 if (nvm->word_size == (1 << 15))
280 nvm->page_size = 128;
281
282 nvm->type = e1000_nvm_eeprom_spi;
283 } else
284 nvm->type = e1000_nvm_flash_hw;
285
247 /* 286 /*
248 * Check for invalid size 287 * Check for invalid size
249 */ 288 */
@@ -251,32 +290,60 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
251 pr_notice("The NVM size is not valid, defaulting to 32K\n"); 290 pr_notice("The NVM size is not valid, defaulting to 32K\n");
252 size = 15; 291 size = 15;
253 } 292 }
254 nvm->word_size = 1 << size;
255 if (nvm->word_size == (1 << 15))
256 nvm->page_size = 128;
257 293
258 /* NVM Function Pointers */ 294 /* NVM Function Pointers */
259 nvm->ops.acquire = igb_acquire_nvm_82575;
260 if (nvm->word_size < (1 << 15))
261 nvm->ops.read = igb_read_nvm_eerd;
262 else
263 nvm->ops.read = igb_read_nvm_spi;
264
265 nvm->ops.release = igb_release_nvm_82575;
266 switch (hw->mac.type) { 295 switch (hw->mac.type) {
267 case e1000_82580: 296 case e1000_82580:
268 nvm->ops.validate = igb_validate_nvm_checksum_82580; 297 nvm->ops.validate = igb_validate_nvm_checksum_82580;
269 nvm->ops.update = igb_update_nvm_checksum_82580; 298 nvm->ops.update = igb_update_nvm_checksum_82580;
299 nvm->ops.acquire = igb_acquire_nvm_82575;
300 nvm->ops.release = igb_release_nvm_82575;
301 if (nvm->word_size < (1 << 15))
302 nvm->ops.read = igb_read_nvm_eerd;
303 else
304 nvm->ops.read = igb_read_nvm_spi;
305 nvm->ops.write = igb_write_nvm_spi;
270 break; 306 break;
271 case e1000_i350: 307 case e1000_i350:
272 nvm->ops.validate = igb_validate_nvm_checksum_i350; 308 nvm->ops.validate = igb_validate_nvm_checksum_i350;
273 nvm->ops.update = igb_update_nvm_checksum_i350; 309 nvm->ops.update = igb_update_nvm_checksum_i350;
310 nvm->ops.acquire = igb_acquire_nvm_82575;
311 nvm->ops.release = igb_release_nvm_82575;
312 if (nvm->word_size < (1 << 15))
313 nvm->ops.read = igb_read_nvm_eerd;
314 else
315 nvm->ops.read = igb_read_nvm_spi;
316 nvm->ops.write = igb_write_nvm_spi;
317 break;
318 case e1000_i210:
319 nvm->ops.validate = igb_validate_nvm_checksum_i210;
320 nvm->ops.update = igb_update_nvm_checksum_i210;
321 nvm->ops.acquire = igb_acquire_nvm_i210;
322 nvm->ops.release = igb_release_nvm_i210;
323 nvm->ops.read = igb_read_nvm_srrd_i210;
324 nvm->ops.valid_led_default = igb_valid_led_default_i210;
325 break;
326 case e1000_i211:
327 nvm->ops.acquire = igb_acquire_nvm_i210;
328 nvm->ops.release = igb_release_nvm_i210;
329 nvm->ops.read = igb_read_nvm_i211;
330 nvm->ops.valid_led_default = igb_valid_led_default_i210;
331 nvm->ops.validate = NULL;
332 nvm->ops.update = NULL;
333 nvm->ops.write = NULL;
274 break; 334 break;
275 default: 335 default:
276 nvm->ops.validate = igb_validate_nvm_checksum; 336 nvm->ops.validate = igb_validate_nvm_checksum;
277 nvm->ops.update = igb_update_nvm_checksum; 337 nvm->ops.update = igb_update_nvm_checksum;
338 nvm->ops.acquire = igb_acquire_nvm_82575;
339 nvm->ops.release = igb_release_nvm_82575;
340 if (nvm->word_size < (1 << 15))
341 nvm->ops.read = igb_read_nvm_eerd;
342 else
343 nvm->ops.read = igb_read_nvm_spi;
344 nvm->ops.write = igb_write_nvm_spi;
345 break;
278 } 346 }
279 nvm->ops.write = igb_write_nvm_spi;
280 347
281 /* if part supports SR-IOV then initialize mailbox parameters */ 348 /* if part supports SR-IOV then initialize mailbox parameters */
282 switch (mac->type) { 349 switch (mac->type) {
@@ -314,9 +381,13 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
314 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 381 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
315 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 382 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
316 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 383 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
317 } else if (hw->mac.type >= e1000_82580) { 384 } else if ((hw->mac.type == e1000_82580)
385 || (hw->mac.type == e1000_i350)) {
318 phy->ops.read_reg = igb_read_phy_reg_82580; 386 phy->ops.read_reg = igb_read_phy_reg_82580;
319 phy->ops.write_reg = igb_write_phy_reg_82580; 387 phy->ops.write_reg = igb_write_phy_reg_82580;
388 } else if (hw->phy.type >= e1000_phy_i210) {
389 phy->ops.read_reg = igb_read_phy_reg_gs40g;
390 phy->ops.write_reg = igb_write_phy_reg_gs40g;
320 } else { 391 } else {
321 phy->ops.read_reg = igb_read_phy_reg_igp; 392 phy->ops.read_reg = igb_read_phy_reg_igp;
322 phy->ops.write_reg = igb_write_phy_reg_igp; 393 phy->ops.write_reg = igb_write_phy_reg_igp;
@@ -345,6 +416,14 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
345 else 416 else
346 phy->ops.get_cable_length = igb_get_cable_length_m88; 417 phy->ops.get_cable_length = igb_get_cable_length_m88;
347 418
419 if (phy->id == I210_I_PHY_ID) {
420 phy->ops.get_cable_length =
421 igb_get_cable_length_m88_gen2;
422 phy->ops.set_d0_lplu_state =
423 igb_set_d0_lplu_state_82580;
424 phy->ops.set_d3_lplu_state =
425 igb_set_d3_lplu_state_82580;
426 }
348 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 427 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
349 break; 428 break;
350 case IGP03E1000_E_PHY_ID: 429 case IGP03E1000_E_PHY_ID:
@@ -364,6 +443,15 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
364 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 443 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
365 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 444 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
366 break; 445 break;
446 case I210_I_PHY_ID:
447 phy->type = e1000_phy_i210;
448 phy->ops.get_phy_info = igb_get_phy_info_m88;
449 phy->ops.check_polarity = igb_check_polarity_m88;
450 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
451 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
452 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
453 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
454 break;
367 default: 455 default:
368 return -E1000_ERR_PHY; 456 return -E1000_ERR_PHY;
369 } 457 }
@@ -389,7 +477,7 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
389 else if (hw->bus.func == E1000_FUNC_3) 477 else if (hw->bus.func == E1000_FUNC_3)
390 mask = E1000_SWFW_PHY3_SM; 478 mask = E1000_SWFW_PHY3_SM;
391 479
392 return igb_acquire_swfw_sync_82575(hw, mask); 480 return hw->mac.ops.acquire_swfw_sync(hw, mask);
393} 481}
394 482
395/** 483/**
@@ -410,7 +498,7 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
410 else if (hw->bus.func == E1000_FUNC_3) 498 else if (hw->bus.func == E1000_FUNC_3)
411 mask = E1000_SWFW_PHY3_SM; 499 mask = E1000_SWFW_PHY3_SM;
412 500
413 igb_release_swfw_sync_82575(hw, mask); 501 hw->mac.ops.release_swfw_sync(hw, mask);
414} 502}
415 503
416/** 504/**
@@ -514,6 +602,8 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
514 break; 602 break;
515 case e1000_82580: 603 case e1000_82580:
516 case e1000_i350: 604 case e1000_i350:
605 case e1000_i210:
606 case e1000_i211:
517 mdic = rd32(E1000_MDICNFG); 607 mdic = rd32(E1000_MDICNFG);
518 mdic &= E1000_MDICNFG_PHY_MASK; 608 mdic &= E1000_MDICNFG_PHY_MASK;
519 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 609 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
@@ -780,14 +870,14 @@ static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
780{ 870{
781 s32 ret_val; 871 s32 ret_val;
782 872
783 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 873 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
784 if (ret_val) 874 if (ret_val)
785 goto out; 875 goto out;
786 876
787 ret_val = igb_acquire_nvm(hw); 877 ret_val = igb_acquire_nvm(hw);
788 878
789 if (ret_val) 879 if (ret_val)
790 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 880 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
791 881
792out: 882out:
793 return ret_val; 883 return ret_val;
@@ -803,7 +893,7 @@ out:
803static void igb_release_nvm_82575(struct e1000_hw *hw) 893static void igb_release_nvm_82575(struct e1000_hw *hw)
804{ 894{
805 igb_release_nvm(hw); 895 igb_release_nvm(hw);
806 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 896 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
807} 897}
808 898
809/** 899/**
@@ -1174,7 +1264,6 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
1174 * is no link. 1264 * is no link.
1175 */ 1265 */
1176 igb_clear_hw_cntrs_82575(hw); 1266 igb_clear_hw_cntrs_82575(hw);
1177
1178 return ret_val; 1267 return ret_val;
1179} 1268}
1180 1269
@@ -1211,6 +1300,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1211 } 1300 }
1212 } 1301 }
1213 switch (hw->phy.type) { 1302 switch (hw->phy.type) {
1303 case e1000_phy_i210:
1214 case e1000_phy_m88: 1304 case e1000_phy_m88:
1215 if (hw->phy.id == I347AT4_E_PHY_ID || 1305 if (hw->phy.id == I347AT4_E_PHY_ID ||
1216 hw->phy.id == M88E1112_E_PHY_ID) 1306 hw->phy.id == M88E1112_E_PHY_ID)
@@ -1851,7 +1941,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1851 1941
1852 /* Determine whether or not a global dev reset is requested */ 1942 /* Determine whether or not a global dev reset is requested */
1853 if (global_device_reset && 1943 if (global_device_reset &&
1854 igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1944 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
1855 global_device_reset = false; 1945 global_device_reset = false;
1856 1946
1857 if (global_device_reset && 1947 if (global_device_reset &&
@@ -1897,7 +1987,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1897 1987
1898 /* Release semaphore */ 1988 /* Release semaphore */
1899 if (global_device_reset) 1989 if (global_device_reset)
1900 igb_release_swfw_sync_82575(hw, swmbsw_mask); 1990 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
1901 1991
1902 return ret_val; 1992 return ret_val;
1903} 1993}
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.h b/drivers/net/ethernet/intel/igb/e1000_82575.h
index b927d79ab536..e85c453f5428 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.h
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.h
@@ -55,10 +55,11 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
55#define E1000_SRRCTL_DROP_EN 0x80000000 55#define E1000_SRRCTL_DROP_EN 0x80000000
56#define E1000_SRRCTL_TIMESTAMP 0x40000000 56#define E1000_SRRCTL_TIMESTAMP 0x40000000
57 57
58
58#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 59#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
59#define E1000_MRQC_ENABLE_VMDQ 0x00000003 60#define E1000_MRQC_ENABLE_VMDQ 0x00000003
60#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
61#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 61#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
62#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
62#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 63#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
63#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 64#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
64 65
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
index 89eb1f85b9fa..6409f85632f5 100644
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -458,6 +458,7 @@
458#define E1000_ERR_INVALID_ARGUMENT 16 458#define E1000_ERR_INVALID_ARGUMENT 16
459#define E1000_ERR_NO_SPACE 17 459#define E1000_ERR_NO_SPACE 17
460#define E1000_ERR_NVM_PBA_SECTION 18 460#define E1000_ERR_NVM_PBA_SECTION 18
461#define E1000_ERR_INVM_VALUE_NOT_FOUND 19
461 462
462/* Loop limit on how long we wait for auto-negotiation to complete */ 463/* Loop limit on how long we wait for auto-negotiation to complete */
463#define COPPER_LINK_UP_LIMIT 10 464#define COPPER_LINK_UP_LIMIT 10
@@ -595,6 +596,25 @@
595#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 596#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
596#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 597#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
597#define E1000_EECD_SIZE_EX_SHIFT 11 598#define E1000_EECD_SIZE_EX_SHIFT 11
599#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
600#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
601#define E1000_FLUDONE_ATTEMPTS 20000
602#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
603#define E1000_I210_FIFO_SEL_RX 0x00
604#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
605#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
606#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
607#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
608#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
609#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
610#define E1000_FLUDONE_ATTEMPTS 20000
611#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
612#define E1000_I210_FIFO_SEL_RX 0x00
613#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
614#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
615#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
616#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
617
598 618
599/* Offset to data in NVM read/write registers */ 619/* Offset to data in NVM read/write registers */
600#define E1000_NVM_RW_REG_DATA 16 620#define E1000_NVM_RW_REG_DATA 16
@@ -613,6 +633,16 @@
613#define NVM_CHECKSUM_REG 0x003F 633#define NVM_CHECKSUM_REG 0x003F
614#define NVM_COMPATIBILITY_REG_3 0x0003 634#define NVM_COMPATIBILITY_REG_3 0x0003
615#define NVM_COMPATIBILITY_BIT_MASK 0x8000 635#define NVM_COMPATIBILITY_BIT_MASK 0x8000
636#define NVM_MAC_ADDR 0x0000
637#define NVM_SUB_DEV_ID 0x000B
638#define NVM_SUB_VEN_ID 0x000C
639#define NVM_DEV_ID 0x000D
640#define NVM_VEN_ID 0x000E
641#define NVM_INIT_CTRL_2 0x000F
642#define NVM_INIT_CTRL_4 0x0013
643#define NVM_LED_1_CFG 0x001C
644#define NVM_LED_0_2_CFG 0x001F
645
616 646
617#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 647#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
618#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 648#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
@@ -639,6 +669,7 @@
639 669
640#define NVM_PBA_OFFSET_0 8 670#define NVM_PBA_OFFSET_0 8
641#define NVM_PBA_OFFSET_1 9 671#define NVM_PBA_OFFSET_1 9
672#define NVM_RESERVED_WORD 0xFFFF
642#define NVM_PBA_PTR_GUARD 0xFAFA 673#define NVM_PBA_PTR_GUARD 0xFAFA
643#define NVM_WORD_SIZE_BASE_SHIFT 6 674#define NVM_WORD_SIZE_BASE_SHIFT 6
644 675
@@ -696,6 +727,7 @@
696#define I82580_I_PHY_ID 0x015403A0 727#define I82580_I_PHY_ID 0x015403A0
697#define I350_I_PHY_ID 0x015403B0 728#define I350_I_PHY_ID 0x015403B0
698#define M88_VENDOR 0x0141 729#define M88_VENDOR 0x0141
730#define I210_I_PHY_ID 0x01410C00
699 731
700/* M88E1000 Specific Registers */ 732/* M88E1000 Specific Registers */
701#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 733#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
@@ -815,6 +847,7 @@
815#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 847#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
816#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 848#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
817#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 849#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
850#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */
818#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 851#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
819 852
820/* SerDes Control */ 853/* SerDes Control */
diff --git a/drivers/net/ethernet/intel/igb/e1000_hw.h b/drivers/net/ethernet/intel/igb/e1000_hw.h
index f67cbd3fa307..c2a51dcda550 100644
--- a/drivers/net/ethernet/intel/igb/e1000_hw.h
+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
@@ -63,6 +63,13 @@ struct e1000_hw;
63#define E1000_DEV_ID_I350_FIBER 0x1522 63#define E1000_DEV_ID_I350_FIBER 0x1522
64#define E1000_DEV_ID_I350_SERDES 0x1523 64#define E1000_DEV_ID_I350_SERDES 0x1523
65#define E1000_DEV_ID_I350_SGMII 0x1524 65#define E1000_DEV_ID_I350_SGMII 0x1524
66#define E1000_DEV_ID_I210_COPPER 0x1533
67#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
68#define E1000_DEV_ID_I210_COPPER_IT 0x1535
69#define E1000_DEV_ID_I210_FIBER 0x1536
70#define E1000_DEV_ID_I210_SERDES 0x1537
71#define E1000_DEV_ID_I210_SGMII 0x1538
72#define E1000_DEV_ID_I211_COPPER 0x1539
66 73
67#define E1000_REVISION_2 2 74#define E1000_REVISION_2 2
68#define E1000_REVISION_4 4 75#define E1000_REVISION_4 4
@@ -83,6 +90,8 @@ enum e1000_mac_type {
83 e1000_82576, 90 e1000_82576,
84 e1000_82580, 91 e1000_82580,
85 e1000_i350, 92 e1000_i350,
93 e1000_i210,
94 e1000_i211,
86 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 95 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
87}; 96};
88 97
@@ -117,6 +126,7 @@ enum e1000_phy_type {
117 e1000_phy_igp_3, 126 e1000_phy_igp_3,
118 e1000_phy_ife, 127 e1000_phy_ife,
119 e1000_phy_82580, 128 e1000_phy_82580,
129 e1000_phy_i210,
120}; 130};
121 131
122enum e1000_bus_type { 132enum e1000_bus_type {
@@ -313,6 +323,9 @@ struct e1000_mac_operations {
313 void (*rar_set)(struct e1000_hw *, u8 *, u32); 323 void (*rar_set)(struct e1000_hw *, u8 *, u32);
314 s32 (*read_mac_addr)(struct e1000_hw *); 324 s32 (*read_mac_addr)(struct e1000_hw *);
315 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 325 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
326 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
327 void (*release_swfw_sync)(struct e1000_hw *, u16);
328
316}; 329};
317 330
318struct e1000_phy_operations { 331struct e1000_phy_operations {
@@ -338,6 +351,7 @@ struct e1000_nvm_operations {
338 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 351 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
339 s32 (*update)(struct e1000_hw *); 352 s32 (*update)(struct e1000_hw *);
340 s32 (*validate)(struct e1000_hw *); 353 s32 (*validate)(struct e1000_hw *);
354 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
341}; 355};
342 356
343struct e1000_info { 357struct e1000_info {
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c
new file mode 100644
index 000000000000..77a5f939bc74
--- /dev/null
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.c
@@ -0,0 +1,603 @@
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26******************************************************************************/
27
28/* e1000_i210
29 * e1000_i211
30 */
31
32#include <linux/types.h>
33#include <linux/if_ether.h>
34
35#include "e1000_hw.h"
36#include "e1000_i210.h"
37
38static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw);
39static void igb_put_hw_semaphore_i210(struct e1000_hw *hw);
40static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
41 u16 *data);
42static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw);
43
44/**
45 * igb_acquire_nvm_i210 - Request for access to EEPROM
46 * @hw: pointer to the HW structure
47 *
48 * Acquire the necessary semaphores for exclusive access to the EEPROM.
49 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
50 * Return successful if access grant bit set, else clear the request for
51 * EEPROM access and return -E1000_ERR_NVM (-1).
52 **/
53s32 igb_acquire_nvm_i210(struct e1000_hw *hw)
54{
55 return igb_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
56}
57
58/**
59 * igb_release_nvm_i210 - Release exclusive access to EEPROM
60 * @hw: pointer to the HW structure
61 *
62 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
63 * then release the semaphores acquired.
64 **/
65void igb_release_nvm_i210(struct e1000_hw *hw)
66{
67 igb_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
68}
69
70/**
71 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
72 * @hw: pointer to the HW structure
73 * @mask: specifies which semaphore to acquire
74 *
75 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
76 * will also specify which port we're acquiring the lock for.
77 **/
78s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
79{
80 u32 swfw_sync;
81 u32 swmask = mask;
82 u32 fwmask = mask << 16;
83 s32 ret_val = E1000_SUCCESS;
84 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
85
86 while (i < timeout) {
87 if (igb_get_hw_semaphore_i210(hw)) {
88 ret_val = -E1000_ERR_SWFW_SYNC;
89 goto out;
90 }
91
92 swfw_sync = rd32(E1000_SW_FW_SYNC);
93 if (!(swfw_sync & fwmask))
94 break;
95
96 /*
97 * Firmware currently using resource (fwmask)
98 */
99 igb_put_hw_semaphore_i210(hw);
100 mdelay(5);
101 i++;
102 }
103
104 if (i == timeout) {
105 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
106 ret_val = -E1000_ERR_SWFW_SYNC;
107 goto out;
108 }
109
110 swfw_sync |= swmask;
111 wr32(E1000_SW_FW_SYNC, swfw_sync);
112
113 igb_put_hw_semaphore_i210(hw);
114out:
115 return ret_val;
116}
117
118/**
119 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
120 * @hw: pointer to the HW structure
121 * @mask: specifies which semaphore to acquire
122 *
123 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
124 * will also specify which port we're releasing the lock for.
125 **/
126void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
127{
128 u32 swfw_sync;
129
130 while (igb_get_hw_semaphore_i210(hw) != E1000_SUCCESS)
131 ; /* Empty */
132
133 swfw_sync = rd32(E1000_SW_FW_SYNC);
134 swfw_sync &= ~mask;
135 wr32(E1000_SW_FW_SYNC, swfw_sync);
136
137 igb_put_hw_semaphore_i210(hw);
138}
139
140/**
141 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
142 * @hw: pointer to the HW structure
143 *
144 * Acquire the HW semaphore to access the PHY or NVM
145 **/
146static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
147{
148 u32 swsm;
149 s32 ret_val = E1000_SUCCESS;
150 s32 timeout = hw->nvm.word_size + 1;
151 s32 i = 0;
152
153 /* Get the FW semaphore. */
154 for (i = 0; i < timeout; i++) {
155 swsm = rd32(E1000_SWSM);
156 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
157
158 /* Semaphore acquired if bit latched */
159 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
160 break;
161
162 udelay(50);
163 }
164
165 if (i == timeout) {
166 /* Release semaphores */
167 igb_put_hw_semaphore(hw);
168 hw_dbg("Driver can't access the NVM\n");
169 ret_val = -E1000_ERR_NVM;
170 goto out;
171 }
172
173out:
174 return ret_val;
175}
176
177/**
178 * igb_put_hw_semaphore_i210 - Release hardware semaphore
179 * @hw: pointer to the HW structure
180 *
181 * Release hardware semaphore used to access the PHY or NVM
182 **/
183static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
184{
185 u32 swsm;
186
187 swsm = rd32(E1000_SWSM);
188
189 swsm &= ~E1000_SWSM_SWESMBI;
190
191 wr32(E1000_SWSM, swsm);
192}
193
194/**
195 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
196 * @hw: pointer to the HW structure
197 * @offset: offset of word in the Shadow Ram to read
198 * @words: number of words to read
199 * @data: word read from the Shadow Ram
200 *
201 * Reads a 16 bit word from the Shadow Ram using the EERD register.
202 * Uses necessary synchronization semaphores.
203 **/
204s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
205 u16 *data)
206{
207 s32 status = E1000_SUCCESS;
208 u16 i, count;
209
210 /* We cannot hold synchronization semaphores for too long,
211 * because of forceful takeover procedure. However it is more efficient
212 * to read in bursts than synchronizing access for each word. */
213 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
214 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
215 E1000_EERD_EEWR_MAX_COUNT : (words - i);
216 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
217 status = igb_read_nvm_eerd(hw, offset, count,
218 data + i);
219 hw->nvm.ops.release(hw);
220 } else {
221 status = E1000_ERR_SWFW_SYNC;
222 }
223
224 if (status != E1000_SUCCESS)
225 break;
226 }
227
228 return status;
229}
230
231/**
232 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
233 * @hw: pointer to the HW structure
234 * @offset: offset within the Shadow RAM to be written to
235 * @words: number of words to write
236 * @data: 16 bit word(s) to be written to the Shadow RAM
237 *
238 * Writes data to Shadow RAM at offset using EEWR register.
239 *
240 * If e1000_update_nvm_checksum is not called after this function , the
241 * data will not be committed to FLASH and also Shadow RAM will most likely
242 * contain an invalid checksum.
243 *
244 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
245 * partially written.
246 **/
247s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
248 u16 *data)
249{
250 s32 status = E1000_SUCCESS;
251 u16 i, count;
252
253 /* We cannot hold synchronization semaphores for too long,
254 * because of forceful takeover procedure. However it is more efficient
255 * to write in bursts than synchronizing access for each word. */
256 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
257 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
258 E1000_EERD_EEWR_MAX_COUNT : (words - i);
259 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
260 status = igb_write_nvm_srwr(hw, offset, count,
261 data + i);
262 hw->nvm.ops.release(hw);
263 } else {
264 status = E1000_ERR_SWFW_SYNC;
265 }
266
267 if (status != E1000_SUCCESS)
268 break;
269 }
270
271 return status;
272}
273
274/**
275 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
276 * @hw: pointer to the HW structure
277 * @offset: offset within the Shadow Ram to be written to
278 * @words: number of words to write
279 * @data: 16 bit word(s) to be written to the Shadow Ram
280 *
281 * Writes data to Shadow Ram at offset using EEWR register.
282 *
283 * If igb_update_nvm_checksum is not called after this function , the
284 * Shadow Ram will most likely contain an invalid checksum.
285 **/
286static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
287 u16 *data)
288{
289 struct e1000_nvm_info *nvm = &hw->nvm;
290 u32 i, k, eewr = 0;
291 u32 attempts = 100000;
292 s32 ret_val = E1000_SUCCESS;
293
294 /*
295 * A check for invalid values: offset too large, too many words,
296 * too many words for the offset, and not enough words.
297 */
298 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
299 (words == 0)) {
300 hw_dbg("nvm parameter(s) out of bounds\n");
301 ret_val = -E1000_ERR_NVM;
302 goto out;
303 }
304
305 for (i = 0; i < words; i++) {
306 eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
307 (data[i] << E1000_NVM_RW_REG_DATA) |
308 E1000_NVM_RW_REG_START;
309
310 wr32(E1000_SRWR, eewr);
311
312 for (k = 0; k < attempts; k++) {
313 if (E1000_NVM_RW_REG_DONE &
314 rd32(E1000_SRWR)) {
315 ret_val = E1000_SUCCESS;
316 break;
317 }
318 udelay(5);
319 }
320
321 if (ret_val != E1000_SUCCESS) {
322 hw_dbg("Shadow RAM write EEWR timed out\n");
323 break;
324 }
325 }
326
327out:
328 return ret_val;
329}
330
331/**
332 * igb_read_nvm_i211 - Read NVM wrapper function for I211
333 * @hw: pointer to the HW structure
334 * @address: the word address (aka eeprom offset) to read
335 * @data: pointer to the data read
336 *
337 * Wrapper function to return data formerly found in the NVM.
338 **/
339s32 igb_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
340 u16 *data)
341{
342 s32 ret_val = E1000_SUCCESS;
343
344 /* Only the MAC addr is required to be present in the iNVM */
345 switch (offset) {
346 case NVM_MAC_ADDR:
347 ret_val = igb_read_invm_i211(hw, offset, &data[0]);
348 ret_val |= igb_read_invm_i211(hw, offset+1, &data[1]);
349 ret_val |= igb_read_invm_i211(hw, offset+2, &data[2]);
350 if (ret_val != E1000_SUCCESS)
351 hw_dbg("MAC Addr not found in iNVM\n");
352 break;
353 case NVM_ID_LED_SETTINGS:
354 case NVM_INIT_CTRL_2:
355 case NVM_INIT_CTRL_4:
356 case NVM_LED_1_CFG:
357 case NVM_LED_0_2_CFG:
358 igb_read_invm_i211(hw, offset, data);
359 break;
360 case NVM_COMPAT:
361 *data = ID_LED_DEFAULT_I210;
362 break;
363 case NVM_SUB_DEV_ID:
364 *data = hw->subsystem_device_id;
365 break;
366 case NVM_SUB_VEN_ID:
367 *data = hw->subsystem_vendor_id;
368 break;
369 case NVM_DEV_ID:
370 *data = hw->device_id;
371 break;
372 case NVM_VEN_ID:
373 *data = hw->vendor_id;
374 break;
375 default:
376 hw_dbg("NVM word 0x%02x is not mapped.\n", offset);
377 *data = NVM_RESERVED_WORD;
378 break;
379 }
380 return ret_val;
381}
382
383/**
384 * igb_read_invm_i211 - Reads OTP
385 * @hw: pointer to the HW structure
386 * @address: the word address (aka eeprom offset) to read
387 * @data: pointer to the data read
388 *
389 * Reads 16-bit words from the OTP. Return error when the word is not
390 * stored in OTP.
391 **/
392s32 igb_read_invm_i211(struct e1000_hw *hw, u16 address, u16 *data)
393{
394 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
395 u32 invm_dword;
396 u16 i;
397 u8 record_type, word_address;
398
399 for (i = 0; i < E1000_INVM_SIZE; i++) {
400 invm_dword = rd32(E1000_INVM_DATA_REG(i));
401 /* Get record type */
402 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
403 if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
404 break;
405 if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
406 i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
407 if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
408 i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
409 if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
410 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
411 if (word_address == (u8)address) {
412 *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
413 hw_dbg("Read INVM Word 0x%02x = %x",
414 address, *data);
415 status = E1000_SUCCESS;
416 break;
417 }
418 }
419 }
420 if (status != E1000_SUCCESS)
421 hw_dbg("Requested word 0x%02x not found in OTP\n", address);
422 return status;
423}
424
425/**
426 * igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
427 * @hw: pointer to the HW structure
428 *
429 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
430 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
431 **/
432s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)
433{
434 s32 status = E1000_SUCCESS;
435 s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
436
437 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
438
439 /*
440 * Replace the read function with semaphore grabbing with
441 * the one that skips this for a while.
442 * We have semaphore taken already here.
443 */
444 read_op_ptr = hw->nvm.ops.read;
445 hw->nvm.ops.read = igb_read_nvm_eerd;
446
447 status = igb_validate_nvm_checksum(hw);
448
449 /* Revert original read operation. */
450 hw->nvm.ops.read = read_op_ptr;
451
452 hw->nvm.ops.release(hw);
453 } else {
454 status = E1000_ERR_SWFW_SYNC;
455 }
456
457 return status;
458}
459
460
461/**
462 * igb_update_nvm_checksum_i210 - Update EEPROM checksum
463 * @hw: pointer to the HW structure
464 *
465 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
466 * up to the checksum. Then calculates the EEPROM checksum and writes the
467 * value to the EEPROM. Next commit EEPROM data onto the Flash.
468 **/
469s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
470{
471 s32 ret_val = E1000_SUCCESS;
472 u16 checksum = 0;
473 u16 i, nvm_data;
474
475 /*
476 * Read the first word from the EEPROM. If this times out or fails, do
477 * not continue or we could be in for a very long wait while every
478 * EEPROM read fails
479 */
480 ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data);
481 if (ret_val != E1000_SUCCESS) {
482 hw_dbg("EEPROM read failed\n");
483 goto out;
484 }
485
486 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
487 /*
488 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
489 * because we do not want to take the synchronization
490 * semaphores twice here.
491 */
492
493 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
494 ret_val = igb_read_nvm_eerd(hw, i, 1, &nvm_data);
495 if (ret_val) {
496 hw->nvm.ops.release(hw);
497 hw_dbg("NVM Read Error while updating checksum.\n");
498 goto out;
499 }
500 checksum += nvm_data;
501 }
502 checksum = (u16) NVM_SUM - checksum;
503 ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
504 &checksum);
505 if (ret_val != E1000_SUCCESS) {
506 hw->nvm.ops.release(hw);
507 hw_dbg("NVM Write Error while updating checksum.\n");
508 goto out;
509 }
510
511 hw->nvm.ops.release(hw);
512
513 ret_val = igb_update_flash_i210(hw);
514 } else {
515 ret_val = -E1000_ERR_SWFW_SYNC;
516 }
517out:
518 return ret_val;
519}
520
521/**
522 * igb_update_flash_i210 - Commit EEPROM to the flash
523 * @hw: pointer to the HW structure
524 *
525 **/
526s32 igb_update_flash_i210(struct e1000_hw *hw)
527{
528 s32 ret_val = E1000_SUCCESS;
529 u32 flup;
530
531 ret_val = igb_pool_flash_update_done_i210(hw);
532 if (ret_val == -E1000_ERR_NVM) {
533 hw_dbg("Flash update time out\n");
534 goto out;
535 }
536
537 flup = rd32(E1000_EECD) | E1000_EECD_FLUPD_I210;
538 wr32(E1000_EECD, flup);
539
540 ret_val = igb_pool_flash_update_done_i210(hw);
541 if (ret_val == E1000_SUCCESS)
542 hw_dbg("Flash update complete\n");
543 else
544 hw_dbg("Flash update time out\n");
545
546out:
547 return ret_val;
548}
549
550/**
551 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
552 * @hw: pointer to the HW structure
553 *
554 **/
555s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
556{
557 s32 ret_val = -E1000_ERR_NVM;
558 u32 i, reg;
559
560 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
561 reg = rd32(E1000_EECD);
562 if (reg & E1000_EECD_FLUDONE_I210) {
563 ret_val = E1000_SUCCESS;
564 break;
565 }
566 udelay(5);
567 }
568
569 return ret_val;
570}
571
572/**
573 * igb_valid_led_default_i210 - Verify a valid default LED config
574 * @hw: pointer to the HW structure
575 * @data: pointer to the NVM (EEPROM)
576 *
577 * Read the EEPROM for the current default LED configuration. If the
578 * LED configuration is not valid, set to a valid LED configuration.
579 **/
580s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
581{
582 s32 ret_val;
583
584 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
585 if (ret_val) {
586 hw_dbg("NVM Read Error\n");
587 goto out;
588 }
589
590 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
591 switch (hw->phy.media_type) {
592 case e1000_media_type_internal_serdes:
593 *data = ID_LED_DEFAULT_I210_SERDES;
594 break;
595 case e1000_media_type_copper:
596 default:
597 *data = ID_LED_DEFAULT_I210;
598 break;
599 }
600 }
601out:
602 return ret_val;
603}
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.h b/drivers/net/ethernet/intel/igb/e1000_i210.h
new file mode 100644
index 000000000000..5dc2bd3f50bc
--- /dev/null
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.h
@@ -0,0 +1,76 @@
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_I210_H_
29#define _E1000_I210_H_
30
31extern s32 igb_update_flash_i210(struct e1000_hw *hw);
32extern s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw);
33extern s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw);
34extern s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
35 u16 words, u16 *data);
36extern s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
37 u16 words, u16 *data);
38extern s32 igb_read_invm_i211(struct e1000_hw *hw, u16 address, u16 *data);
39extern s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
40extern void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
41extern s32 igb_acquire_nvm_i210(struct e1000_hw *hw);
42extern void igb_release_nvm_i210(struct e1000_hw *hw);
43extern s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
44extern s32 igb_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
45 u16 *data);
46
47#define E1000_STM_OPCODE 0xDB00
48#define E1000_EEPROM_FLASH_SIZE_WORD 0x11
49
50#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
51 (u8)((invm_dword) & 0x7)
52#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
53 (u8)(((invm_dword) & 0x0000FE00) >> 9)
54#define INVM_DWORD_TO_WORD_DATA(invm_dword) \
55 (u16)(((invm_dword) & 0xFFFF0000) >> 16)
56
57enum E1000_INVM_STRUCTURE_TYPE {
58 E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00,
59 E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01,
60 E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02,
61 E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03,
62 E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04,
63 E1000_INVM_INVALIDATED_STRUCTURE = 0x0F,
64};
65
66#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8
67#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1
68
69#define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \
70 (ID_LED_OFF1_OFF2 << 4) | \
71 (ID_LED_DEF1_DEF2))
72#define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \
73 (ID_LED_DEF1_DEF2 << 4) | \
74 (ID_LED_DEF1_DEF2))
75
76#endif
diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c
index f57338afd71f..819c145ac762 100644
--- a/drivers/net/ethernet/intel/igb/e1000_mac.c
+++ b/drivers/net/ethernet/intel/igb/e1000_mac.c
@@ -658,6 +658,7 @@ s32 igb_setup_link(struct e1000_hw *hw)
658 ret_val = igb_set_fc_watermarks(hw); 658 ret_val = igb_set_fc_watermarks(hw);
659 659
660out: 660out:
661
661 return ret_val; 662 return ret_val;
662} 663}
663 664
diff --git a/drivers/net/ethernet/intel/igb/e1000_nvm.c b/drivers/net/ethernet/intel/igb/e1000_nvm.c
index fa2c6ba62139..aa5fcdf3f357 100644
--- a/drivers/net/ethernet/intel/igb/e1000_nvm.c
+++ b/drivers/net/ethernet/intel/igb/e1000_nvm.c
@@ -710,4 +710,3 @@ s32 igb_update_nvm_checksum(struct e1000_hw *hw)
710out: 710out:
711 return ret_val; 711 return ret_val;
712} 712}
713
diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c
index 789de5b83aad..7be98b6f1052 100644
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
@@ -35,6 +35,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 35static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
36 u16 *phy_ctrl); 36 u16 *phy_ctrl);
37static s32 igb_wait_autoneg(struct e1000_hw *hw); 37static s32 igb_wait_autoneg(struct e1000_hw *hw);
38static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
38 39
39/* Cable length tables */ 40/* Cable length tables */
40static const u16 e1000_m88_cable_length_table[] = 41static const u16 e1000_m88_cable_length_table[] =
@@ -570,6 +571,11 @@ s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
570 hw_dbg("Error committing the PHY changes\n"); 571 hw_dbg("Error committing the PHY changes\n");
571 goto out; 572 goto out;
572 } 573 }
574 if (phy->type == e1000_phy_i210) {
575 ret_val = igb_set_master_slave_mode(hw);
576 if (ret_val)
577 return ret_val;
578 }
573 579
574out: 580out:
575 return ret_val; 581 return ret_val;
@@ -1213,12 +1219,22 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1213 goto out; 1219 goto out;
1214 1220
1215 if (!link) { 1221 if (!link) {
1216 if (hw->phy.type != e1000_phy_m88 || 1222 bool reset_dsp = true;
1217 hw->phy.id == I347AT4_E_PHY_ID || 1223
1218 hw->phy.id == M88E1112_E_PHY_ID) { 1224 switch (hw->phy.id) {
1225 case I347AT4_E_PHY_ID:
1226 case M88E1112_E_PHY_ID:
1227 case I210_I_PHY_ID:
1228 reset_dsp = false;
1229 break;
1230 default:
1231 if (hw->phy.type != e1000_phy_m88)
1232 reset_dsp = false;
1233 break;
1234 }
1235 if (!reset_dsp)
1219 hw_dbg("Link taking longer than expected.\n"); 1236 hw_dbg("Link taking longer than expected.\n");
1220 } else { 1237 else {
1221
1222 /* 1238 /*
1223 * We didn't get link. 1239 * We didn't get link.
1224 * Reset the DSP and cross our fingers. 1240 * Reset the DSP and cross our fingers.
@@ -1243,7 +1259,8 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1243 1259
1244 if (hw->phy.type != e1000_phy_m88 || 1260 if (hw->phy.type != e1000_phy_m88 ||
1245 hw->phy.id == I347AT4_E_PHY_ID || 1261 hw->phy.id == I347AT4_E_PHY_ID ||
1246 hw->phy.id == M88E1112_E_PHY_ID) 1262 hw->phy.id == M88E1112_E_PHY_ID ||
1263 hw->phy.id == I210_I_PHY_ID)
1247 goto out; 1264 goto out;
1248 1265
1249 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1266 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
@@ -1441,6 +1458,7 @@ s32 igb_check_downshift(struct e1000_hw *hw)
1441 u16 phy_data, offset, mask; 1458 u16 phy_data, offset, mask;
1442 1459
1443 switch (phy->type) { 1460 switch (phy->type) {
1461 case e1000_phy_i210:
1444 case e1000_phy_m88: 1462 case e1000_phy_m88:
1445 case e1000_phy_gg82563: 1463 case e1000_phy_gg82563:
1446 offset = M88E1000_PHY_SPEC_STATUS; 1464 offset = M88E1000_PHY_SPEC_STATUS;
@@ -1476,7 +1494,7 @@ out:
1476 * 1494 *
1477 * Polarity is determined based on the PHY specific status register. 1495 * Polarity is determined based on the PHY specific status register.
1478 **/ 1496 **/
1479static s32 igb_check_polarity_m88(struct e1000_hw *hw) 1497s32 igb_check_polarity_m88(struct e1000_hw *hw)
1480{ 1498{
1481 struct e1000_phy_info *phy = &hw->phy; 1499 struct e1000_phy_info *phy = &hw->phy;
1482 s32 ret_val; 1500 s32 ret_val;
@@ -1665,6 +1683,7 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1665 u16 phy_data, phy_data2, index, default_page, is_cm; 1683 u16 phy_data, phy_data2, index, default_page, is_cm;
1666 1684
1667 switch (hw->phy.id) { 1685 switch (hw->phy.id) {
1686 case I210_I_PHY_ID:
1668 case I347AT4_E_PHY_ID: 1687 case I347AT4_E_PHY_ID:
1669 /* Remember the original page select and set it to 7 */ 1688 /* Remember the original page select and set it to 7 */
1670 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1689 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
@@ -2129,10 +2148,16 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2129void igb_power_up_phy_copper(struct e1000_hw *hw) 2148void igb_power_up_phy_copper(struct e1000_hw *hw)
2130{ 2149{
2131 u16 mii_reg = 0; 2150 u16 mii_reg = 0;
2151 u16 power_reg = 0;
2132 2152
2133 /* The PHY will retain its settings across a power down/up cycle */ 2153 /* The PHY will retain its settings across a power down/up cycle */
2134 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2154 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2135 mii_reg &= ~MII_CR_POWER_DOWN; 2155 mii_reg &= ~MII_CR_POWER_DOWN;
2156 if (hw->phy.type == e1000_phy_i210) {
2157 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2158 power_reg &= ~GS40G_CS_POWER_DOWN;
2159 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2160 }
2136 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2161 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2137} 2162}
2138 2163
@@ -2146,10 +2171,18 @@ void igb_power_up_phy_copper(struct e1000_hw *hw)
2146void igb_power_down_phy_copper(struct e1000_hw *hw) 2171void igb_power_down_phy_copper(struct e1000_hw *hw)
2147{ 2172{
2148 u16 mii_reg = 0; 2173 u16 mii_reg = 0;
2174 u16 power_reg = 0;
2149 2175
2150 /* The PHY will retain its settings across a power down/up cycle */ 2176 /* The PHY will retain its settings across a power down/up cycle */
2151 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2177 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2152 mii_reg |= MII_CR_POWER_DOWN; 2178 mii_reg |= MII_CR_POWER_DOWN;
2179
2180 /* i210 Phy requires an additional bit for power up/down */
2181 if (hw->phy.type == e1000_phy_i210) {
2182 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2183 power_reg |= GS40G_CS_POWER_DOWN;
2184 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2185 }
2153 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2186 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2154 msleep(1); 2187 msleep(1);
2155} 2188}
@@ -2345,3 +2378,103 @@ s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2345out: 2378out:
2346 return ret_val; 2379 return ret_val;
2347} 2380}
2381
2382/**
2383 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2384 * @hw: pointer to the HW structure
2385 * @offset: lower half is register offset to write to
2386 * upper half is page to use.
2387 * @data: data to write at register offset
2388 *
2389 * Acquires semaphore, if necessary, then writes the data to PHY register
2390 * at the offset. Release any acquired semaphores before exiting.
2391 **/
2392s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2393{
2394 s32 ret_val;
2395 u16 page = offset >> GS40G_PAGE_SHIFT;
2396
2397 offset = offset & GS40G_OFFSET_MASK;
2398 ret_val = hw->phy.ops.acquire(hw);
2399 if (ret_val)
2400 return ret_val;
2401
2402 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2403 if (ret_val)
2404 goto release;
2405 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2406
2407release:
2408 hw->phy.ops.release(hw);
2409 return ret_val;
2410}
2411
2412/**
2413 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2414 * @hw: pointer to the HW structure
2415 * @offset: lower half is register offset to read to
2416 * upper half is page to use.
2417 * @data: data to read at register offset
2418 *
2419 * Acquires semaphore, if necessary, then reads the data in the PHY register
2420 * at the offset. Release any acquired semaphores before exiting.
2421 **/
2422s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2423{
2424 s32 ret_val;
2425 u16 page = offset >> GS40G_PAGE_SHIFT;
2426
2427 offset = offset & GS40G_OFFSET_MASK;
2428 ret_val = hw->phy.ops.acquire(hw);
2429 if (ret_val)
2430 return ret_val;
2431
2432 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2433 if (ret_val)
2434 goto release;
2435 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2436
2437release:
2438 hw->phy.ops.release(hw);
2439 return ret_val;
2440}
2441
2442/**
2443 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2444 * @hw: pointer to the HW structure
2445 *
2446 * Sets up Master/slave mode
2447 **/
2448static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2449{
2450 s32 ret_val;
2451 u16 phy_data;
2452
2453 /* Resolve Master/Slave mode */
2454 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2455 if (ret_val)
2456 return ret_val;
2457
2458 /* load defaults for future use */
2459 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2460 ((phy_data & CR_1000T_MS_VALUE) ?
2461 e1000_ms_force_master :
2462 e1000_ms_force_slave) : e1000_ms_auto;
2463
2464 switch (hw->phy.ms_type) {
2465 case e1000_ms_force_master:
2466 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2467 break;
2468 case e1000_ms_force_slave:
2469 phy_data |= CR_1000T_MS_ENABLE;
2470 phy_data &= ~(CR_1000T_MS_VALUE);
2471 break;
2472 case e1000_ms_auto:
2473 phy_data &= ~CR_1000T_MS_ENABLE;
2474 /* fall-through */
2475 default:
2476 break;
2477 }
2478
2479 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2480}
diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h
index 84172ea2bc1b..34e40619f16b 100644
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
@@ -73,6 +73,9 @@ s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
73s32 igb_get_phy_info_82580(struct e1000_hw *hw); 73s32 igb_get_phy_info_82580(struct e1000_hw *hw);
74s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); 74s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
75s32 igb_get_cable_length_82580(struct e1000_hw *hw); 75s32 igb_get_cable_length_82580(struct e1000_hw *hw);
76s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
77s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
78s32 igb_check_polarity_m88(struct e1000_hw *hw);
76 79
77/* IGP01E1000 Specific Registers */ 80/* IGP01E1000 Specific Registers */
78#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 81#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
@@ -140,4 +143,16 @@ s32 igb_get_cable_length_82580(struct e1000_hw *hw);
140 143
141#define E1000_CABLE_LENGTH_UNDEFINED 0xFF 144#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
142 145
146/* GS40G - I210 PHY defines */
147#define GS40G_PAGE_SELECT 0x16
148#define GS40G_PAGE_SHIFT 16
149#define GS40G_OFFSET_MASK 0xFFFF
150#define GS40G_PAGE_2 0x20000
151#define GS40G_MAC_REG2 0x15
152#define GS40G_MAC_LB 0x4140
153#define GS40G_MAC_SPEED_1G 0X0006
154#define GS40G_COPPER_SPEC 0x0010
155#define GS40G_CS_POWER_DOWN 0x0002
156#define GS40G_LINE_LB 0x4000
157
143#endif 158#endif
diff --git a/drivers/net/ethernet/intel/igb/e1000_regs.h b/drivers/net/ethernet/intel/igb/e1000_regs.h
index ccdf36d503fd..35d1e4f2c92c 100644
--- a/drivers/net/ethernet/intel/igb/e1000_regs.h
+++ b/drivers/net/ethernet/intel/igb/e1000_regs.h
@@ -352,4 +352,18 @@
352#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 352#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */
353#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 353#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */
354 354
355#define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */
356#define E1000_I210_FLMNGCTL 0x12038
357#define E1000_I210_FLMNGDATA 0x1203C
358#define E1000_I210_FLMNGCNT 0x12040
359
360#define E1000_I210_FLSWCTL 0x12048
361#define E1000_I210_FLSWDATA 0x1204C
362#define E1000_I210_FLSWCNT 0x12050
363
364#define E1000_I210_FLA 0x1201C
365
366#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
367#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */
368
355#endif 369#endif
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h
index 3758ad246742..ae6d3f393a54 100644
--- a/drivers/net/ethernet/intel/igb/igb.h
+++ b/drivers/net/ethernet/intel/igb/igb.h
@@ -65,10 +65,13 @@ struct igb_adapter;
65#define MAX_Q_VECTORS 8 65#define MAX_Q_VECTORS 8
66 66
67/* Transmit and receive queues */ 67/* Transmit and receive queues */
68#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ 68#define IGB_MAX_RX_QUEUES ((adapter->vfs_allocated_count ? 2 : \
69 (hw->mac.type > e1000_82575 ? 8 : 4)) 69 (hw->mac.type > e1000_82575 ? 8 : 4)))
70#define IGB_MAX_RX_QUEUES_I210 4
71#define IGB_MAX_RX_QUEUES_I211 2
70#define IGB_MAX_TX_QUEUES 16 72#define IGB_MAX_TX_QUEUES 16
71 73#define IGB_MAX_TX_QUEUES_I210 4
74#define IGB_MAX_TX_QUEUES_I211 2
72#define IGB_MAX_VF_MC_ENTRIES 30 75#define IGB_MAX_VF_MC_ENTRIES 30
73#define IGB_MAX_VF_FUNCTIONS 8 76#define IGB_MAX_VF_FUNCTIONS 8
74#define IGB_MAX_VFTA_ENTRIES 128 77#define IGB_MAX_VFTA_ENTRIES 128
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index faadf2340866..812d4f963bd1 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -552,10 +552,13 @@ static void igb_get_regs(struct net_device *netdev,
552 regs_buff[548] = rd32(E1000_TDFT); 552 regs_buff[548] = rd32(E1000_TDFT);
553 regs_buff[549] = rd32(E1000_TDFHS); 553 regs_buff[549] = rd32(E1000_TDFHS);
554 regs_buff[550] = rd32(E1000_TDFPC); 554 regs_buff[550] = rd32(E1000_TDFPC);
555 regs_buff[551] = adapter->stats.o2bgptc; 555
556 regs_buff[552] = adapter->stats.b2ospc; 556 if (hw->mac.type > e1000_82580) {
557 regs_buff[553] = adapter->stats.o2bspc; 557 regs_buff[551] = adapter->stats.o2bgptc;
558 regs_buff[554] = adapter->stats.b2ogprc; 558 regs_buff[552] = adapter->stats.b2ospc;
559 regs_buff[553] = adapter->stats.o2bspc;
560 regs_buff[554] = adapter->stats.b2ogprc;
561 }
559 562
560 if (hw->mac.type != e1000_82576) 563 if (hw->mac.type != e1000_82576)
561 return; 564 return;
@@ -660,6 +663,9 @@ static int igb_set_eeprom(struct net_device *netdev,
660 if (eeprom->len == 0) 663 if (eeprom->len == 0)
661 return -EOPNOTSUPP; 664 return -EOPNOTSUPP;
662 665
666 if (hw->mac.type == e1000_i211)
667 return -EOPNOTSUPP;
668
663 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 669 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
664 return -EFAULT; 670 return -EFAULT;
665 671
@@ -887,6 +893,36 @@ struct igb_reg_test {
887#define TABLE64_TEST_LO 5 893#define TABLE64_TEST_LO 5
888#define TABLE64_TEST_HI 6 894#define TABLE64_TEST_HI 6
889 895
896/* i210 reg test */
897static struct igb_reg_test reg_test_i210[] = {
898 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
899 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
900 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
901 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
902 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
903 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
904 /* RDH is read-only for i210, only test RDT. */
905 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
906 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
907 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
908 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
909 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
910 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
911 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
912 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
913 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
914 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
915 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
916 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
917 { E1000_RA, 0, 16, TABLE64_TEST_LO,
918 0xFFFFFFFF, 0xFFFFFFFF },
919 { E1000_RA, 0, 16, TABLE64_TEST_HI,
920 0x900FFFFF, 0xFFFFFFFF },
921 { E1000_MTA, 0, 128, TABLE32_TEST,
922 0xFFFFFFFF, 0xFFFFFFFF },
923 { 0, 0, 0, 0, 0 }
924};
925
890/* i350 reg test */ 926/* i350 reg test */
891static struct igb_reg_test reg_test_i350[] = { 927static struct igb_reg_test reg_test_i350[] = {
892 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 928 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
@@ -1109,6 +1145,11 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1109 test = reg_test_i350; 1145 test = reg_test_i350;
1110 toggle = 0x7FEFF3FF; 1146 toggle = 0x7FEFF3FF;
1111 break; 1147 break;
1148 case e1000_i210:
1149 case e1000_i211:
1150 test = reg_test_i210;
1151 toggle = 0x7FEFF3FF;
1152 break;
1112 case e1000_82580: 1153 case e1000_82580:
1113 test = reg_test_82580; 1154 test = reg_test_82580;
1114 toggle = 0x7FEFF3FF; 1155 toggle = 0x7FEFF3FF;
@@ -1190,23 +1231,13 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1190 1231
1191static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1232static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1192{ 1233{
1193 u16 temp;
1194 u16 checksum = 0;
1195 u16 i;
1196
1197 *data = 0; 1234 *data = 0;
1198 /* Read and add up the contents of the EEPROM */
1199 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1200 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1201 *data = 1;
1202 break;
1203 }
1204 checksum += temp;
1205 }
1206 1235
1207 /* If Checksum is not Correct return error else test passed */ 1236 /* Validate eeprom on all parts but i211 */
1208 if ((checksum != (u16) NVM_SUM) && !(*data)) 1237 if (adapter->hw.mac.type != e1000_i211) {
1209 *data = 2; 1238 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1239 *data = 2;
1240 }
1210 1241
1211 return *data; 1242 return *data;
1212} 1243}
@@ -1272,6 +1303,8 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1272 ics_mask = 0x77DCFED5; 1303 ics_mask = 0x77DCFED5;
1273 break; 1304 break;
1274 case e1000_i350: 1305 case e1000_i350:
1306 case e1000_i210:
1307 case e1000_i211:
1275 ics_mask = 0x77DCFED5; 1308 ics_mask = 0x77DCFED5;
1276 break; 1309 break;
1277 default: 1310 default:
@@ -1438,23 +1471,35 @@ static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1438{ 1471{
1439 struct e1000_hw *hw = &adapter->hw; 1472 struct e1000_hw *hw = &adapter->hw;
1440 u32 ctrl_reg = 0; 1473 u32 ctrl_reg = 0;
1474 u16 phy_reg = 0;
1441 1475
1442 hw->mac.autoneg = false; 1476 hw->mac.autoneg = false;
1443 1477
1444 if (hw->phy.type == e1000_phy_m88) { 1478 switch (hw->phy.type) {
1479 case e1000_phy_m88:
1445 /* Auto-MDI/MDIX Off */ 1480 /* Auto-MDI/MDIX Off */
1446 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1481 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1447 /* reset to update Auto-MDI/MDIX */ 1482 /* reset to update Auto-MDI/MDIX */
1448 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1483 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1449 /* autoneg off */ 1484 /* autoneg off */
1450 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1485 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1451 } else if (hw->phy.type == e1000_phy_82580) { 1486 break;
1487 case e1000_phy_82580:
1452 /* enable MII loopback */ 1488 /* enable MII loopback */
1453 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1489 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1490 break;
1491 case e1000_phy_i210:
1492 /* set loopback speed in PHY */
1493 igb_read_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1494 &phy_reg);
1495 phy_reg |= GS40G_MAC_SPEED_1G;
1496 igb_write_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1497 phy_reg);
1498 ctrl_reg = rd32(E1000_CTRL_EXT);
1499 default:
1500 break;
1454 } 1501 }
1455 1502
1456 ctrl_reg = rd32(E1000_CTRL);
1457
1458 /* force 1000, set loopback */ 1503 /* force 1000, set loopback */
1459 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1504 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1460 1505
@@ -1467,7 +1512,7 @@ static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1467 E1000_CTRL_FD | /* Force Duplex to FULL */ 1512 E1000_CTRL_FD | /* Force Duplex to FULL */
1468 E1000_CTRL_SLU); /* Set link up enable bit */ 1513 E1000_CTRL_SLU); /* Set link up enable bit */
1469 1514
1470 if (hw->phy.type == e1000_phy_m88) 1515 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1471 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1516 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1472 1517
1473 wr32(E1000_CTRL, ctrl_reg); 1518 wr32(E1000_CTRL, ctrl_reg);
@@ -1475,7 +1520,7 @@ static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1475 /* Disable the receiver on the PHY so when a cable is plugged in, the 1520 /* Disable the receiver on the PHY so when a cable is plugged in, the
1476 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1521 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1477 */ 1522 */
1478 if (hw->phy.type == e1000_phy_m88) 1523 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1479 igb_phy_disable_receiver(adapter); 1524 igb_phy_disable_receiver(adapter);
1480 1525
1481 udelay(500); 1526 udelay(500);
@@ -1740,6 +1785,14 @@ static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1740 *data = 0; 1785 *data = 0;
1741 goto out; 1786 goto out;
1742 } 1787 }
1788 if ((adapter->hw.mac.type == e1000_i210)
1789 || (adapter->hw.mac.type == e1000_i210)) {
1790 dev_err(&adapter->pdev->dev,
1791 "Loopback test not supported "
1792 "on this part at this time.\n");
1793 *data = 0;
1794 goto out;
1795 }
1743 *data = igb_setup_desc_rings(adapter); 1796 *data = igb_setup_desc_rings(adapter);
1744 if (*data) 1797 if (*data)
1745 goto out; 1798 goto out;
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 80d52d2dfea3..ba21f9c72a21 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -75,6 +75,11 @@ static const struct e1000_info *igb_info_tbl[] = {
75}; 75};
76 76
77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
@@ -641,6 +646,8 @@ static void igb_cache_ring_register(struct igb_adapter *adapter)
641 case e1000_82575: 646 case e1000_82575:
642 case e1000_82580: 647 case e1000_82580:
643 case e1000_i350: 648 case e1000_i350:
649 case e1000_i210:
650 case e1000_i211:
644 default: 651 default:
645 for (; i < adapter->num_rx_queues; i++) 652 for (; i < adapter->num_rx_queues; i++)
646 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 653 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
@@ -727,8 +734,11 @@ static int igb_alloc_queues(struct igb_adapter *adapter)
727 if (adapter->hw.mac.type >= e1000_82576) 734 if (adapter->hw.mac.type >= e1000_82576)
728 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 735 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
729 736
730 /* On i350, loopback VLAN packets have the tag byte-swapped. */ 737 /*
731 if (adapter->hw.mac.type == e1000_i350) 738 * On i350, i210, and i211, loopback VLAN packets
739 * have the tag byte-swapped.
740 * */
741 if (adapter->hw.mac.type >= e1000_i350)
732 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 742 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
733 743
734 adapter->rx_ring[i] = ring; 744 adapter->rx_ring[i] = ring;
@@ -822,6 +832,8 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
822 break; 832 break;
823 case e1000_82580: 833 case e1000_82580:
824 case e1000_i350: 834 case e1000_i350:
835 case e1000_i210:
836 case e1000_i211:
825 /* 837 /*
826 * On 82580 and newer adapters the scheme is similar to 82576 838 * On 82580 and newer adapters the scheme is similar to 82576
827 * however instead of ordering column-major we have things 839 * however instead of ordering column-major we have things
@@ -888,6 +900,8 @@ static void igb_configure_msix(struct igb_adapter *adapter)
888 case e1000_82576: 900 case e1000_82576:
889 case e1000_82580: 901 case e1000_82580:
890 case e1000_i350: 902 case e1000_i350:
903 case e1000_i210:
904 case e1000_i211:
891 /* Turn on MSI-X capability first, or our settings 905 /* Turn on MSI-X capability first, or our settings
892 * won't stick. And it will take days to debug. */ 906 * won't stick. And it will take days to debug. */
893 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 907 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
@@ -1034,6 +1048,11 @@ static int igb_set_interrupt_capability(struct igb_adapter *adapter)
1034 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1048 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1035 numvecs += adapter->num_tx_queues; 1049 numvecs += adapter->num_tx_queues;
1036 1050
1051 /* i210 and i211 can only have 4 MSIX vectors for rx/tx queues. */
1052 if ((adapter->hw.mac.type == e1000_i210)
1053 || (adapter->hw.mac.type == e1000_i211))
1054 numvecs = 4;
1055
1037 /* store the number of vectors reserved for queues */ 1056 /* store the number of vectors reserved for queues */
1038 adapter->num_q_vectors = numvecs; 1057 adapter->num_q_vectors = numvecs;
1039 1058
@@ -1041,6 +1060,7 @@ static int igb_set_interrupt_capability(struct igb_adapter *adapter)
1041 numvecs++; 1060 numvecs++;
1042 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 1061 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1043 GFP_KERNEL); 1062 GFP_KERNEL);
1063
1044 if (!adapter->msix_entries) 1064 if (!adapter->msix_entries)
1045 goto msi_only; 1065 goto msi_only;
1046 1066
@@ -1631,6 +1651,8 @@ void igb_reset(struct igb_adapter *adapter)
1631 pba &= E1000_RXPBS_SIZE_MASK_82576; 1651 pba &= E1000_RXPBS_SIZE_MASK_82576;
1632 break; 1652 break;
1633 case e1000_82575: 1653 case e1000_82575:
1654 case e1000_i210:
1655 case e1000_i211:
1634 default: 1656 default:
1635 pba = E1000_PBA_34K; 1657 pba = E1000_PBA_34K;
1636 break; 1658 break;
@@ -1826,7 +1848,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1826 */ 1848 */
1827 if (pdev->is_virtfn) { 1849 if (pdev->is_virtfn) {
1828 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1850 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1829 pci_name(pdev), pdev->vendor, pdev->device); 1851 pci_name(pdev), pdev->vendor, pdev->device);
1830 return -EINVAL; 1852 return -EINVAL;
1831 } 1853 }
1832 1854
@@ -1980,11 +2002,16 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1980 * known good starting state */ 2002 * known good starting state */
1981 hw->mac.ops.reset_hw(hw); 2003 hw->mac.ops.reset_hw(hw);
1982 2004
1983 /* make sure the NVM is good */ 2005 /*
1984 if (hw->nvm.ops.validate(hw) < 0) { 2006 * make sure the NVM is good , i211 parts have special NVM that
1985 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2007 * doesn't contain a checksum
1986 err = -EIO; 2008 */
1987 goto err_eeprom; 2009 if (hw->mac.type != e1000_i211) {
2010 if (hw->nvm.ops.validate(hw) < 0) {
2011 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2012 err = -EIO;
2013 goto err_eeprom;
2014 }
1988 } 2015 }
1989 2016
1990 /* copy the MAC address out of the NVM */ 2017 /* copy the MAC address out of the NVM */
@@ -2118,6 +2145,8 @@ static int __devinit igb_probe(struct pci_dev *pdev,
2118 adapter->num_rx_queues, adapter->num_tx_queues); 2145 adapter->num_rx_queues, adapter->num_tx_queues);
2119 switch (hw->mac.type) { 2146 switch (hw->mac.type) {
2120 case e1000_i350: 2147 case e1000_i350:
2148 case e1000_i210:
2149 case e1000_i211:
2121 igb_set_eee_i350(hw); 2150 igb_set_eee_i350(hw);
2122 break; 2151 break;
2123 default: 2152 default:
@@ -2244,9 +2273,14 @@ static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2244{ 2273{
2245#ifdef CONFIG_PCI_IOV 2274#ifdef CONFIG_PCI_IOV
2246 struct pci_dev *pdev = adapter->pdev; 2275 struct pci_dev *pdev = adapter->pdev;
2276 struct e1000_hw *hw = &adapter->hw;
2247 int old_vfs = igb_find_enabled_vfs(adapter); 2277 int old_vfs = igb_find_enabled_vfs(adapter);
2248 int i; 2278 int i;
2249 2279
2280 /* Virtualization features not supported on i210 family. */
2281 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2282 return;
2283
2250 if (old_vfs) { 2284 if (old_vfs) {
2251 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2285 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2252 "max_vfs setting of %d\n", old_vfs, max_vfs); 2286 "max_vfs setting of %d\n", old_vfs, max_vfs);
@@ -2258,6 +2292,7 @@ static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2258 2292
2259 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2293 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2260 sizeof(struct vf_data_storage), GFP_KERNEL); 2294 sizeof(struct vf_data_storage), GFP_KERNEL);
2295
2261 /* if allocation failed then we do not support SR-IOV */ 2296 /* if allocation failed then we do not support SR-IOV */
2262 if (!adapter->vf_data) { 2297 if (!adapter->vf_data) {
2263 adapter->vfs_allocated_count = 0; 2298 adapter->vfs_allocated_count = 0;
@@ -2332,11 +2367,28 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
2332 } else 2367 } else
2333 adapter->vfs_allocated_count = max_vfs; 2368 adapter->vfs_allocated_count = max_vfs;
2334 break; 2369 break;
2370 case e1000_i210:
2371 case e1000_i211:
2372 adapter->vfs_allocated_count = 0;
2373 break;
2335 default: 2374 default:
2336 break; 2375 break;
2337 } 2376 }
2338#endif /* CONFIG_PCI_IOV */ 2377#endif /* CONFIG_PCI_IOV */
2339 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); 2378 switch (hw->mac.type) {
2379 case e1000_i210:
2380 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES_I210,
2381 num_online_cpus());
2382 break;
2383 case e1000_i211:
2384 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES_I211,
2385 num_online_cpus());
2386 break;
2387 default:
2388 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES,
2389 num_online_cpus());
2390 break;
2391 }
2340 /* i350 cannot do RSS and SR-IOV at the same time */ 2392 /* i350 cannot do RSS and SR-IOV at the same time */
2341 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count) 2393 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2342 adapter->rss_queues = 1; 2394 adapter->rss_queues = 1;
@@ -2366,7 +2418,7 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
2366 /* Explicitly disable IRQ since the NIC can be in any state. */ 2418 /* Explicitly disable IRQ since the NIC can be in any state. */
2367 igb_irq_disable(adapter); 2419 igb_irq_disable(adapter);
2368 2420
2369 if (hw->mac.type == e1000_i350) 2421 if (hw->mac.type >= e1000_i350)
2370 adapter->flags &= ~IGB_FLAG_DMAC; 2422 adapter->flags &= ~IGB_FLAG_DMAC;
2371 2423
2372 set_bit(__IGB_DOWN, &adapter->state); 2424 set_bit(__IGB_DOWN, &adapter->state);
@@ -2819,6 +2871,17 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
2819 2871
2820 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2872 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2821 wr32(E1000_RXCSUM, rxcsum); 2873 wr32(E1000_RXCSUM, rxcsum);
2874 /*
2875 * Generate RSS hash based on TCP port numbers and/or
2876 * IPv4/v6 src and dst addresses since UDP cannot be
2877 * hashed reliably due to IP fragmentation
2878 */
2879
2880 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2881 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2882 E1000_MRQC_RSS_FIELD_IPV6 |
2883 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2884 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2822 2885
2823 /* If VMDq is enabled then we set the appropriate mode for that, else 2886 /* If VMDq is enabled then we set the appropriate mode for that, else
2824 * we default to RSS so that an RSS hash is calculated per packet even 2887 * we default to RSS so that an RSS hash is calculated per packet even
@@ -2834,25 +2897,15 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
2834 wr32(E1000_VT_CTL, vtctl); 2897 wr32(E1000_VT_CTL, vtctl);
2835 } 2898 }
2836 if (adapter->rss_queues > 1) 2899 if (adapter->rss_queues > 1)
2837 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2900 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2838 else 2901 else
2839 mrqc = E1000_MRQC_ENABLE_VMDQ; 2902 mrqc |= E1000_MRQC_ENABLE_VMDQ;
2840 } else { 2903 } else {
2841 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2904 if (hw->mac.type != e1000_i211)
2905 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2842 } 2906 }
2843 igb_vmm_control(adapter); 2907 igb_vmm_control(adapter);
2844 2908
2845 /*
2846 * Generate RSS hash based on TCP port numbers and/or
2847 * IPv4/v6 src and dst addresses since UDP cannot be
2848 * hashed reliably due to IP fragmentation
2849 */
2850 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2851 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2852 E1000_MRQC_RSS_FIELD_IPV6 |
2853 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2854 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2855
2856 wr32(E1000_MRQC, mrqc); 2909 wr32(E1000_MRQC, mrqc);
2857} 2910}
2858 2911
@@ -3454,7 +3507,7 @@ static void igb_set_rx_mode(struct net_device *netdev)
3454 * we will have issues with VLAN tag stripping not being done for frames 3507 * we will have issues with VLAN tag stripping not being done for frames
3455 * that are only arriving because we are the default pool 3508 * that are only arriving because we are the default pool
3456 */ 3509 */
3457 if (hw->mac.type < e1000_82576) 3510 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3458 return; 3511 return;
3459 3512
3460 vmolr |= rd32(E1000_VMOLR(vfn)) & 3513 vmolr |= rd32(E1000_VMOLR(vfn)) &
@@ -3551,7 +3604,7 @@ static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3551 bool ret = false; 3604 bool ret = false;
3552 u32 ctrl_ext, thstat; 3605 u32 ctrl_ext, thstat;
3553 3606
3554 /* check for thermal sensor event on i350, copper only */ 3607 /* check for thermal sensor event on i350 copper only */
3555 if (hw->mac.type == e1000_i350) { 3608 if (hw->mac.type == e1000_i350) {
3556 thstat = rd32(E1000_THSTAT); 3609 thstat = rd32(E1000_THSTAT);
3557 ctrl_ext = rd32(E1000_CTRL_EXT); 3610 ctrl_ext = rd32(E1000_CTRL_EXT);
@@ -7027,6 +7080,8 @@ static void igb_vmm_control(struct igb_adapter *adapter)
7027 7080
7028 switch (hw->mac.type) { 7081 switch (hw->mac.type) {
7029 case e1000_82575: 7082 case e1000_82575:
7083 case e1000_i210:
7084 case e1000_i211:
7030 default: 7085 default:
7031 /* replication is not supported for 82575 */ 7086 /* replication is not supported for 82575 */
7032 return; 7087 return;
diff --git a/drivers/net/ethernet/intel/igb/igb_ptp.c b/drivers/net/ethernet/intel/igb/igb_ptp.c
index c9b71c5bc475..d5ee7fa50723 100644
--- a/drivers/net/ethernet/intel/igb/igb_ptp.c
+++ b/drivers/net/ethernet/intel/igb/igb_ptp.c
@@ -262,6 +262,8 @@ void igb_ptp_init(struct igb_adapter *adapter)
262 struct e1000_hw *hw = &adapter->hw; 262 struct e1000_hw *hw = &adapter->hw;
263 263
264 switch (hw->mac.type) { 264 switch (hw->mac.type) {
265 case e1000_i210:
266 case e1000_i211:
265 case e1000_i350: 267 case e1000_i350:
266 case e1000_82580: 268 case e1000_82580:
267 adapter->caps.owner = THIS_MODULE; 269 adapter->caps.owner = THIS_MODULE;
@@ -362,6 +364,8 @@ void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
362 unsigned long flags; 364 unsigned long flags;
363 365
364 switch (adapter->hw.mac.type) { 366 switch (adapter->hw.mac.type) {
367 case e1000_i210:
368 case e1000_i211:
365 case e1000_i350: 369 case e1000_i350:
366 case e1000_82580: 370 case e1000_82580:
367 case e1000_82576: 371 case e1000_82576:
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 15:45:06 -0400