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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-08-19 09:55:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:41 -0400
commitf96a3383cfede841cdf80a5927f14478981ed78c (patch)
tree8d6da93bbf355c2f95a2591d116b18b8b6e42b1f
parent9fa32c6b0275ab1e8b19f74fbfa3ed8411345db6 (diff)
MIPS: RBTX4927: More explicit initialization
* Make sure all interrupts cleared on startup * Initialize some GPIOs Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c5
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c9
-rw-r--r--include/asm-mips/txx9/rbtx4927.h2
3 files changed, 16 insertions, 0 deletions
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 00cd5231da30..22076e3f03a8 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -142,6 +142,11 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
142{ 142{
143 int i; 143 int i;
144 144
145 /* mask all IOC interrupts */
146 writeb(0, rbtx4927_imask_addr);
147 /* clear SoftInt interrupts */
148 writeb(0, rbtx4927_softint_addr);
149
145 for (i = RBTX4927_IRQ_IOC; 150 for (i = RBTX4927_IRQ_IOC;
146 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) 151 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
147 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 152 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 0d39bafea794..5985f330838a 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -48,6 +48,7 @@
48#include <linux/ioport.h> 48#include <linux/ioport.h>
49#include <linux/platform_device.h> 49#include <linux/platform_device.h>
50#include <linux/delay.h> 50#include <linux/delay.h>
51#include <linux/gpio.h>
51#include <asm/io.h> 52#include <asm/io.h>
52#include <asm/reboot.h> 53#include <asm/reboot.h>
53#include <asm/txx9/generic.h> 54#include <asm/txx9/generic.h>
@@ -212,6 +213,14 @@ static void __init rbtx4927_mem_setup(void)
212 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 213 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
213#endif 214#endif
214 215
216 /* TX4927-SIO DTR on (PIO[15]) */
217 gpio_request(15, "sio-dtr");
218 gpio_direction_output(15, 1);
219 gpio_request(0, "led");
220 gpio_direction_output(0, 1);
221 gpio_request(1, "led");
222 gpio_direction_output(1, 1);
223
215 tx4927_sio_init(0, 0); 224 tx4927_sio_init(0, 0);
216#ifdef CONFIG_SERIAL_TXX9_CONSOLE 225#ifdef CONFIG_SERIAL_TXX9_CONSOLE
217 argptr = prom_getcmdline(); 226 argptr = prom_getcmdline();
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index 6fcec912c143..c6015463432e 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -36,6 +36,7 @@
36 36
37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) 37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) 38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
39#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) 40#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) 41#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) 42#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
@@ -47,6 +48,7 @@
47 48
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) 49#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) 50#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
51#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) 52#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \ 53#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) 54 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)