diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2014-01-24 14:12:37 -0500 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2014-03-26 05:01:30 -0400 |
| commit | f8b34c3fd5a3fe7820952400ebbbc0528ec80686 (patch) | |
| tree | 050623f94aa1e157c8176ee5748a2b1d5b55fcdc | |
| parent | 35571f4bdcae4bf2262fa0c94f56594dd0457f5a (diff) | |
ARC: [clockevent] simplify timer ISR
* Remove one liner IRQ ACK accessor, it was coming in the way of readability.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| -rw-r--r-- | arch/arc/kernel/time.c | 34 |
1 files changed, 15 insertions, 19 deletions
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index a8787bcbbc8e..71c42521c77f 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c | |||
| @@ -155,22 +155,6 @@ static void arc_timer_event_setup(unsigned int limit) | |||
| 155 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); | 155 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); |
| 156 | } | 156 | } |
| 157 | 157 | ||
| 158 | /* | ||
| 159 | * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic) | ||
| 160 | * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted) | ||
| 161 | * -Rearming is done by setting the IE bit | ||
| 162 | * | ||
| 163 | * Small optimisation: Normal code would have been | ||
| 164 | * if (irq_reenable) | ||
| 165 | * CTRL_REG = (IE | NH); | ||
| 166 | * else | ||
| 167 | * CTRL_REG = NH; | ||
| 168 | * However since IE is BIT0 we can fold the branch | ||
| 169 | */ | ||
| 170 | static void arc_timer_event_ack(unsigned int irq_reenable) | ||
| 171 | { | ||
| 172 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | ||
| 173 | } | ||
| 174 | 158 | ||
| 175 | static int arc_clkevent_set_next_event(unsigned long delta, | 159 | static int arc_clkevent_set_next_event(unsigned long delta, |
| 176 | struct clock_event_device *dev) | 160 | struct clock_event_device *dev) |
| @@ -207,10 +191,22 @@ static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { | |||
| 207 | 191 | ||
| 208 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) | 192 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) |
| 209 | { | 193 | { |
| 210 | struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device); | 194 | /* |
| 195 | * Note that generic IRQ core could have passed @evt for @dev_id if | ||
| 196 | * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() | ||
| 197 | */ | ||
| 198 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | ||
| 199 | int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC; | ||
| 200 | |||
| 201 | /* | ||
| 202 | * Any write to CTRL reg ACks the interrupt, we rewrite the | ||
| 203 | * Count when [N]ot [H]alted bit. | ||
| 204 | * And re-arm it if perioid by [I]nterrupt [E]nable bit | ||
| 205 | */ | ||
| 206 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | ||
| 207 | |||
| 208 | evt->event_handler(evt); | ||
| 211 | 209 | ||
| 212 | arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC); | ||
| 213 | clk->event_handler(clk); | ||
| 214 | return IRQ_HANDLED; | 210 | return IRQ_HANDLED; |
| 215 | } | 211 | } |
| 216 | 212 | ||
