diff options
author | Yijing Wang <wangyijing@huawei.com> | 2013-09-05 03:55:28 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-09-23 19:30:03 -0400 |
commit | f8a26fe637fc740ebb927ce25dcf036363a998df (patch) | |
tree | a3a84881bb5e83d303e3c53138adacde890a5ff7 | |
parent | fdfe151127a75de037c7e32cef110ae9c7c5e3c8 (diff) |
x86/pci: Use cached pci_dev->pcie_cap to simplify code
The PCI core caches the PCIe Capability offset in pci_dev->pcie_cap, so
use that instead of pci_find_capability(). Use pci_bus_set_ops() when
replacing the device pci_ops. And use #defines instead of numeric
constants.
[bhelgaas: changelog, also use PCI_EXP_LNKCTL_ASPMC]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r-- | arch/x86/pci/fixup.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index f5809fa2753e..b046e070e088 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c | |||
@@ -231,7 +231,7 @@ static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int wh | |||
231 | offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; | 231 | offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; |
232 | 232 | ||
233 | if ((offset) && (where == offset)) | 233 | if ((offset) && (where == offset)) |
234 | value = value & 0xfffffffc; | 234 | value = value & ~PCI_EXP_LNKCTL_ASPMC; |
235 | 235 | ||
236 | return raw_pci_write(pci_domain_nr(bus), bus->number, | 236 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
237 | devfn, where, size, value); | 237 | devfn, where, size, value); |
@@ -252,7 +252,7 @@ static struct pci_ops quirk_pcie_aspm_ops = { | |||
252 | */ | 252 | */ |
253 | static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) | 253 | static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) |
254 | { | 254 | { |
255 | int cap_base, i; | 255 | int i; |
256 | struct pci_bus *pbus; | 256 | struct pci_bus *pbus; |
257 | struct pci_dev *dev; | 257 | struct pci_dev *dev; |
258 | 258 | ||
@@ -278,7 +278,7 @@ static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) | |||
278 | for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) | 278 | for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) |
279 | quirk_aspm_offset[i] = 0; | 279 | quirk_aspm_offset[i] = 0; |
280 | 280 | ||
281 | pbus->ops = pbus->parent->ops; | 281 | pci_bus_set_ops(pbus, pbus->parent->ops); |
282 | } else { | 282 | } else { |
283 | /* | 283 | /* |
284 | * If devices are attached to the root port at power-up or | 284 | * If devices are attached to the root port at power-up or |
@@ -286,13 +286,15 @@ static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) | |||
286 | * each root port to save the register offsets and replace the | 286 | * each root port to save the register offsets and replace the |
287 | * bus ops. | 287 | * bus ops. |
288 | */ | 288 | */ |
289 | list_for_each_entry(dev, &pbus->devices, bus_list) { | 289 | list_for_each_entry(dev, &pbus->devices, bus_list) |
290 | /* There are 0 to 8 devices attached to this bus */ | 290 | /* There are 0 to 8 devices attached to this bus */ |
291 | cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP); | 291 | quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = |
292 | quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10; | 292 | dev->pcie_cap + PCI_EXP_LNKCTL; |
293 | } | 293 | |
294 | pbus->ops = &quirk_pcie_aspm_ops; | 294 | pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops); |
295 | dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n"); | ||
295 | } | 296 | } |
297 | |||
296 | } | 298 | } |
297 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); | 299 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); |
298 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); | 300 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); |