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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-03-16 06:40:57 -0400
committerTero Kristo <t-kristo@ti.com>2015-03-24 14:23:50 -0400
commitf757d1b047dfe704d459746c289f27934de6f91e (patch)
tree436d2464a1ebdb3e7632e6dfa6c3ab46fb2c140a
parentc807dbedb5e5adbd4e1e2d07574d230df924a5a7 (diff)
clk: ti: clk-3xxx: Correct McBSP related DT clock definitions
In DT boot we do not have devices named as omap-mcbsp.X. Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2). Collect the McBSP clock definition in one location at the same time. Fixes the following warning on boot: [ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16 [ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
-rw-r--r--drivers/clk/ti/clk-3xxx.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 383a06e49b09..757636d166cf 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -34,7 +34,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
34 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), 34 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
35 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), 35 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
36 DT_CLK(NULL, "sys_altclk", "sys_altclk"), 36 DT_CLK(NULL, "sys_altclk", "sys_altclk"),
37 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
38 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), 37 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
39 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), 38 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
40 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), 39 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
@@ -82,8 +81,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
82 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), 81 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
83 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), 82 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
84 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), 83 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
85 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
86 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
87 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), 84 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
88 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), 85 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
89 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), 86 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
@@ -122,10 +119,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
122 DT_CLK(NULL, "uart1_ick", "uart1_ick"), 119 DT_CLK(NULL, "uart1_ick", "uart1_ick"),
123 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), 120 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
124 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), 121 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
125 DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
126 DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
127 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
128 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
129 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), 122 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
130 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), 123 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
131 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), 124 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
@@ -179,15 +172,17 @@ static struct ti_dt_clk omap3xxx_clks[] = {
179 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), 172 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
180 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), 173 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
181 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), 174 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
182 DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), 175 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
183 DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), 176 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
184 DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), 177 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
185 DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
186 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), 178 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
187 DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"), 179 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
180 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
181 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
188 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), 182 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
189 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), 183 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
190 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), 184 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
185 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
191 DT_CLK("etb", "emu_src_ck", "emu_src_ck"), 186 DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
192 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), 187 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
193 DT_CLK(NULL, "pclk_fck", "pclk_fck"), 188 DT_CLK(NULL, "pclk_fck", "pclk_fck"),