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authorAddy Ke <addy.ke@rock-chips.com>2014-12-03 21:49:35 -0500
committerHeiko Stuebner <heiko@sntech.de>2014-12-21 08:20:03 -0500
commitf74ba117dab86b35e15f8b5a8d913145f3e72ca1 (patch)
tree5d48cdfe406ed69bdab59fa1bc3cf16b74d3dff8
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
ARM: dts: rockchip: set dw_mmc max-freq 150Mhz
All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288 are limited to 150Mhz. It was mainly caused by two reasons: - RK3288's IO pad(except DDR IO pad) is generic, which can only support the max of 150Mhz. - Mmc controller was designed at 150Mhz, and the pressure test by IC team was based on this freequency point. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index fd19f00784bd..3aad41d873d3 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -151,6 +151,7 @@
151 151
152 sdmmc: dwmmc@ff0c0000 { 152 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc"; 153 compatible = "rockchip,rk3288-dw-mshc";
154 clock-freq-min-max = <400000 150000000>;
154 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 155 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
155 clock-names = "biu", "ciu"; 156 clock-names = "biu", "ciu";
156 fifo-depth = <0x100>; 157 fifo-depth = <0x100>;
@@ -161,6 +162,7 @@
161 162
162 sdio0: dwmmc@ff0d0000 { 163 sdio0: dwmmc@ff0d0000 {
163 compatible = "rockchip,rk3288-dw-mshc"; 164 compatible = "rockchip,rk3288-dw-mshc";
165 clock-freq-min-max = <400000 150000000>;
164 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; 166 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
165 clock-names = "biu", "ciu"; 167 clock-names = "biu", "ciu";
166 fifo-depth = <0x100>; 168 fifo-depth = <0x100>;
@@ -171,6 +173,7 @@
171 173
172 sdio1: dwmmc@ff0e0000 { 174 sdio1: dwmmc@ff0e0000 {
173 compatible = "rockchip,rk3288-dw-mshc"; 175 compatible = "rockchip,rk3288-dw-mshc";
176 clock-freq-min-max = <400000 150000000>;
174 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; 177 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
175 clock-names = "biu", "ciu"; 178 clock-names = "biu", "ciu";
176 fifo-depth = <0x100>; 179 fifo-depth = <0x100>;
@@ -181,6 +184,7 @@
181 184
182 emmc: dwmmc@ff0f0000 { 185 emmc: dwmmc@ff0f0000 {
183 compatible = "rockchip,rk3288-dw-mshc"; 186 compatible = "rockchip,rk3288-dw-mshc";
187 clock-freq-min-max = <400000 150000000>;
184 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 188 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
185 clock-names = "biu", "ciu"; 189 clock-names = "biu", "ciu";
186 fifo-depth = <0x100>; 190 fifo-depth = <0x100>;