aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2014-10-02 09:31:09 -0400
committerMark Brown <broonie@kernel.org>2014-10-02 12:06:26 -0400
commitf7477c2be8689ee8355db345f107744c9bd7f112 (patch)
treede5e0e2142413e2b399159134aea7f4a06eb52f1
parent2a285299446cccbaf9ba47403e8f2ce578cd1ad1 (diff)
spi: dw-mid: follow new DMAengine workflow
Though intel-mid-dma does not follow a new DMA workflow (*) let's prepare SPI DW driver for that. (*) The client is obliged to call dma_async_issue_pending() which starts the actual transfers. Old DMA drivers do not follow this, since requirement was introduced in the discussion of [1]. [1] http://www.spinics.net/lists/arm-kernel/msg125987.html Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-dw-mid.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a507add6231e..46c6d58e1fda 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -150,7 +150,7 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
150 &dws->tx_sgl, 150 &dws->tx_sgl,
151 1, 151 1,
152 DMA_MEM_TO_DEV, 152 DMA_MEM_TO_DEV,
153 DMA_PREP_INTERRUPT); 153 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
154 txdesc->callback = dw_spi_dma_done; 154 txdesc->callback = dw_spi_dma_done;
155 txdesc->callback_param = dws; 155 txdesc->callback_param = dws;
156 156
@@ -172,13 +172,17 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
172 &dws->rx_sgl, 172 &dws->rx_sgl,
173 1, 173 1,
174 DMA_DEV_TO_MEM, 174 DMA_DEV_TO_MEM,
175 DMA_PREP_INTERRUPT); 175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
176 rxdesc->callback = dw_spi_dma_done; 176 rxdesc->callback = dw_spi_dma_done;
177 rxdesc->callback_param = dws; 177 rxdesc->callback_param = dws;
178 178
179 /* rx must be started before tx due to spi instinct */ 179 /* rx must be started before tx due to spi instinct */
180 dmaengine_submit(rxdesc); 180 dmaengine_submit(rxdesc);
181 dma_async_issue_pending(dws->rxchan);
182
181 dmaengine_submit(txdesc); 183 dmaengine_submit(txdesc);
184 dma_async_issue_pending(dws->txchan);
185
182 return 0; 186 return 0;
183} 187}
184 188