diff options
author | Philipp Zabel <p.zabel@pengutronix.de> | 2015-03-10 10:03:43 -0400 |
---|---|---|
committer | Philipp Zabel <p.zabel@pengutronix.de> | 2015-03-31 06:03:54 -0400 |
commit | f7089d923eacb9c8e57d8492699662756881b54d (patch) | |
tree | 9751d3e0c1daed286261d150b961e9b81be99bd1 | |
parent | 91fd89660ba2e8ee59a587294fa9b17761691b05 (diff) |
gpu: ipu-v3: limit pixel clock divider to 8-bits
The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.
Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-di.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c index 3ddfb3d0b64d..2970c6bb668c 100644 --- a/drivers/gpu/ipu-v3/ipu-di.c +++ b/drivers/gpu/ipu-v3/ipu-di.c | |||
@@ -441,8 +441,7 @@ static void ipu_di_config_clock(struct ipu_di *di, | |||
441 | 441 | ||
442 | in_rate = clk_get_rate(clk); | 442 | in_rate = clk_get_rate(clk); |
443 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); | 443 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
444 | if (div == 0) | 444 | div = clamp(div, 1U, 255U); |
445 | div = 1; | ||
446 | 445 | ||
447 | clkgen0 = div << 4; | 446 | clkgen0 = div << 4; |
448 | } | 447 | } |
@@ -459,8 +458,7 @@ static void ipu_di_config_clock(struct ipu_di *di, | |||
459 | 458 | ||
460 | clkrate = clk_get_rate(di->clk_ipu); | 459 | clkrate = clk_get_rate(di->clk_ipu); |
461 | div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); | 460 | div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); |
462 | if (div == 0) | 461 | div = clamp(div, 1U, 255U); |
463 | div = 1; | ||
464 | rate = clkrate / div; | 462 | rate = clkrate / div; |
465 | 463 | ||
466 | error = rate / (sig->mode.pixelclock / 1000); | 464 | error = rate / (sig->mode.pixelclock / 1000); |
@@ -483,8 +481,7 @@ static void ipu_di_config_clock(struct ipu_di *di, | |||
483 | 481 | ||
484 | in_rate = clk_get_rate(clk); | 482 | in_rate = clk_get_rate(clk); |
485 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); | 483 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
486 | if (div == 0) | 484 | div = clamp(div, 1U, 255U); |
487 | div = 1; | ||
488 | 485 | ||
489 | clkgen0 = div << 4; | 486 | clkgen0 = div << 4; |
490 | } | 487 | } |