diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2014-11-12 13:08:32 -0500 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-11-23 11:00:23 -0500 |
| commit | f6c3b0460850574f0131f8fd8903d8a766f35cac (patch) | |
| tree | dc6fed9c35c852e0512019fb63fdd1aff68bc715 | |
| parent | ba61e8938ffcc79ce4aba834a1218d0e958b49b7 (diff) | |
ARM: sun6i: DT: Add PLL6 multiple outputs
PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 4c4792fea0b7..529c73803976 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi | |||
| @@ -132,11 +132,11 @@ | |||
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | pll6: clk@01c20028 { | 134 | pll6: clk@01c20028 { |
| 135 | #clock-cells = <0>; | 135 | #clock-cells = <1>; |
| 136 | compatible = "allwinner,sun6i-a31-pll6-clk"; | 136 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
| 137 | reg = <0x01c20028 0x4>; | 137 | reg = <0x01c20028 0x4>; |
| 138 | clocks = <&osc24M>; | 138 | clocks = <&osc24M>; |
| 139 | clock-output-names = "pll6"; | 139 | clock-output-names = "pll6", "pll6x2"; |
| 140 | }; | 140 | }; |
| 141 | 141 | ||
| 142 | cpu: cpu@01c20050 { | 142 | cpu: cpu@01c20050 { |
| @@ -166,7 +166,7 @@ | |||
| 166 | #clock-cells = <0>; | 166 | #clock-cells = <0>; |
| 167 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | 167 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; |
| 168 | reg = <0x01c20054 0x4>; | 168 | reg = <0x01c20054 0x4>; |
| 169 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | 169 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; |
| 170 | clock-output-names = "ahb1_mux"; | 170 | clock-output-names = "ahb1_mux"; |
| 171 | }; | 171 | }; |
| 172 | 172 | ||
| @@ -221,7 +221,7 @@ | |||
| 221 | #clock-cells = <0>; | 221 | #clock-cells = <0>; |
| 222 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; | 222 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 223 | reg = <0x01c20058 0x4>; | 223 | reg = <0x01c20058 0x4>; |
| 224 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | 224 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
| 225 | clock-output-names = "apb2_mux"; | 225 | clock-output-names = "apb2_mux"; |
| 226 | }; | 226 | }; |
| 227 | 227 | ||
| @@ -248,7 +248,7 @@ | |||
| 248 | #clock-cells = <0>; | 248 | #clock-cells = <0>; |
| 249 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 249 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 250 | reg = <0x01c20088 0x4>; | 250 | reg = <0x01c20088 0x4>; |
| 251 | clocks = <&osc24M>, <&pll6>; | 251 | clocks = <&osc24M>, <&pll6 0>; |
| 252 | clock-output-names = "mmc0"; | 252 | clock-output-names = "mmc0"; |
| 253 | }; | 253 | }; |
| 254 | 254 | ||
| @@ -256,7 +256,7 @@ | |||
| 256 | #clock-cells = <0>; | 256 | #clock-cells = <0>; |
| 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 258 | reg = <0x01c2008c 0x4>; | 258 | reg = <0x01c2008c 0x4>; |
| 259 | clocks = <&osc24M>, <&pll6>; | 259 | clocks = <&osc24M>, <&pll6 0>; |
| 260 | clock-output-names = "mmc1"; | 260 | clock-output-names = "mmc1"; |
| 261 | }; | 261 | }; |
| 262 | 262 | ||
| @@ -264,7 +264,7 @@ | |||
| 264 | #clock-cells = <0>; | 264 | #clock-cells = <0>; |
| 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 266 | reg = <0x01c20090 0x4>; | 266 | reg = <0x01c20090 0x4>; |
| 267 | clocks = <&osc24M>, <&pll6>; | 267 | clocks = <&osc24M>, <&pll6 0>; |
| 268 | clock-output-names = "mmc2"; | 268 | clock-output-names = "mmc2"; |
| 269 | }; | 269 | }; |
| 270 | 270 | ||
| @@ -272,7 +272,7 @@ | |||
| 272 | #clock-cells = <0>; | 272 | #clock-cells = <0>; |
| 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 274 | reg = <0x01c20094 0x4>; | 274 | reg = <0x01c20094 0x4>; |
| 275 | clocks = <&osc24M>, <&pll6>; | 275 | clocks = <&osc24M>, <&pll6 0>; |
| 276 | clock-output-names = "mmc3"; | 276 | clock-output-names = "mmc3"; |
| 277 | }; | 277 | }; |
| 278 | 278 | ||
| @@ -280,7 +280,7 @@ | |||
| 280 | #clock-cells = <0>; | 280 | #clock-cells = <0>; |
| 281 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 281 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 282 | reg = <0x01c200a0 0x4>; | 282 | reg = <0x01c200a0 0x4>; |
| 283 | clocks = <&osc24M>, <&pll6>; | 283 | clocks = <&osc24M>, <&pll6 0>; |
| 284 | clock-output-names = "spi0"; | 284 | clock-output-names = "spi0"; |
| 285 | }; | 285 | }; |
| 286 | 286 | ||
| @@ -288,7 +288,7 @@ | |||
| 288 | #clock-cells = <0>; | 288 | #clock-cells = <0>; |
| 289 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 289 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 290 | reg = <0x01c200a4 0x4>; | 290 | reg = <0x01c200a4 0x4>; |
| 291 | clocks = <&osc24M>, <&pll6>; | 291 | clocks = <&osc24M>, <&pll6 0>; |
| 292 | clock-output-names = "spi1"; | 292 | clock-output-names = "spi1"; |
| 293 | }; | 293 | }; |
| 294 | 294 | ||
| @@ -296,7 +296,7 @@ | |||
| 296 | #clock-cells = <0>; | 296 | #clock-cells = <0>; |
| 297 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 297 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 298 | reg = <0x01c200a8 0x4>; | 298 | reg = <0x01c200a8 0x4>; |
| 299 | clocks = <&osc24M>, <&pll6>; | 299 | clocks = <&osc24M>, <&pll6 0>; |
| 300 | clock-output-names = "spi2"; | 300 | clock-output-names = "spi2"; |
| 301 | }; | 301 | }; |
| 302 | 302 | ||
| @@ -304,7 +304,7 @@ | |||
| 304 | #clock-cells = <0>; | 304 | #clock-cells = <0>; |
| 305 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 305 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 306 | reg = <0x01c200ac 0x4>; | 306 | reg = <0x01c200ac 0x4>; |
| 307 | clocks = <&osc24M>, <&pll6>; | 307 | clocks = <&osc24M>, <&pll6 0>; |
| 308 | clock-output-names = "spi3"; | 308 | clock-output-names = "spi3"; |
| 309 | }; | 309 | }; |
| 310 | 310 | ||
| @@ -364,7 +364,7 @@ | |||
| 364 | 364 | ||
| 365 | /* DMA controller requires AHB1 clocked from PLL6 */ | 365 | /* DMA controller requires AHB1 clocked from PLL6 */ |
| 366 | assigned-clocks = <&ahb1_mux>; | 366 | assigned-clocks = <&ahb1_mux>; |
| 367 | assigned-clock-parents = <&pll6>; | 367 | assigned-clock-parents = <&pll6 0>; |
| 368 | }; | 368 | }; |
| 369 | 369 | ||
| 370 | mmc0: mmc@01c0f000 { | 370 | mmc0: mmc@01c0f000 { |
| @@ -844,7 +844,7 @@ | |||
| 844 | ar100: ar100_clk { | 844 | ar100: ar100_clk { |
| 845 | compatible = "allwinner,sun6i-a31-ar100-clk"; | 845 | compatible = "allwinner,sun6i-a31-ar100-clk"; |
| 846 | #clock-cells = <0>; | 846 | #clock-cells = <0>; |
| 847 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | 847 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
| 848 | clock-output-names = "ar100"; | 848 | clock-output-names = "ar100"; |
| 849 | }; | 849 | }; |
| 850 | 850 | ||