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authorSujith Manoharan <c_manoha@qca.qualcomm.com>2015-01-12 05:30:02 -0500
committerKalle Valo <kvalo@qca.qualcomm.com>2015-01-12 06:51:57 -0500
commitf6603ff2b7a8e02b748dd1acf00fcde78eb5dbcb (patch)
tree50fefa3fcde7b54e210e1c193a5d0aef459ca02e
parent350b193ebd50f6c70ba4a82541300cf236c904d8 (diff)
ath10k: Fix DMA burst size
A value of zero indicates that 128B is the maximum DMA request size for read/writes. But PCI cards based on AR9880 can support 256B, so enable this for the 10.2 firmware. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
-rw-r--r--drivers/net/wireless/ath/ath10k/hw.h3
-rw-r--r--drivers/net/wireless/ath/ath10k/wmi.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index 5729901923ac..7b771ae7789f 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -183,6 +183,9 @@ struct ath10k_pktlog_hdr {
183#define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 183#define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
184#define TARGET_10X_MAX_FRAG_ENTRIES 0 184#define TARGET_10X_MAX_FRAG_ENTRIES 0
185 185
186/* 10.2 parameters */
187#define TARGET_10_2_DMA_BURST_SIZE 1
188
186/* Target specific defines for WMI-TLV firmware */ 189/* Target specific defines for WMI-TLV firmware */
187#define TARGET_TLV_NUM_VDEVS 3 190#define TARGET_TLV_NUM_VDEVS 3
188#define TARGET_TLV_NUM_STATIONS 32 191#define TARGET_TLV_NUM_STATIONS 32
diff --git a/drivers/net/wireless/ath/ath10k/wmi.c b/drivers/net/wireless/ath/ath10k/wmi.c
index ac742905331b..b103122c5874 100644
--- a/drivers/net/wireless/ath/ath10k/wmi.c
+++ b/drivers/net/wireless/ath/ath10k/wmi.c
@@ -3744,7 +3744,7 @@ static struct sk_buff *ath10k_wmi_10_2_op_gen_init(struct ath10k *ar)
3744 config.mcast2ucast_mode = __cpu_to_le32(TARGET_10X_MCAST2UCAST_MODE); 3744 config.mcast2ucast_mode = __cpu_to_le32(TARGET_10X_MCAST2UCAST_MODE);
3745 config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE); 3745 config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
3746 config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES); 3746 config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
3747 config.dma_burst_size = __cpu_to_le32(TARGET_10X_DMA_BURST_SIZE); 3747 config.dma_burst_size = __cpu_to_le32(TARGET_10_2_DMA_BURST_SIZE);
3748 config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM); 3748 config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
3749 3749
3750 val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 3750 val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;