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authorGraf Yang <graf.yang@analog.com>2009-05-06 05:59:11 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:11:26 -0400
commitf5879fda09ea98d7aa845a0e0fa7e508452e5f9f (patch)
treeb1404b8cbaa64758f0d1caac3349384e42e34057
parentf339f46b05cfe289024b15a0525c8b61f1426a88 (diff)
Blackfin: add MDMA defines to make cross-variant coding easier
Add some defines to make the BF538/BF561 look like most other Blackfin parts in that it has a MDMA0 channel available for low level init. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h19
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h59
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h56
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h29
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h56
5 files changed, 200 insertions, 19 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index ea25371a922b..6f628353dde3 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -68,25 +68,6 @@
68#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 68#define OFFSET_SCR 0x1C /* SCR Scratch Register */
69#define OFFSET_GCTL 0x24 /* Global Control Register */ 69#define OFFSET_GCTL 0x24 /* Global Control Register */
70 70
71
72#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS
73#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR
74#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR
75#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT
76#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT
77#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT
78#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT
79#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY
80#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY
81#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY
82#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY
83#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG
84#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG
85#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_S0_CONFIG
86#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS
87#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS
88
89
90/* DPMC*/ 71/* DPMC*/
91#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 72#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
92#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 73#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 7a5f74c3cf6e..99ca3f4305e2 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1247,6 +1247,65 @@
1247#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) 1247#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
1248#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 1248#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
1249#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) 1249#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
1250
1251#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG()
1252#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
1253#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS()
1254#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
1255#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY()
1256#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
1257#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY()
1258#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
1259#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT()
1260#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
1261#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT()
1262#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
1263#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR()
1264#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
1265#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG()
1266#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
1267#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS()
1268#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
1269#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY()
1270#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
1271#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY()
1272#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
1273#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT()
1274#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
1275#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT()
1276#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
1277#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR()
1278#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
1279
1280#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG()
1281#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
1282#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS()
1283#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
1284#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY()
1285#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
1286#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY()
1287#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
1288#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT()
1289#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
1290#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT()
1291#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
1292#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR()
1293#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
1294#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG()
1295#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
1296#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS()
1297#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
1298#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY()
1299#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
1300#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY()
1301#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
1302#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT()
1303#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
1304#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT()
1305#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
1306#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR()
1307#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
1308
1250#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) 1309#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
1251#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 1310#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
1252#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 1311#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 6adbfcc65a35..bdc330cd0e1c 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -412,6 +412,62 @@
412#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ 412#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
413#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ 413#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
414 414
415#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
416#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
417#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
418#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
419#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
420#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
421#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
422#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
423#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
424#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
425#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
426#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
427#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
428
429#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
430#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
431#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
432#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
433#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
434#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
435#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
436#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
437#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
438#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
439#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
440#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
441#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
442
443#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
444#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
445#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
446#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
447#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
448#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
449#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
450#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
451#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
452#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
453#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
454#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
455#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
456
457#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
458#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
459#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
460#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
461#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
462#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
463#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
464#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
465#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
466#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
467#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
468#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
469#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
470
415 471
416/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ 472/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
417#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 473#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 95d609f11c97..9d9858c2be68 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1526,6 +1526,35 @@
1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() 1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) 1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1528 1528
1529#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG()
1530#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
1531#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS()
1532#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
1533#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY()
1534#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
1535#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY()
1536#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
1537#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT()
1538#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
1539#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT()
1540#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
1541#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR()
1542#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
1543#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG()
1544#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
1545#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS()
1546#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
1547#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY()
1548#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
1549#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY()
1550#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
1551#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT()
1552#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
1553#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT()
1554#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
1555#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
1556#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
1557
1529/* These need to be last due to the cdef/linux inter-dependencies */ 1558/* These need to be last due to the cdef/linux inter-dependencies */
1530#include <asm/irq.h> 1559#include <asm/irq.h>
1531 1560
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index cf922295f4ce..5fc0f05026e0 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -796,6 +796,62 @@
796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ 796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ 797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
798 798
799#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
800#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
801#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
802#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
803#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
804#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
805#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
806#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
807#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
808#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
809#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
810#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
811#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
812
813#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
814#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
815#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
816#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
817#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
818#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
819#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
820#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
821#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
822#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
823#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
824#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
825#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
826
827#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
828#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
829#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
830#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
831#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
832#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
833#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
834#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
835#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
836#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
837#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
838#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
839#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
840
841#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
842#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
843#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
844#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
845#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
846#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
847#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
848#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
849#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
850#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
851#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
852#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
853#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
854
799/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 855/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
800#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ 856#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
801#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ 857#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */