diff options
| author | Philipp Zabel <p.zabel@pengutronix.de> | 2013-06-21 09:36:11 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-07-14 20:28:05 -0400 |
| commit | f5786b8e934e77f76f689c515baa582ff5a196ec (patch) | |
| tree | 15cf3ca319a4adce435134b7ef41fc547c9c2876 | |
| parent | ad81f0545ef01ea651886dddac4bef6cec930092 (diff) | |
ARM i.MX53: Fix UART pad configuration
The current default pad configuration for UART RX and TX pads sets a 360k
pull-down and writes 1 to a reserved bit (1 << 0). It doesn't seem right to
me that in idle state, the UART has to keep the signal high against a
pull-down resistor.
This patch instead sets a 100k pull-up, which incidentally corresponds to the
register reset value for all but one (MX53_PAD_KEY_ROW0__UART4_RXD_MUX) pad,
and removes the write to the reserved bit.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3895fbba8fce..569aa9f2c4ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -725,15 +725,15 @@ | |||
| 725 | uart1 { | 725 | uart1 { |
| 726 | pinctrl_uart1_1: uart1grp-1 { | 726 | pinctrl_uart1_1: uart1grp-1 { |
| 727 | fsl,pins = < | 727 | fsl,pins = < |
| 728 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5 | 728 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 |
| 729 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5 | 729 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 |
| 730 | >; | 730 | >; |
| 731 | }; | 731 | }; |
| 732 | 732 | ||
| 733 | pinctrl_uart1_2: uart1grp-2 { | 733 | pinctrl_uart1_2: uart1grp-2 { |
| 734 | fsl,pins = < | 734 | fsl,pins = < |
| 735 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5 | 735 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 |
| 736 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 | 736 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 |
| 737 | >; | 737 | >; |
| 738 | }; | 738 | }; |
| 739 | 739 | ||
| @@ -748,8 +748,8 @@ | |||
| 748 | uart2 { | 748 | uart2 { |
| 749 | pinctrl_uart2_1: uart2grp-1 { | 749 | pinctrl_uart2_1: uart2grp-1 { |
| 750 | fsl,pins = < | 750 | fsl,pins = < |
| 751 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 | 751 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 |
| 752 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | 752 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 |
| 753 | >; | 753 | >; |
| 754 | }; | 754 | }; |
| 755 | 755 | ||
| @@ -766,17 +766,17 @@ | |||
| 766 | uart3 { | 766 | uart3 { |
| 767 | pinctrl_uart3_1: uart3grp-1 { | 767 | pinctrl_uart3_1: uart3grp-1 { |
| 768 | fsl,pins = < | 768 | fsl,pins = < |
| 769 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 | 769 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 |
| 770 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 | 770 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 |
| 771 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5 | 771 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 |
| 772 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5 | 772 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 |
| 773 | >; | 773 | >; |
| 774 | }; | 774 | }; |
| 775 | 775 | ||
| 776 | pinctrl_uart3_2: uart3grp-2 { | 776 | pinctrl_uart3_2: uart3grp-2 { |
| 777 | fsl,pins = < | 777 | fsl,pins = < |
| 778 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 | 778 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 |
| 779 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 | 779 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 |
| 780 | >; | 780 | >; |
| 781 | }; | 781 | }; |
| 782 | 782 | ||
| @@ -785,8 +785,8 @@ | |||
| 785 | uart4 { | 785 | uart4 { |
| 786 | pinctrl_uart4_1: uart4grp-1 { | 786 | pinctrl_uart4_1: uart4grp-1 { |
| 787 | fsl,pins = < | 787 | fsl,pins = < |
| 788 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5 | 788 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 |
| 789 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5 | 789 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 |
| 790 | >; | 790 | >; |
| 791 | }; | 791 | }; |
| 792 | }; | 792 | }; |
| @@ -794,8 +794,8 @@ | |||
| 794 | uart5 { | 794 | uart5 { |
| 795 | pinctrl_uart5_1: uart5grp-1 { | 795 | pinctrl_uart5_1: uart5grp-1 { |
| 796 | fsl,pins = < | 796 | fsl,pins = < |
| 797 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5 | 797 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 |
| 798 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5 | 798 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 |
| 799 | >; | 799 | >; |
| 800 | }; | 800 | }; |
| 801 | }; | 801 | }; |