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authorJohn Crispin <blogic@openwrt.org>2014-10-08 22:02:53 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 01:45:24 -0500
commitf576fb6a0700c76a68ca7b45a3cfbd70399b24ab (patch)
tree21223a4a74d70c02e03f95f566a483982da863d9
parent4248f7f121b755b272a3c77a1a5601faa6004350 (diff)
MIPS: ralink: cleanup the soc specific pinmux data
Before we had a pinctrl driver we used a custom OF api. This patch converts the soc specific pinmux data to a new set of structs. We also add some new pinmux setings. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h41
-rw-r--r--arch/mips/include/asm/mach-ralink/pinmux.h55
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x.h35
-rw-r--r--arch/mips/include/asm/mach-ralink/rt3883.h16
-rw-r--r--arch/mips/ralink/common.h19
-rw-r--r--arch/mips/ralink/mt7620.c159
-rw-r--r--arch/mips/ralink/prom.c1
-rw-r--r--arch/mips/ralink/rt288x.c62
-rw-r--r--arch/mips/ralink/rt305x.c153
-rw-r--r--arch/mips/ralink/rt3883.c173
10 files changed, 294 insertions, 420 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 7ff929005d15..a05c14c23155 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -82,7 +82,6 @@
82#define MT7620_DDR2_SIZE_MIN 32 82#define MT7620_DDR2_SIZE_MIN 32
83#define MT7620_DDR2_SIZE_MAX 256 83#define MT7620_DDR2_SIZE_MAX 256
84 84
85#define MT7620_GPIO_MODE_I2C BIT(0)
86#define MT7620_GPIO_MODE_UART0_SHIFT 2 85#define MT7620_GPIO_MODE_UART0_SHIFT 2
87#define MT7620_GPIO_MODE_UART0_MASK 0x7 86#define MT7620_GPIO_MODE_UART0_MASK 0x7
88#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) 87#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
@@ -94,16 +93,36 @@
94#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 93#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
95#define MT7620_GPIO_MODE_GPIO_I2S 0x6 94#define MT7620_GPIO_MODE_GPIO_I2S 0x6
96#define MT7620_GPIO_MODE_GPIO 0x7 95#define MT7620_GPIO_MODE_GPIO 0x7
97#define MT7620_GPIO_MODE_UART1 BIT(5) 96
98#define MT7620_GPIO_MODE_MDIO BIT(8) 97#define MT7620_GPIO_MODE_NAND 0
99#define MT7620_GPIO_MODE_RGMII1 BIT(9) 98#define MT7620_GPIO_MODE_SD 1
100#define MT7620_GPIO_MODE_RGMII2 BIT(10) 99#define MT7620_GPIO_MODE_ND_SD_GPIO 2
101#define MT7620_GPIO_MODE_SPI BIT(11) 100#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
102#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) 101#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
103#define MT7620_GPIO_MODE_WLED BIT(13) 102
104#define MT7620_GPIO_MODE_JTAG BIT(15) 103#define MT7620_GPIO_MODE_PCIE_RST 0
105#define MT7620_GPIO_MODE_EPHY BIT(15) 104#define MT7620_GPIO_MODE_PCIE_REF 1
106#define MT7620_GPIO_MODE_WDT BIT(22) 105#define MT7620_GPIO_MODE_PCIE_GPIO 2
106#define MT7620_GPIO_MODE_PCIE_MASK 0x3
107#define MT7620_GPIO_MODE_PCIE_SHIFT 16
108
109#define MT7620_GPIO_MODE_WDT_RST 0
110#define MT7620_GPIO_MODE_WDT_REF 1
111#define MT7620_GPIO_MODE_WDT_GPIO 2
112#define MT7620_GPIO_MODE_WDT_MASK 0x3
113#define MT7620_GPIO_MODE_WDT_SHIFT 21
114
115#define MT7620_GPIO_MODE_I2C 0
116#define MT7620_GPIO_MODE_UART1 5
117#define MT7620_GPIO_MODE_MDIO 8
118#define MT7620_GPIO_MODE_RGMII1 9
119#define MT7620_GPIO_MODE_RGMII2 10
120#define MT7620_GPIO_MODE_SPI 11
121#define MT7620_GPIO_MODE_SPI_REF_CLK 12
122#define MT7620_GPIO_MODE_WLED 13
123#define MT7620_GPIO_MODE_JTAG 15
124#define MT7620_GPIO_MODE_EPHY 15
125#define MT7620_GPIO_MODE_PA 20
107 126
108static inline int mt7620_get_eco(void) 127static inline int mt7620_get_eco(void)
109{ 128{
diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h
new file mode 100644
index 000000000000..be106cb2e26d
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
@@ -0,0 +1,55 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * publishhed by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _RT288X_PINMUX_H__
10#define _RT288X_PINMUX_H__
11
12#define FUNC(name, value, pin_first, pin_count) \
13 { name, value, pin_first, pin_count }
14
15#define GRP(_name, _func, _mask, _shift) \
16 { .name = _name, .mask = _mask, .shift = _shift, \
17 .func = _func, .gpio = _mask, \
18 .func_count = ARRAY_SIZE(_func) }
19
20#define GRP_G(_name, _func, _mask, _gpio, _shift) \
21 { .name = _name, .mask = _mask, .shift = _shift, \
22 .func = _func, .gpio = _gpio, \
23 .func_count = ARRAY_SIZE(_func) }
24
25struct rt2880_pmx_group;
26
27struct rt2880_pmx_func {
28 const char *name;
29 const char value;
30
31 int pin_first;
32 int pin_count;
33 int *pins;
34
35 int *groups;
36 int group_count;
37
38 int enabled;
39};
40
41struct rt2880_pmx_group {
42 const char *name;
43 int enabled;
44
45 const u32 shift;
46 const char mask;
47 const char gpio;
48
49 struct rt2880_pmx_func *func;
50 int func_count;
51};
52
53extern struct rt2880_pmx_group *rt2880_pinmux_data;
54
55#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 069bf37a6010..96f731bac79a 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
125#define RT305X_GPIO_GE0_TXD0 40 125#define RT305X_GPIO_GE0_TXD0 40
126#define RT305X_GPIO_GE0_RXCLK 51 126#define RT305X_GPIO_GE0_RXCLK 51
127 127
128#define RT305X_GPIO_MODE_I2C BIT(0)
129#define RT305X_GPIO_MODE_SPI BIT(1)
130#define RT305X_GPIO_MODE_UART0_SHIFT 2 128#define RT305X_GPIO_MODE_UART0_SHIFT 2
131#define RT305X_GPIO_MODE_UART0_MASK 0x7 129#define RT305X_GPIO_MODE_UART0_MASK 0x7
132#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) 130#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
133#define RT305X_GPIO_MODE_UARTF 0x0 131#define RT305X_GPIO_MODE_UARTF 0
134#define RT305X_GPIO_MODE_PCM_UARTF 0x1 132#define RT305X_GPIO_MODE_PCM_UARTF 1
135#define RT305X_GPIO_MODE_PCM_I2S 0x2 133#define RT305X_GPIO_MODE_PCM_I2S 2
136#define RT305X_GPIO_MODE_I2S_UARTF 0x3 134#define RT305X_GPIO_MODE_I2S_UARTF 3
137#define RT305X_GPIO_MODE_PCM_GPIO 0x4 135#define RT305X_GPIO_MODE_PCM_GPIO 4
138#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 136#define RT305X_GPIO_MODE_GPIO_UARTF 5
139#define RT305X_GPIO_MODE_GPIO_I2S 0x6 137#define RT305X_GPIO_MODE_GPIO_I2S 6
140#define RT305X_GPIO_MODE_GPIO 0x7 138#define RT305X_GPIO_MODE_GPIO 7
141#define RT305X_GPIO_MODE_UART1 BIT(5) 139
142#define RT305X_GPIO_MODE_JTAG BIT(6) 140#define RT305X_GPIO_MODE_I2C 0
143#define RT305X_GPIO_MODE_MDIO BIT(7) 141#define RT305X_GPIO_MODE_SPI 1
144#define RT305X_GPIO_MODE_SDRAM BIT(8) 142#define RT305X_GPIO_MODE_UART1 5
145#define RT305X_GPIO_MODE_RGMII BIT(9) 143#define RT305X_GPIO_MODE_JTAG 6
144#define RT305X_GPIO_MODE_MDIO 7
145#define RT305X_GPIO_MODE_SDRAM 8
146#define RT305X_GPIO_MODE_RGMII 9
147#define RT5350_GPIO_MODE_PHY_LED 14
148#define RT5350_GPIO_MODE_SPI_CS1 21
149#define RT3352_GPIO_MODE_LNA 18
150#define RT3352_GPIO_MODE_PA 20
146 151
147#define RT3352_SYSC_REG_SYSCFG0 0x010 152#define RT3352_SYSC_REG_SYSCFG0 0x010
148#define RT3352_SYSC_REG_SYSCFG1 0x014 153#define RT3352_SYSC_REG_SYSCFG1 0x014
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
index 058382f37f92..0fbe6f9257cd 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -112,8 +112,6 @@
112#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) 112#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
113#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) 113#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
114 114
115#define RT3883_GPIO_MODE_I2C BIT(0)
116#define RT3883_GPIO_MODE_SPI BIT(1)
117#define RT3883_GPIO_MODE_UART0_SHIFT 2 115#define RT3883_GPIO_MODE_UART0_SHIFT 2
118#define RT3883_GPIO_MODE_UART0_MASK 0x7 116#define RT3883_GPIO_MODE_UART0_MASK 0x7
119#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) 117#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
@@ -125,11 +123,15 @@
125#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 123#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
126#define RT3883_GPIO_MODE_GPIO_I2S 0x6 124#define RT3883_GPIO_MODE_GPIO_I2S 0x6
127#define RT3883_GPIO_MODE_GPIO 0x7 125#define RT3883_GPIO_MODE_GPIO 0x7
128#define RT3883_GPIO_MODE_UART1 BIT(5) 126
129#define RT3883_GPIO_MODE_JTAG BIT(6) 127#define RT3883_GPIO_MODE_I2C 0
130#define RT3883_GPIO_MODE_MDIO BIT(7) 128#define RT3883_GPIO_MODE_SPI 1
131#define RT3883_GPIO_MODE_GE1 BIT(9) 129#define RT3883_GPIO_MODE_UART1 5
132#define RT3883_GPIO_MODE_GE2 BIT(10) 130#define RT3883_GPIO_MODE_JTAG 6
131#define RT3883_GPIO_MODE_MDIO 7
132#define RT3883_GPIO_MODE_GE1 9
133#define RT3883_GPIO_MODE_GE2 10
134
133#define RT3883_GPIO_MODE_PCI_SHIFT 11 135#define RT3883_GPIO_MODE_PCI_SHIFT 11
134#define RT3883_GPIO_MODE_PCI_MASK 0x7 136#define RT3883_GPIO_MODE_PCI_MASK 0x7
135#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) 137#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 42dfd6100a2d..8e7d8e618fb9 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -11,25 +11,6 @@
11 11
12#define RAMIPS_SYS_TYPE_LEN 32 12#define RAMIPS_SYS_TYPE_LEN 32
13 13
14struct ralink_pinmux_grp {
15 const char *name;
16 u32 mask;
17 int gpio_first;
18 int gpio_last;
19};
20
21struct ralink_pinmux {
22 struct ralink_pinmux_grp *mode;
23 struct ralink_pinmux_grp *uart;
24 int uart_shift;
25 u32 uart_mask;
26 void (*wdt_reset)(void);
27 struct ralink_pinmux_grp *pci;
28 int pci_shift;
29 u32 pci_mask;
30};
31extern struct ralink_pinmux rt_gpio_pinmux;
32
33struct ralink_soc_info { 14struct ralink_soc_info {
34 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN]; 15 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
35 unsigned char *compatible; 16 unsigned char *compatible;
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 584681709db2..24fb40a441ca 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -17,6 +17,7 @@
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h> 18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/mt7620.h> 19#include <asm/mach-ralink/mt7620.h>
20#include <asm/mach-ralink/pinmux.h>
20 21
21#include "common.h" 22#include "common.h"
22 23
@@ -39,118 +40,58 @@
39/* does the board have sdram or ddram */ 40/* does the board have sdram or ddram */
40static int dram_type; 41static int dram_type;
41 42
42static struct ralink_pinmux_grp mode_mux[] = { 43static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
43 { 44static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
44 .name = "i2c", 45static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
45 .mask = MT7620_GPIO_MODE_I2C, 46static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
46 .gpio_first = 1, 47static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
47 .gpio_last = 2, 48static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
48 }, { 49static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
49 .name = "spi", 50static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
50 .mask = MT7620_GPIO_MODE_SPI, 51static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
51 .gpio_first = 3, 52static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
52 .gpio_last = 6, 53static struct rt2880_pmx_func uartf_grp[] = {
53 }, { 54 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
54 .name = "uartlite", 55 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
55 .mask = MT7620_GPIO_MODE_UART1, 56 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
56 .gpio_first = 15, 57 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
57 .gpio_last = 16, 58 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
58 }, { 59 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
59 .name = "wdt", 60 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
60 .mask = MT7620_GPIO_MODE_WDT,
61 .gpio_first = 17,
62 .gpio_last = 17,
63 }, {
64 .name = "mdio",
65 .mask = MT7620_GPIO_MODE_MDIO,
66 .gpio_first = 22,
67 .gpio_last = 23,
68 }, {
69 .name = "rgmii1",
70 .mask = MT7620_GPIO_MODE_RGMII1,
71 .gpio_first = 24,
72 .gpio_last = 35,
73 }, {
74 .name = "spi refclk",
75 .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
76 .gpio_first = 37,
77 .gpio_last = 39,
78 }, {
79 .name = "jtag",
80 .mask = MT7620_GPIO_MODE_JTAG,
81 .gpio_first = 40,
82 .gpio_last = 44,
83 }, {
84 /* shared lines with jtag */
85 .name = "ephy",
86 .mask = MT7620_GPIO_MODE_EPHY,
87 .gpio_first = 40,
88 .gpio_last = 44,
89 }, {
90 .name = "nand",
91 .mask = MT7620_GPIO_MODE_JTAG,
92 .gpio_first = 45,
93 .gpio_last = 59,
94 }, {
95 .name = "rgmii2",
96 .mask = MT7620_GPIO_MODE_RGMII2,
97 .gpio_first = 60,
98 .gpio_last = 71,
99 }, {
100 .name = "wled",
101 .mask = MT7620_GPIO_MODE_WLED,
102 .gpio_first = 72,
103 .gpio_last = 72,
104 }, {0}
105}; 61};
106 62static struct rt2880_pmx_func wdt_grp[] = {
107static struct ralink_pinmux_grp uart_mux[] = { 63 FUNC("wdt rst", 0, 17, 1),
108 { 64 FUNC("wdt refclk", 0, 17, 1),
109 .name = "uartf", 65 };
110 .mask = MT7620_GPIO_MODE_UARTF, 66static struct rt2880_pmx_func pcie_rst_grp[] = {
111 .gpio_first = 7, 67 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
112 .gpio_last = 14, 68 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
113 }, { 69};
114 .name = "pcm uartf", 70static struct rt2880_pmx_func nd_sd_grp[] = {
115 .mask = MT7620_GPIO_MODE_PCM_UARTF, 71 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
116 .gpio_first = 7, 72 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
117 .gpio_last = 14,
118 }, {
119 .name = "pcm i2s",
120 .mask = MT7620_GPIO_MODE_PCM_I2S,
121 .gpio_first = 7,
122 .gpio_last = 14,
123 }, {
124 .name = "i2s uartf",
125 .mask = MT7620_GPIO_MODE_I2S_UARTF,
126 .gpio_first = 7,
127 .gpio_last = 14,
128 }, {
129 .name = "pcm gpio",
130 .mask = MT7620_GPIO_MODE_PCM_GPIO,
131 .gpio_first = 11,
132 .gpio_last = 14,
133 }, {
134 .name = "gpio uartf",
135 .mask = MT7620_GPIO_MODE_GPIO_UARTF,
136 .gpio_first = 7,
137 .gpio_last = 10,
138 }, {
139 .name = "gpio i2s",
140 .mask = MT7620_GPIO_MODE_GPIO_I2S,
141 .gpio_first = 7,
142 .gpio_last = 10,
143 }, {
144 .name = "gpio",
145 .mask = MT7620_GPIO_MODE_GPIO,
146 }, {0}
147}; 73};
148 74
149struct ralink_pinmux rt_gpio_pinmux = { 75static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
150 .mode = mode_mux, 76 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
151 .uart = uart_mux, 77 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
152 .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT, 78 MT7620_GPIO_MODE_UART0_SHIFT),
153 .uart_mask = MT7620_GPIO_MODE_UART0_MASK, 79 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
80 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
81 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
82 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
83 GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
84 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
85 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
86 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
87 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
88 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
89 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
90 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
91 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
92 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
93 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
94 { 0 }
154}; 95};
155 96
156static __init u32 97static __init u32
diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
index 9c64f029d047..09419f67da39 100644
--- a/arch/mips/ralink/prom.c
+++ b/arch/mips/ralink/prom.c
@@ -18,6 +18,7 @@
18#include "common.h" 18#include "common.h"
19 19
20struct ralink_soc_info soc_info; 20struct ralink_soc_info soc_info;
21struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
21 22
22const char *get_system_type(void) 23const char *get_system_type(void)
23{ 24{
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
index 90e89349bd18..738cec865f41 100644
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -17,46 +17,27 @@
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h> 18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt288x.h> 19#include <asm/mach-ralink/rt288x.h>
20#include <asm/mach-ralink/pinmux.h>
20 21
21#include "common.h" 22#include "common.h"
22 23
23static struct ralink_pinmux_grp mode_mux[] = { 24static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
24 { 25static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
25 .name = "i2c", 26static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
26 .mask = RT2880_GPIO_MODE_I2C, 27static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
27 .gpio_first = 1, 28static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
28 .gpio_last = 2, 29static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
29 }, { 30static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
30 .name = "spi", 31
31 .mask = RT2880_GPIO_MODE_SPI, 32static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
32 .gpio_first = 3, 33 GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
33 .gpio_last = 6, 34 GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
34 }, { 35 GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
35 .name = "uartlite", 36 GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
36 .mask = RT2880_GPIO_MODE_UART0, 37 GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
37 .gpio_first = 7, 38 GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
38 .gpio_last = 14, 39 GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
39 }, { 40 { 0 }
40 .name = "jtag",
41 .mask = RT2880_GPIO_MODE_JTAG,
42 .gpio_first = 17,
43 .gpio_last = 21,
44 }, {
45 .name = "mdio",
46 .mask = RT2880_GPIO_MODE_MDIO,
47 .gpio_first = 22,
48 .gpio_last = 23,
49 }, {
50 .name = "sdram",
51 .mask = RT2880_GPIO_MODE_SDRAM,
52 .gpio_first = 24,
53 .gpio_last = 39,
54 }, {
55 .name = "pci",
56 .mask = RT2880_GPIO_MODE_PCI,
57 .gpio_first = 40,
58 .gpio_last = 71,
59 }, {0}
60}; 41};
61 42
62static void rt288x_wdt_reset(void) 43static void rt288x_wdt_reset(void)
@@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void)
69 rt_sysc_w32(t, SYSC_REG_CLKCFG); 50 rt_sysc_w32(t, SYSC_REG_CLKCFG);
70} 51}
71 52
72struct ralink_pinmux rt_gpio_pinmux = {
73 .mode = mode_mux,
74 .wdt_reset = rt288x_wdt_reset,
75};
76
77void __init ralink_clk_init(void) 53void __init ralink_clk_init(void)
78{ 54{
79 unsigned long cpu_rate, wmac_rate = 40000000; 55 unsigned long cpu_rate, wmac_rate = 40000000;
@@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
141 soc_info->mem_base = RT2880_SDRAM_BASE; 117 soc_info->mem_base = RT2880_SDRAM_BASE;
142 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; 118 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
143 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; 119 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
120
121 rt2880_pinmux_data = rt2880_pinmux_data_act;
144} 122}
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index bb82a82da9e7..c40776ab67db 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -17,90 +17,78 @@
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h> 18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt305x.h> 19#include <asm/mach-ralink/rt305x.h>
20#include <asm/mach-ralink/pinmux.h>
20 21
21#include "common.h" 22#include "common.h"
22 23
23enum rt305x_soc_type rt305x_soc; 24enum rt305x_soc_type rt305x_soc;
24 25
25static struct ralink_pinmux_grp mode_mux[] = { 26static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
26 { 27static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
27 .name = "i2c", 28static struct rt2880_pmx_func uartf_func[] = {
28 .mask = RT305X_GPIO_MODE_I2C, 29 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
29 .gpio_first = RT305X_GPIO_I2C_SD, 30 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
30 .gpio_last = RT305X_GPIO_I2C_SCLK, 31 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
31 }, { 32 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
32 .name = "spi", 33 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
33 .mask = RT305X_GPIO_MODE_SPI, 34 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
34 .gpio_first = RT305X_GPIO_SPI_EN, 35 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
35 .gpio_last = RT305X_GPIO_SPI_CLK, 36};
36 }, { 37static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
37 .name = "uartlite", 38static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
38 .mask = RT305X_GPIO_MODE_UART1, 39static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
39 .gpio_first = RT305X_GPIO_UART1_TXD, 40static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
40 .gpio_last = RT305X_GPIO_UART1_RXD, 41static struct rt2880_pmx_func rt5350_cs1_func[] = {
41 }, { 42 FUNC("spi_cs1", 0, 27, 1),
42 .name = "jtag", 43 FUNC("wdg_cs1", 1, 27, 1),
43 .mask = RT305X_GPIO_MODE_JTAG, 44};
44 .gpio_first = RT305X_GPIO_JTAG_TDO, 45static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
45 .gpio_last = RT305X_GPIO_JTAG_TDI, 46static struct rt2880_pmx_func rt3352_rgmii_func[] = {
46 }, { 47 FUNC("rgmii", 0, 24, 12)
47 .name = "mdio", 48};
48 .mask = RT305X_GPIO_MODE_MDIO, 49static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
49 .gpio_first = RT305X_GPIO_MDIO_MDC, 50static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
50 .gpio_last = RT305X_GPIO_MDIO_MDIO, 51static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
51 }, { 52static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
52 .name = "sdram", 53
53 .mask = RT305X_GPIO_MODE_SDRAM, 54static struct rt2880_pmx_group rt3050_pinmux_data[] = {
54 .gpio_first = RT305X_GPIO_SDRAM_MD16, 55 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
55 .gpio_last = RT305X_GPIO_SDRAM_MD31, 56 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
56 }, { 57 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
57 .name = "rgmii", 58 RT305X_GPIO_MODE_UART0_SHIFT),
58 .mask = RT305X_GPIO_MODE_RGMII, 59 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
59 .gpio_first = RT305X_GPIO_GE0_TXD0, 60 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
60 .gpio_last = RT305X_GPIO_GE0_RXCLK, 61 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
61 }, {0} 62 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
63 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
64 { 0 }
62}; 65};
63 66
64static struct ralink_pinmux_grp uart_mux[] = { 67static struct rt2880_pmx_group rt3352_pinmux_data[] = {
65 { 68 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
66 .name = "uartf", 69 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
67 .mask = RT305X_GPIO_MODE_UARTF, 70 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
68 .gpio_first = RT305X_GPIO_7, 71 RT305X_GPIO_MODE_UART0_SHIFT),
69 .gpio_last = RT305X_GPIO_14, 72 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
70 }, { 73 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
71 .name = "pcm uartf", 74 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
72 .mask = RT305X_GPIO_MODE_PCM_UARTF, 75 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
73 .gpio_first = RT305X_GPIO_7, 76 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
74 .gpio_last = RT305X_GPIO_14, 77 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
75 }, { 78 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
76 .name = "pcm i2s", 79 { 0 }
77 .mask = RT305X_GPIO_MODE_PCM_I2S, 80};
78 .gpio_first = RT305X_GPIO_7, 81
79 .gpio_last = RT305X_GPIO_14, 82static struct rt2880_pmx_group rt5350_pinmux_data[] = {
80 }, { 83 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
81 .name = "i2s uartf", 84 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
82 .mask = RT305X_GPIO_MODE_I2S_UARTF, 85 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
83 .gpio_first = RT305X_GPIO_7, 86 RT305X_GPIO_MODE_UART0_SHIFT),
84 .gpio_last = RT305X_GPIO_14, 87 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
85 }, { 88 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
86 .name = "pcm gpio", 89 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
87 .mask = RT305X_GPIO_MODE_PCM_GPIO, 90 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
88 .gpio_first = RT305X_GPIO_10, 91 { 0 }
89 .gpio_last = RT305X_GPIO_14,
90 }, {
91 .name = "gpio uartf",
92 .mask = RT305X_GPIO_MODE_GPIO_UARTF,
93 .gpio_first = RT305X_GPIO_7,
94 .gpio_last = RT305X_GPIO_10,
95 }, {
96 .name = "gpio i2s",
97 .mask = RT305X_GPIO_MODE_GPIO_I2S,
98 .gpio_first = RT305X_GPIO_7,
99 .gpio_last = RT305X_GPIO_10,
100 }, {
101 .name = "gpio",
102 .mask = RT305X_GPIO_MODE_GPIO,
103 }, {0}
104}; 92};
105 93
106static void rt305x_wdt_reset(void) 94static void rt305x_wdt_reset(void)
@@ -114,14 +102,6 @@ static void rt305x_wdt_reset(void)
114 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); 102 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
115} 103}
116 104
117struct ralink_pinmux rt_gpio_pinmux = {
118 .mode = mode_mux,
119 .uart = uart_mux,
120 .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
121 .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
122 .wdt_reset = rt305x_wdt_reset,
123};
124
125static unsigned long rt5350_get_mem_size(void) 105static unsigned long rt5350_get_mem_size(void)
126{ 106{
127 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 107 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
@@ -290,11 +270,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
290 soc_info->mem_base = RT305X_SDRAM_BASE; 270 soc_info->mem_base = RT305X_SDRAM_BASE;
291 if (soc_is_rt5350()) { 271 if (soc_is_rt5350()) {
292 soc_info->mem_size = rt5350_get_mem_size(); 272 soc_info->mem_size = rt5350_get_mem_size();
273 rt2880_pinmux_data = rt5350_pinmux_data;
293 } else if (soc_is_rt305x() || soc_is_rt3350()) { 274 } else if (soc_is_rt305x() || soc_is_rt3350()) {
294 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; 275 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
295 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; 276 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
277 rt2880_pinmux_data = rt3050_pinmux_data;
296 } else if (soc_is_rt3352()) { 278 } else if (soc_is_rt3352()) {
297 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; 279 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
298 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; 280 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
281 rt2880_pinmux_data = rt3352_pinmux_data;
299 } 282 }
300} 283}
diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
index 58b5b9f464a1..86a535c770d8 100644
--- a/arch/mips/ralink/rt3883.c
+++ b/arch/mips/ralink/rt3883.c
@@ -17,132 +17,50 @@
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h> 18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt3883.h> 19#include <asm/mach-ralink/rt3883.h>
20#include <asm/mach-ralink/pinmux.h>
20 21
21#include "common.h" 22#include "common.h"
22 23
23static struct ralink_pinmux_grp mode_mux[] = { 24static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
24 { 25static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
25 .name = "i2c", 26static struct rt2880_pmx_func uartf_func[] = {
26 .mask = RT3883_GPIO_MODE_I2C, 27 FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
27 .gpio_first = RT3883_GPIO_I2C_SD, 28 FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
28 .gpio_last = RT3883_GPIO_I2C_SCLK, 29 FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
29 }, { 30 FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
30 .name = "spi", 31 FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
31 .mask = RT3883_GPIO_MODE_SPI, 32 FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
32 .gpio_first = RT3883_GPIO_SPI_CS0, 33 FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
33 .gpio_last = RT3883_GPIO_SPI_MISO,
34 }, {
35 .name = "uartlite",
36 .mask = RT3883_GPIO_MODE_UART1,
37 .gpio_first = RT3883_GPIO_UART1_TXD,
38 .gpio_last = RT3883_GPIO_UART1_RXD,
39 }, {
40 .name = "jtag",
41 .mask = RT3883_GPIO_MODE_JTAG,
42 .gpio_first = RT3883_GPIO_JTAG_TDO,
43 .gpio_last = RT3883_GPIO_JTAG_TCLK,
44 }, {
45 .name = "mdio",
46 .mask = RT3883_GPIO_MODE_MDIO,
47 .gpio_first = RT3883_GPIO_MDIO_MDC,
48 .gpio_last = RT3883_GPIO_MDIO_MDIO,
49 }, {
50 .name = "ge1",
51 .mask = RT3883_GPIO_MODE_GE1,
52 .gpio_first = RT3883_GPIO_GE1_TXD0,
53 .gpio_last = RT3883_GPIO_GE1_RXCLK,
54 }, {
55 .name = "ge2",
56 .mask = RT3883_GPIO_MODE_GE2,
57 .gpio_first = RT3883_GPIO_GE2_TXD0,
58 .gpio_last = RT3883_GPIO_GE2_RXCLK,
59 }, {
60 .name = "pci",
61 .mask = RT3883_GPIO_MODE_PCI,
62 .gpio_first = RT3883_GPIO_PCI_AD0,
63 .gpio_last = RT3883_GPIO_PCI_AD31,
64 }, {
65 .name = "lna a",
66 .mask = RT3883_GPIO_MODE_LNA_A,
67 .gpio_first = RT3883_GPIO_LNA_PE_A0,
68 .gpio_last = RT3883_GPIO_LNA_PE_A2,
69 }, {
70 .name = "lna g",
71 .mask = RT3883_GPIO_MODE_LNA_G,
72 .gpio_first = RT3883_GPIO_LNA_PE_G0,
73 .gpio_last = RT3883_GPIO_LNA_PE_G2,
74 }, {0}
75}; 34};
76 35static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
77static struct ralink_pinmux_grp uart_mux[] = { 36static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
78 { 37static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
79 .name = "uartf", 38static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
80 .mask = RT3883_GPIO_MODE_UARTF, 39static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
81 .gpio_first = RT3883_GPIO_7, 40static struct rt2880_pmx_func pci_func[] = {
82 .gpio_last = RT3883_GPIO_14, 41 FUNC("pci-dev", 0, 40, 32),
83 }, { 42 FUNC("pci-host2", 1, 40, 32),
84 .name = "pcm uartf", 43 FUNC("pci-host1", 2, 40, 32),
85 .mask = RT3883_GPIO_MODE_PCM_UARTF, 44 FUNC("pci-fnc", 3, 40, 32)
86 .gpio_first = RT3883_GPIO_7,
87 .gpio_last = RT3883_GPIO_14,
88 }, {
89 .name = "pcm i2s",
90 .mask = RT3883_GPIO_MODE_PCM_I2S,
91 .gpio_first = RT3883_GPIO_7,
92 .gpio_last = RT3883_GPIO_14,
93 }, {
94 .name = "i2s uartf",
95 .mask = RT3883_GPIO_MODE_I2S_UARTF,
96 .gpio_first = RT3883_GPIO_7,
97 .gpio_last = RT3883_GPIO_14,
98 }, {
99 .name = "pcm gpio",
100 .mask = RT3883_GPIO_MODE_PCM_GPIO,
101 .gpio_first = RT3883_GPIO_11,
102 .gpio_last = RT3883_GPIO_14,
103 }, {
104 .name = "gpio uartf",
105 .mask = RT3883_GPIO_MODE_GPIO_UARTF,
106 .gpio_first = RT3883_GPIO_7,
107 .gpio_last = RT3883_GPIO_10,
108 }, {
109 .name = "gpio i2s",
110 .mask = RT3883_GPIO_MODE_GPIO_I2S,
111 .gpio_first = RT3883_GPIO_7,
112 .gpio_last = RT3883_GPIO_10,
113 }, {
114 .name = "gpio",
115 .mask = RT3883_GPIO_MODE_GPIO,
116 }, {0}
117}; 45};
118 46static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
119static struct ralink_pinmux_grp pci_mux[] = { 47static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
120 { 48
121 .name = "pci-dev", 49static struct rt2880_pmx_group rt3883_pinmux_data[] = {
122 .mask = 0, 50 GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
123 .gpio_first = RT3883_GPIO_PCI_AD0, 51 GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
124 .gpio_last = RT3883_GPIO_PCI_AD31, 52 GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
125 }, { 53 RT3883_GPIO_MODE_UART0_SHIFT),
126 .name = "pci-host2", 54 GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
127 .mask = 1, 55 GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
128 .gpio_first = RT3883_GPIO_PCI_AD0, 56 GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
129 .gpio_last = RT3883_GPIO_PCI_AD31, 57 GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
130 }, { 58 GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
131 .name = "pci-host1", 59 GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
132 .mask = 2, 60 RT3883_GPIO_MODE_PCI_SHIFT),
133 .gpio_first = RT3883_GPIO_PCI_AD0, 61 GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
134 .gpio_last = RT3883_GPIO_PCI_AD31, 62 GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
135 }, { 63 { 0 }
136 .name = "pci-fnc",
137 .mask = 3,
138 .gpio_first = RT3883_GPIO_PCI_AD0,
139 .gpio_last = RT3883_GPIO_PCI_AD31,
140 }, {
141 .name = "pci-gpio",
142 .mask = 7,
143 .gpio_first = RT3883_GPIO_PCI_AD0,
144 .gpio_last = RT3883_GPIO_PCI_AD31,
145 }, {0}
146}; 64};
147 65
148static void rt3883_wdt_reset(void) 66static void rt3883_wdt_reset(void)
@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
155 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1); 73 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
156} 74}
157 75
158struct ralink_pinmux rt_gpio_pinmux = {
159 .mode = mode_mux,
160 .uart = uart_mux,
161 .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
162 .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
163 .wdt_reset = rt3883_wdt_reset,
164 .pci = pci_mux,
165 .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
166 .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
167};
168
169void __init ralink_clk_init(void) 76void __init ralink_clk_init(void)
170{ 77{
171 unsigned long cpu_rate, sys_rate; 78 unsigned long cpu_rate, sys_rate;
@@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
244 soc_info->mem_base = RT3883_SDRAM_BASE; 151 soc_info->mem_base = RT3883_SDRAM_BASE;
245 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; 152 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
246 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; 153 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
154
155 rt2880_pinmux_data = rt3883_pinmux_data;
247} 156}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 14:36:21 -0400