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authorArnd Bergmann <arnd@arndb.de>2013-04-19 16:50:41 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-19 16:50:52 -0400
commitf54ae513d3d39b60bcc2ef446f1219f501d859bf (patch)
treea60c22feaee5265fa9b017bc504793ae1b531972
parent1b361942b53c33f38d55065c13785aadb5103a18 (diff)
parente34d3865ee4a71195f91b23fd09e2619a5f727d3 (diff)
Merge branch 'spear/dwdma' into late/cleanup
This is a series originally prepared for inclusion in 3.9, which did not work out because of dependencies on the dmaengine driver. All the changes for the dmaengine code are merged in 3.9 now, so we can finally do the switchover and remove the now unnecessary dma definitions for spear13xx from the platform code. The dma platform_data actually made up the majority of the spear13xx platform code overall, so moving that into device tree files makes the code substantially smaller. * spear/dwdma: ata: arasan: remove the need for platform_data ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT serial: pl011: use generic DMA slave configuration if possible spi: pl022: use generic DMA slave configuration if possible Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/primecell.txt19
-rw-r--r--Documentation/devicetree/bindings/ata/pata-arasan.txt22
-rw-r--r--Documentation/devicetree/bindings/serial/pl011.txt17
-rw-r--r--Documentation/devicetree/bindings/spi/spi_pl022.txt36
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi3
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi25
-rw-r--r--arch/arm/mach-spear/generic.h5
-rw-r--r--arch/arm/mach-spear/include/mach/spear.h2
-rw-r--r--arch/arm/mach-spear/spear1310.c30
-rw-r--r--arch/arm/mach-spear/spear1340.c32
-rw-r--r--arch/arm/mach-spear/spear13xx-dma.h128
-rw-r--r--arch/arm/mach-spear/spear13xx.c58
-rw-r--r--drivers/ata/pata_arasan_cf.c37
-rw-r--r--drivers/spi/spi-pl022.c43
-rw-r--r--drivers/tty/serial/amba-pl011.c62
-rw-r--r--include/linux/pata_arasan_cf_data.h2
16 files changed, 219 insertions, 302 deletions
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 64fc82bc8928..0df6acacfaea 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -16,14 +16,31 @@ Optional properties:
16- clocks : From common clock binding. First clock is phandle to clock for apb 16- clocks : From common clock binding. First clock is phandle to clock for apb
17 pclk. Additional clocks are optional and specific to those peripherals. 17 pclk. Additional clocks are optional and specific to those peripherals.
18- clock-names : From common clock binding. Shall be "apb_pclk" for first clock. 18- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
19- dmas : From common DMA binding. If present, refers to one or more dma channels.
20- dma-names : From common DMA binding, needs to match the 'dmas' property.
21 Devices with exactly one receive and transmit channel shall name
22 these "rx" and "tx", respectively.
23- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
24- pinctrl-names : Names corresponding to the numbered pinctrl states
25- interrupts : one or more interrupt specifiers
26- interrupt-names : names corresponding to the interrupts properties
19 27
20Example: 28Example:
21 29
22serial@fff36000 { 30serial@fff36000 {
23 compatible = "arm,pl011", "arm,primecell"; 31 compatible = "arm,pl011", "arm,primecell";
24 arm,primecell-periphid = <0x00341011>; 32 arm,primecell-periphid = <0x00341011>;
33
25 clocks = <&pclk>; 34 clocks = <&pclk>;
26 clock-names = "apb_pclk"; 35 clock-names = "apb_pclk";
27 36
37 dmas = <&dma-controller 4>, <&dma-controller 5>;
38 dma-names = "rx", "tx";
39
40 pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
41 pinctrl-1 = <&uart0_sleep_mode>;
42 pinctrl-names = "default","sleep";
43
44 interrupts = <0 11 0x4>;
28}; 45};
29 46
diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt
index 95ec7f825ede..2aff154be84e 100644
--- a/Documentation/devicetree/bindings/ata/pata-arasan.txt
+++ b/Documentation/devicetree/bindings/ata/pata-arasan.txt
@@ -6,6 +6,26 @@ Required properties:
6- interrupt-parent: Should be the phandle for the interrupt controller 6- interrupt-parent: Should be the phandle for the interrupt controller
7 that services interrupts for this device 7 that services interrupts for this device
8- interrupt: Should contain the CF interrupt number 8- interrupt: Should contain the CF interrupt number
9- clock-frequency: Interface clock rate, in Hz, one of
10 25000000
11 33000000
12 40000000
13 50000000
14 66000000
15 75000000
16 100000000
17 125000000
18 150000000
19 166000000
20 200000000
21
22Optional properties:
23- arasan,broken-udma: if present, UDMA mode is unusable
24- arasan,broken-mwdma: if present, MWDMA mode is unusable
25- arasan,broken-pio: if present, PIO mode is unusable
26- dmas: one DMA channel, as described in bindings/dma/dma.txt
27 required unless both UDMA and MWDMA mode are broken
28- dma-names: the corresponding channel name, must be "data"
9 29
10Example: 30Example:
11 31
@@ -14,4 +34,6 @@ Example:
14 reg = <0xfc000000 0x1000>; 34 reg = <0xfc000000 0x1000>;
15 interrupt-parent = <&vic1>; 35 interrupt-parent = <&vic1>;
16 interrupts = <12>; 36 interrupts = <12>;
37 dmas = <&dma-controller 23>;
38 dma-names = "data";
17 }; 39 };
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt
new file mode 100644
index 000000000000..5d2e840ae65c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/pl011.txt
@@ -0,0 +1,17 @@
1* ARM AMBA Primecell PL011 serial UART
2
3Required properties:
4- compatible: must be "arm,primecell", "arm,pl011"
5- reg: exactly one register range with length 0x1000
6- interrupts: exactly one interrupt specifier
7
8Optional properties:
9- pinctrl: When present, must have one state named "sleep"
10 and one state named "default"
11- clocks: When present, must refer to exactly one clock named
12 "apb_pclk"
13- dmas: When present, may have one or two dma channels.
14 The first one must be named "rx", the second one
15 must be named "tx".
16
17See also bindings/arm/primecell.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
index f158fd31cfda..22ed6797216d 100644
--- a/Documentation/devicetree/bindings/spi/spi_pl022.txt
+++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt
@@ -16,6 +16,11 @@ Optional properties:
16 device will be suspended immediately 16 device will be suspended immediately
17- pl022,rt : indicates the controller should run the message pump with realtime 17- pl022,rt : indicates the controller should run the message pump with realtime
18 priority to minimise the transfer latency on the bus (boolean) 18 priority to minimise the transfer latency on the bus (boolean)
19- dmas : Two or more DMA channel specifiers following the convention outlined
20 in bindings/dma/dma.txt
21- dma-names: Names for the dma channels, if present. There must be at
22 least one channel named "tx" for transmit and named "rx" for
23 receive.
19 24
20 25
21SPI slave nodes must be children of the SPI master node and can 26SPI slave nodes must be children of the SPI master node and can
@@ -32,3 +37,34 @@ contain the following properties.
32- pl022,wait-state : Microwire interface: Wait state 37- pl022,wait-state : Microwire interface: Wait state
33- pl022,duplex : Microwire interface: Full/Half duplex 38- pl022,duplex : Microwire interface: Full/Half duplex
34 39
40
41Example:
42
43 spi@e0100000 {
44 compatible = "arm,pl022", "arm,primecell";
45 reg = <0xe0100000 0x1000>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48 interrupts = <0 31 0x4>;
49 dmas = <&dma-controller 23 1>,
50 <&dma-controller 24 0>;
51 dma-names = "rx", "tx";
52
53 m25p80@1 {
54 compatible = "st,m25p80";
55 reg = <1>;
56 spi-max-frequency = <12000000>;
57 spi-cpol;
58 spi-cpha;
59 pl022,hierarchy = <0>;
60 pl022,interface = <0>;
61 pl022,slave-tx-disable;
62 pl022,com-mode = <0x2>;
63 pl022,rx-level-trig = <0>;
64 pl022,tx-level-trig = <0>;
65 pl022,ctrl-len = <0x11>;
66 pl022,wait-state = <0>;
67 pl022,duplex = <0>;
68 };
69 };
70
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..e1786a0b2fcd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -113,6 +113,9 @@
113 reg = <0xb4100000 0x1000>; 113 reg = <0xb4100000 0x1000>;
114 interrupts = <0 105 0x4>; 114 interrupts = <0 105 0x4>;
115 status = "disabled"; 115 status = "disabled";
116 dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */
117 <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */
118 dma-names = "tx", "rx";
116 }; 119 };
117 120
118 thermal@e07008c4 { 121 thermal@e07008c4 {
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index b4ca60f4eb42..45597fd91050 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -98,13 +98,24 @@
98 reg = <0xb2800000 0x1000>; 98 reg = <0xb2800000 0x1000>;
99 interrupts = <0 29 0x4>; 99 interrupts = <0 29 0x4>;
100 status = "disabled"; 100 status = "disabled";
101 dmas = <&dwdma0 0 0 0 0>;
102 dma-names = "data";
101 }; 103 };
102 104
103 dma@ea800000 { 105 dwdma0: dma@ea800000 {
104 compatible = "snps,dma-spear1340"; 106 compatible = "snps,dma-spear1340";
105 reg = <0xea800000 0x1000>; 107 reg = <0xea800000 0x1000>;
106 interrupts = <0 19 0x4>; 108 interrupts = <0 19 0x4>;
107 status = "disabled"; 109 status = "disabled";
110
111 dma-channels = <8>;
112 #dma-cells = <3>;
113 dma-requests = <32>;
114 chan_allocation_order = <1>;
115 chan_priority = <1>;
116 block_size = <0xfff>;
117 dma-masters = <2>;
118 data_width = <3 3 0 0>;
108 }; 119 };
109 120
110 dma@eb000000 { 121 dma@eb000000 {
@@ -112,6 +123,15 @@
112 reg = <0xeb000000 0x1000>; 123 reg = <0xeb000000 0x1000>;
113 interrupts = <0 59 0x4>; 124 interrupts = <0 59 0x4>;
114 status = "disabled"; 125 status = "disabled";
126
127 dma-requests = <32>;
128 dma-channels = <8>;
129 dma-masters = <2>;
130 #dma-cells = <3>;
131 chan_allocation_order = <1>;
132 chan_priority = <1>;
133 block_size = <0xfff>;
134 data_width = <3 3 0 0>;
115 }; 135 };
116 136
117 fsmc: flash@b0000000 { 137 fsmc: flash@b0000000 {
@@ -261,6 +281,9 @@
261 #size-cells = <0>; 281 #size-cells = <0>;
262 interrupts = <0 31 0x4>; 282 interrupts = <0 31 0x4>;
263 status = "disabled"; 283 status = "disabled";
284 dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
285 <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */
286 dma-names = "tx", "rx";
264 }; 287 };
265 288
266 rtc@e0580000 { 289 rtc@e0580000 {
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index 8ba7e75b648d..a9fd45362fee 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -22,11 +22,6 @@ extern void spear13xx_timer_init(void);
22extern void spear3xx_timer_init(void); 22extern void spear3xx_timer_init(void);
23extern struct pl022_ssp_controller pl022_plat_data; 23extern struct pl022_ssp_controller pl022_plat_data;
24extern struct pl08x_platform_data pl080_plat_data; 24extern struct pl08x_platform_data pl080_plat_data;
25extern struct dw_dma_platform_data dmac_plat_data;
26extern struct dw_dma_slave cf_dma_priv;
27extern struct dw_dma_slave nand_read_dma_priv;
28extern struct dw_dma_slave nand_write_dma_priv;
29bool dw_dma_filter(struct dma_chan *chan, void *slave);
30 25
31void __init spear_setup_of_timer(void); 26void __init spear_setup_of_timer(void);
32void __init spear3xx_clk_init(void __iomem *misc_base, 27void __init spear3xx_clk_init(void __iomem *misc_base,
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 374ddc393df1..cf3a5369eeca 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -82,8 +82,6 @@
82#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) 82#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
83 83
84/* others */ 84/* others */
85#define DMAC0_BASE UL(0xEA800000)
86#define DMAC1_BASE UL(0xEB000000)
87#define MCIF_CF_BASE UL(0xB2800000) 85#define MCIF_CF_BASE UL(0xB2800000)
88 86
89/* Debug uart for linux, will be used for debug and uncompress messages */ 87/* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index ed3b5c287a7b..9eaac2c881ea 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -23,40 +23,12 @@
23#include <mach/spear.h> 23#include <mach/spear.h>
24 24
25/* Base addresses */ 25/* Base addresses */
26#define SPEAR1310_SSP1_BASE UL(0x5D400000)
27#define SPEAR1310_SATA0_BASE UL(0xB1000000)
28#define SPEAR1310_SATA1_BASE UL(0xB1800000)
29#define SPEAR1310_SATA2_BASE UL(0xB4000000)
30
31#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) 26#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
32#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) 27#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
33 28
34static struct arasan_cf_pdata cf_pdata = {
35 .cf_if_clk = CF_IF_CLK_166M,
36 .quirk = CF_BROKEN_UDMA,
37 .dma_priv = &cf_dma_priv,
38};
39
40/* ssp device registration */
41static struct pl022_ssp_controller ssp1_plat_data = {
42 .enable_dma = 0,
43};
44
45/* Add SPEAr1310 auxdata to pass platform data */
46static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
47 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
48 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
49 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
50 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
51
52 OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
53 {}
54};
55
56static void __init spear1310_dt_init(void) 29static void __init spear1310_dt_init(void)
57{ 30{
58 of_platform_populate(NULL, of_default_bus_match_table, 31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
59 spear1310_auxdata_lookup, NULL);
60} 32}
61 33
62static const char * const spear1310_dt_board_compat[] = { 34static const char * const spear1310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 75e38644bbfb..a04a7fe76f71 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -16,18 +16,16 @@
16#include <linux/ahci_platform.h> 16#include <linux/ahci_platform.h>
17#include <linux/amba/serial.h> 17#include <linux/amba/serial.h>
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/dw_dmac.h>
20#include <linux/of_platform.h> 19#include <linux/of_platform.h>
21#include <linux/irqchip.h> 20#include <linux/irqchip.h>
22#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
23#include "generic.h" 22#include "generic.h"
24#include <mach/spear.h> 23#include <mach/spear.h>
25 24
26#include "spear13xx-dma.h" 25/* FIXME: Move SATA PHY code into a standalone driver */
27 26
28/* Base addresses */ 27/* Base addresses */
29#define SPEAR1340_SATA_BASE UL(0xB1000000) 28#define SPEAR1340_SATA_BASE UL(0xB1000000)
30#define SPEAR1340_UART1_BASE UL(0xB4100000)
31 29
32/* Power Management Registers */ 30/* Power Management Registers */
33#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) 31#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
@@ -79,28 +77,6 @@
79 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ 77 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
80 SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) 78 SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
81 79
82static struct dw_dma_slave uart1_dma_param[] = {
83 {
84 /* Tx */
85 .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
86 .cfg_lo = 0,
87 .src_master = DMA_MASTER_MEMORY,
88 .dst_master = SPEAR1340_DMA_MASTER_UART1,
89 }, {
90 /* Rx */
91 .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
92 .cfg_lo = 0,
93 .src_master = SPEAR1340_DMA_MASTER_UART1,
94 .dst_master = DMA_MASTER_MEMORY,
95 }
96};
97
98static struct amba_pl011_data uart1_data = {
99 .dma_filter = dw_dma_filter,
100 .dma_tx_param = &uart1_dma_param[0],
101 .dma_rx_param = &uart1_dma_param[1],
102};
103
104/* SATA device registration */ 80/* SATA device registration */
105static int sata_miphy_init(struct device *dev, void __iomem *addr) 81static int sata_miphy_init(struct device *dev, void __iomem *addr)
106{ 82{
@@ -159,14 +135,8 @@ static struct ahci_platform_data sata_pdata = {
159 135
160/* Add SPEAr1340 auxdata to pass platform data */ 136/* Add SPEAr1340 auxdata to pass platform data */
161static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { 137static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
162 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
163 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
164 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
165 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
166
167 OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, 138 OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
168 &sata_pdata), 139 &sata_pdata),
169 OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
170 {} 140 {}
171}; 141};
172 142
diff --git a/arch/arm/mach-spear/spear13xx-dma.h b/arch/arm/mach-spear/spear13xx-dma.h
deleted file mode 100644
index d50bdb605925..000000000000
--- a/arch/arm/mach-spear/spear13xx-dma.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/dma.h
3 *
4 * DMA information for SPEAr13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_DMA_H
15#define __MACH_DMA_H
16
17/* request id of all the peripherals */
18enum dma_master_info {
19 /* Accessible from only one master */
20 DMA_MASTER_MCIF = 0,
21 DMA_MASTER_FSMC = 1,
22 /* Accessible from both 0 & 1 */
23 DMA_MASTER_MEMORY = 0,
24 DMA_MASTER_ADC = 0,
25 DMA_MASTER_UART0 = 0,
26 DMA_MASTER_SSP0 = 0,
27 DMA_MASTER_I2C0 = 0,
28
29#ifdef CONFIG_MACH_SPEAR1310
30 /* Accessible from only one master */
31 SPEAR1310_DMA_MASTER_JPEG = 1,
32
33 /* Accessible from both 0 & 1 */
34 SPEAR1310_DMA_MASTER_I2S = 0,
35 SPEAR1310_DMA_MASTER_UART1 = 0,
36 SPEAR1310_DMA_MASTER_UART2 = 0,
37 SPEAR1310_DMA_MASTER_UART3 = 0,
38 SPEAR1310_DMA_MASTER_UART4 = 0,
39 SPEAR1310_DMA_MASTER_UART5 = 0,
40 SPEAR1310_DMA_MASTER_I2C1 = 0,
41 SPEAR1310_DMA_MASTER_I2C2 = 0,
42 SPEAR1310_DMA_MASTER_I2C3 = 0,
43 SPEAR1310_DMA_MASTER_I2C4 = 0,
44 SPEAR1310_DMA_MASTER_I2C5 = 0,
45 SPEAR1310_DMA_MASTER_I2C6 = 0,
46 SPEAR1310_DMA_MASTER_I2C7 = 0,
47 SPEAR1310_DMA_MASTER_SSP1 = 0,
48#endif
49
50#ifdef CONFIG_MACH_SPEAR1340
51 /* Accessible from only one master */
52 SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
53 SPEAR1340_DMA_MASTER_I2S_REC = 1,
54 SPEAR1340_DMA_MASTER_I2C1 = 1,
55 SPEAR1340_DMA_MASTER_UART1 = 1,
56
57 /* following are accessible from both master 0 & 1 */
58 SPEAR1340_DMA_MASTER_SPDIF = 0,
59 SPEAR1340_DMA_MASTER_CAM = 1,
60 SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
61 SPEAR1340_DMA_MASTER_MALI = 0,
62#endif
63};
64
65enum request_id {
66 DMA_REQ_ADC = 0,
67 DMA_REQ_SSP0_TX = 4,
68 DMA_REQ_SSP0_RX = 5,
69 DMA_REQ_UART0_TX = 6,
70 DMA_REQ_UART0_RX = 7,
71 DMA_REQ_I2C0_TX = 8,
72 DMA_REQ_I2C0_RX = 9,
73
74#ifdef CONFIG_MACH_SPEAR1310
75 SPEAR1310_DMA_REQ_FROM_JPEG = 2,
76 SPEAR1310_DMA_REQ_TO_JPEG = 3,
77 SPEAR1310_DMA_REQ_I2S_TX = 10,
78 SPEAR1310_DMA_REQ_I2S_RX = 11,
79
80 SPEAR1310_DMA_REQ_I2C1_RX = 0,
81 SPEAR1310_DMA_REQ_I2C1_TX = 1,
82 SPEAR1310_DMA_REQ_I2C2_RX = 2,
83 SPEAR1310_DMA_REQ_I2C2_TX = 3,
84 SPEAR1310_DMA_REQ_I2C3_RX = 4,
85 SPEAR1310_DMA_REQ_I2C3_TX = 5,
86 SPEAR1310_DMA_REQ_I2C4_RX = 6,
87 SPEAR1310_DMA_REQ_I2C4_TX = 7,
88 SPEAR1310_DMA_REQ_I2C5_RX = 8,
89 SPEAR1310_DMA_REQ_I2C5_TX = 9,
90 SPEAR1310_DMA_REQ_I2C6_RX = 10,
91 SPEAR1310_DMA_REQ_I2C6_TX = 11,
92 SPEAR1310_DMA_REQ_UART1_RX = 12,
93 SPEAR1310_DMA_REQ_UART1_TX = 13,
94 SPEAR1310_DMA_REQ_UART2_RX = 14,
95 SPEAR1310_DMA_REQ_UART2_TX = 15,
96 SPEAR1310_DMA_REQ_UART5_RX = 16,
97 SPEAR1310_DMA_REQ_UART5_TX = 17,
98 SPEAR1310_DMA_REQ_SSP1_RX = 18,
99 SPEAR1310_DMA_REQ_SSP1_TX = 19,
100 SPEAR1310_DMA_REQ_I2C7_RX = 20,
101 SPEAR1310_DMA_REQ_I2C7_TX = 21,
102 SPEAR1310_DMA_REQ_UART3_RX = 28,
103 SPEAR1310_DMA_REQ_UART3_TX = 29,
104 SPEAR1310_DMA_REQ_UART4_RX = 30,
105 SPEAR1310_DMA_REQ_UART4_TX = 31,
106#endif
107
108#ifdef CONFIG_MACH_SPEAR1340
109 SPEAR1340_DMA_REQ_SPDIF_TX = 2,
110 SPEAR1340_DMA_REQ_SPDIF_RX = 3,
111 SPEAR1340_DMA_REQ_I2S_TX = 10,
112 SPEAR1340_DMA_REQ_I2S_RX = 11,
113 SPEAR1340_DMA_REQ_UART1_TX = 12,
114 SPEAR1340_DMA_REQ_UART1_RX = 13,
115 SPEAR1340_DMA_REQ_I2C1_TX = 14,
116 SPEAR1340_DMA_REQ_I2C1_RX = 15,
117 SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
118 SPEAR1340_DMA_REQ_CAM0_ODD = 1,
119 SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
120 SPEAR1340_DMA_REQ_CAM1_ODD = 3,
121 SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
122 SPEAR1340_DMA_REQ_CAM2_ODD = 5,
123 SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
124 SPEAR1340_DMA_REQ_CAM3_ODD = 7,
125#endif
126};
127
128#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 1b97e8623472..3975916666a0 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -15,7 +15,6 @@
15 15
16#include <linux/amba/pl022.h> 16#include <linux/amba/pl022.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/dw_dmac.h>
19#include <linux/err.h> 18#include <linux/err.h>
20#include <linux/of.h> 19#include <linux/of.h>
21#include <asm/hardware/cache-l2x0.h> 20#include <asm/hardware/cache-l2x0.h>
@@ -24,63 +23,6 @@
24#include "generic.h" 23#include "generic.h"
25#include <mach/spear.h> 24#include <mach/spear.h>
26 25
27#include "spear13xx-dma.h"
28
29/* common dw_dma filter routine to be used by peripherals */
30bool dw_dma_filter(struct dma_chan *chan, void *slave)
31{
32 struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
33
34 if (chan->device->dev == dws->dma_dev) {
35 chan->private = slave;
36 return true;
37 } else {
38 return false;
39 }
40}
41
42/* ssp device registration */
43static struct dw_dma_slave ssp_dma_param[] = {
44 {
45 /* Tx */
46 .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
47 .cfg_lo = 0,
48 .src_master = DMA_MASTER_MEMORY,
49 .dst_master = DMA_MASTER_SSP0,
50 }, {
51 /* Rx */
52 .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
53 .cfg_lo = 0,
54 .src_master = DMA_MASTER_SSP0,
55 .dst_master = DMA_MASTER_MEMORY,
56 }
57};
58
59struct pl022_ssp_controller pl022_plat_data = {
60 .enable_dma = 1,
61 .dma_filter = dw_dma_filter,
62 .dma_rx_param = &ssp_dma_param[1],
63 .dma_tx_param = &ssp_dma_param[0],
64};
65
66/* CF device registration */
67struct dw_dma_slave cf_dma_priv = {
68 .cfg_hi = 0,
69 .cfg_lo = 0,
70 .src_master = 0,
71 .dst_master = 0,
72};
73
74/* dmac device registeration */
75struct dw_dma_platform_data dmac_plat_data = {
76 .nr_channels = 8,
77 .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
78 .chan_priority = CHAN_PRIORITY_DESCENDING,
79 .block_size = 4095U,
80 .nr_masters = 2,
81 .data_width = { 3, 3, 0, 0 },
82};
83
84void __init spear13xx_l2x0_init(void) 26void __init spear13xx_l2x0_init(void)
85{ 27{
86 /* 28 /*
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index 405022d302c3..7638121cb5d1 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -209,8 +209,6 @@ struct arasan_cf_dev {
209 struct dma_chan *dma_chan; 209 struct dma_chan *dma_chan;
210 /* Mask for DMA transfers */ 210 /* Mask for DMA transfers */
211 dma_cap_mask_t mask; 211 dma_cap_mask_t mask;
212 /* dma channel private data */
213 void *dma_priv;
214 /* DMA transfer work */ 212 /* DMA transfer work */
215 struct work_struct work; 213 struct work_struct work;
216 /* DMA delayed finish work */ 214 /* DMA delayed finish work */
@@ -308,6 +306,7 @@ static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
308static int cf_init(struct arasan_cf_dev *acdev) 306static int cf_init(struct arasan_cf_dev *acdev)
309{ 307{
310 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev); 308 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
309 unsigned int if_clk;
311 unsigned long flags; 310 unsigned long flags;
312 int ret = 0; 311 int ret = 0;
313 312
@@ -325,8 +324,12 @@ static int cf_init(struct arasan_cf_dev *acdev)
325 324
326 spin_lock_irqsave(&acdev->host->lock, flags); 325 spin_lock_irqsave(&acdev->host->lock, flags);
327 /* configure CF interface clock */ 326 /* configure CF interface clock */
328 writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk : 327 /* TODO: read from device tree */
329 CF_IF_CLK_166M, acdev->vbase + CLK_CFG); 328 if_clk = CF_IF_CLK_166M;
329 if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
330 if_clk = pdata->cf_if_clk;
331
332 writel(if_clk, acdev->vbase + CLK_CFG);
330 333
331 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE); 334 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
332 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1); 335 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
@@ -357,12 +360,6 @@ static void dma_callback(void *dev)
357 complete(&acdev->dma_completion); 360 complete(&acdev->dma_completion);
358} 361}
359 362
360static bool filter(struct dma_chan *chan, void *slave)
361{
362 chan->private = slave;
363 return true;
364}
365
366static inline void dma_complete(struct arasan_cf_dev *acdev) 363static inline void dma_complete(struct arasan_cf_dev *acdev)
367{ 364{
368 struct ata_queued_cmd *qc = acdev->qc; 365 struct ata_queued_cmd *qc = acdev->qc;
@@ -530,8 +527,7 @@ static void data_xfer(struct work_struct *work)
530 527
531 /* request dma channels */ 528 /* request dma channels */
532 /* dma_request_channel may sleep, so calling from process context */ 529 /* dma_request_channel may sleep, so calling from process context */
533 acdev->dma_chan = dma_request_channel(acdev->mask, filter, 530 acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
534 acdev->dma_priv);
535 if (!acdev->dma_chan) { 531 if (!acdev->dma_chan) {
536 dev_err(acdev->host->dev, "Unable to get dma_chan\n"); 532 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
537 goto chan_request_fail; 533 goto chan_request_fail;
@@ -798,6 +794,7 @@ static int arasan_cf_probe(struct platform_device *pdev)
798 struct ata_host *host; 794 struct ata_host *host;
799 struct ata_port *ap; 795 struct ata_port *ap;
800 struct resource *res; 796 struct resource *res;
797 u32 quirk;
801 irq_handler_t irq_handler = NULL; 798 irq_handler_t irq_handler = NULL;
802 int ret = 0; 799 int ret = 0;
803 800
@@ -817,12 +814,17 @@ static int arasan_cf_probe(struct platform_device *pdev)
817 return -ENOMEM; 814 return -ENOMEM;
818 } 815 }
819 816
817 if (pdata)
818 quirk = pdata->quirk;
819 else
820 quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
821
820 /* if irq is 0, support only PIO */ 822 /* if irq is 0, support only PIO */
821 acdev->irq = platform_get_irq(pdev, 0); 823 acdev->irq = platform_get_irq(pdev, 0);
822 if (acdev->irq) 824 if (acdev->irq)
823 irq_handler = arasan_cf_interrupt; 825 irq_handler = arasan_cf_interrupt;
824 else 826 else
825 pdata->quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA; 827 quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
826 828
827 acdev->pbase = res->start; 829 acdev->pbase = res->start;
828 acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start, 830 acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
@@ -859,17 +861,16 @@ static int arasan_cf_probe(struct platform_device *pdev)
859 INIT_WORK(&acdev->work, data_xfer); 861 INIT_WORK(&acdev->work, data_xfer);
860 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish); 862 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
861 dma_cap_set(DMA_MEMCPY, acdev->mask); 863 dma_cap_set(DMA_MEMCPY, acdev->mask);
862 acdev->dma_priv = pdata->dma_priv;
863 864
864 /* Handle platform specific quirks */ 865 /* Handle platform specific quirks */
865 if (pdata->quirk) { 866 if (quirk) {
866 if (pdata->quirk & CF_BROKEN_PIO) { 867 if (quirk & CF_BROKEN_PIO) {
867 ap->ops->set_piomode = NULL; 868 ap->ops->set_piomode = NULL;
868 ap->pio_mask = 0; 869 ap->pio_mask = 0;
869 } 870 }
870 if (pdata->quirk & CF_BROKEN_MWDMA) 871 if (quirk & CF_BROKEN_MWDMA)
871 ap->mwdma_mask = 0; 872 ap->mwdma_mask = 0;
872 if (pdata->quirk & CF_BROKEN_UDMA) 873 if (quirk & CF_BROKEN_UDMA)
873 ap->udma_mask = 0; 874 ap->udma_mask = 0;
874 } 875 }
875 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI; 876 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index b0fe393c882c..371cc66f1a0e 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1139,6 +1139,35 @@ err_no_rxchan:
1139 return -ENODEV; 1139 return -ENODEV;
1140} 1140}
1141 1141
1142static int pl022_dma_autoprobe(struct pl022 *pl022)
1143{
1144 struct device *dev = &pl022->adev->dev;
1145
1146 /* automatically configure DMA channels from platform, normally using DT */
1147 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
1148 if (!pl022->dma_rx_channel)
1149 goto err_no_rxchan;
1150
1151 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
1152 if (!pl022->dma_tx_channel)
1153 goto err_no_txchan;
1154
1155 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1156 if (!pl022->dummypage)
1157 goto err_no_dummypage;
1158
1159 return 0;
1160
1161err_no_dummypage:
1162 dma_release_channel(pl022->dma_tx_channel);
1163 pl022->dma_tx_channel = NULL;
1164err_no_txchan:
1165 dma_release_channel(pl022->dma_rx_channel);
1166 pl022->dma_rx_channel = NULL;
1167err_no_rxchan:
1168 return -ENODEV;
1169}
1170
1142static void terminate_dma(struct pl022 *pl022) 1171static void terminate_dma(struct pl022 *pl022)
1143{ 1172{
1144 struct dma_chan *rxchan = pl022->dma_rx_channel; 1173 struct dma_chan *rxchan = pl022->dma_rx_channel;
@@ -1167,6 +1196,11 @@ static inline int configure_dma(struct pl022 *pl022)
1167 return -ENODEV; 1196 return -ENODEV;
1168} 1197}
1169 1198
1199static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1200{
1201 return 0;
1202}
1203
1170static inline int pl022_dma_probe(struct pl022 *pl022) 1204static inline int pl022_dma_probe(struct pl022 *pl022)
1171{ 1205{
1172 return 0; 1206 return 0;
@@ -2226,8 +2260,13 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2226 goto err_no_irq; 2260 goto err_no_irq;
2227 } 2261 }
2228 2262
2229 /* Get DMA channels */ 2263 /* Get DMA channels, try autoconfiguration first */
2230 if (platform_info->enable_dma) { 2264 status = pl022_dma_autoprobe(pl022);
2265
2266 /* If that failed, use channels from platform_info */
2267 if (status == 0)
2268 platform_info->enable_dma = 1;
2269 else if (platform_info->enable_dma) {
2231 status = pl022_dma_probe(pl022); 2270 status = pl022_dma_probe(pl022);
2232 if (status != 0) 2271 if (status != 0)
2233 platform_info->enable_dma = 0; 2272 platform_info->enable_dma = 0;
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3ea5408fcbeb..c25b00ef9dbb 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -245,7 +245,7 @@ static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
245 } 245 }
246} 246}
247 247
248static void pl011_dma_probe_initcall(struct uart_amba_port *uap) 248static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap)
249{ 249{
250 /* DMA is the sole user of the platform data right now */ 250 /* DMA is the sole user of the platform data right now */
251 struct amba_pl011_data *plat = uap->port.dev->platform_data; 251 struct amba_pl011_data *plat = uap->port.dev->platform_data;
@@ -259,20 +259,25 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
259 struct dma_chan *chan; 259 struct dma_chan *chan;
260 dma_cap_mask_t mask; 260 dma_cap_mask_t mask;
261 261
262 /* We need platform data */ 262 chan = dma_request_slave_channel(dev, "tx");
263 if (!plat || !plat->dma_filter) {
264 dev_info(uap->port.dev, "no DMA platform data\n");
265 return;
266 }
267 263
268 /* Try to acquire a generic DMA engine slave TX channel */
269 dma_cap_zero(mask);
270 dma_cap_set(DMA_SLAVE, mask);
271
272 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
273 if (!chan) { 264 if (!chan) {
274 dev_err(uap->port.dev, "no TX DMA channel!\n"); 265 /* We need platform data */
275 return; 266 if (!plat || !plat->dma_filter) {
267 dev_info(uap->port.dev, "no DMA platform data\n");
268 return;
269 }
270
271 /* Try to acquire a generic DMA engine slave TX channel */
272 dma_cap_zero(mask);
273 dma_cap_set(DMA_SLAVE, mask);
274
275 chan = dma_request_channel(mask, plat->dma_filter,
276 plat->dma_tx_param);
277 if (!chan) {
278 dev_err(uap->port.dev, "no TX DMA channel!\n");
279 return;
280 }
276 } 281 }
277 282
278 dmaengine_slave_config(chan, &tx_conf); 283 dmaengine_slave_config(chan, &tx_conf);
@@ -282,7 +287,18 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
282 dma_chan_name(uap->dmatx.chan)); 287 dma_chan_name(uap->dmatx.chan));
283 288
284 /* Optionally make use of an RX channel as well */ 289 /* Optionally make use of an RX channel as well */
285 if (plat->dma_rx_param) { 290 chan = dma_request_slave_channel(dev, "rx");
291
292 if (!chan && plat->dma_rx_param) {
293 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
294
295 if (!chan) {
296 dev_err(uap->port.dev, "no RX DMA channel!\n");
297 return;
298 }
299 }
300
301 if (chan) {
286 struct dma_slave_config rx_conf = { 302 struct dma_slave_config rx_conf = {
287 .src_addr = uap->port.mapbase + UART01x_DR, 303 .src_addr = uap->port.mapbase + UART01x_DR,
288 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 304 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
@@ -291,12 +307,6 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
291 .device_fc = false, 307 .device_fc = false,
292 }; 308 };
293 309
294 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
295 if (!chan) {
296 dev_err(uap->port.dev, "no RX DMA channel!\n");
297 return;
298 }
299
300 dmaengine_slave_config(chan, &rx_conf); 310 dmaengine_slave_config(chan, &rx_conf);
301 uap->dmarx.chan = chan; 311 uap->dmarx.chan = chan;
302 312
@@ -315,6 +325,7 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
315struct dma_uap { 325struct dma_uap {
316 struct list_head node; 326 struct list_head node;
317 struct uart_amba_port *uap; 327 struct uart_amba_port *uap;
328 struct device *dev;
318}; 329};
319 330
320static LIST_HEAD(pl011_dma_uarts); 331static LIST_HEAD(pl011_dma_uarts);
@@ -325,7 +336,7 @@ static int __init pl011_dma_initcall(void)
325 336
326 list_for_each_safe(node, tmp, &pl011_dma_uarts) { 337 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
327 struct dma_uap *dmau = list_entry(node, struct dma_uap, node); 338 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
328 pl011_dma_probe_initcall(dmau->uap); 339 pl011_dma_probe_initcall(dmau->dev, dmau->uap);
329 list_del(node); 340 list_del(node);
330 kfree(dmau); 341 kfree(dmau);
331 } 342 }
@@ -334,18 +345,19 @@ static int __init pl011_dma_initcall(void)
334 345
335device_initcall(pl011_dma_initcall); 346device_initcall(pl011_dma_initcall);
336 347
337static void pl011_dma_probe(struct uart_amba_port *uap) 348static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
338{ 349{
339 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); 350 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
340 if (dmau) { 351 if (dmau) {
341 dmau->uap = uap; 352 dmau->uap = uap;
353 dmau->dev = dev;
342 list_add_tail(&dmau->node, &pl011_dma_uarts); 354 list_add_tail(&dmau->node, &pl011_dma_uarts);
343 } 355 }
344} 356}
345#else 357#else
346static void pl011_dma_probe(struct uart_amba_port *uap) 358static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
347{ 359{
348 pl011_dma_probe_initcall(uap); 360 pl011_dma_probe_initcall(dev, uap);
349} 361}
350#endif 362#endif
351 363
@@ -2020,7 +2032,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2020 uap->port.ops = &amba_pl011_pops; 2032 uap->port.ops = &amba_pl011_pops;
2021 uap->port.flags = UPF_BOOT_AUTOCONF; 2033 uap->port.flags = UPF_BOOT_AUTOCONF;
2022 uap->port.line = i; 2034 uap->port.line = i;
2023 pl011_dma_probe(uap); 2035 pl011_dma_probe(&dev->dev, uap);
2024 2036
2025 /* Ensure interrupts from this UART are masked and cleared */ 2037 /* Ensure interrupts from this UART are masked and cleared */
2026 writew(0, uap->port.membase + UART011_IMSC); 2038 writew(0, uap->port.membase + UART011_IMSC);
diff --git a/include/linux/pata_arasan_cf_data.h b/include/linux/pata_arasan_cf_data.h
index a7b4fc386e63..3cc21c9cc1e8 100644
--- a/include/linux/pata_arasan_cf_data.h
+++ b/include/linux/pata_arasan_cf_data.h
@@ -37,8 +37,6 @@ struct arasan_cf_pdata {
37 #define CF_BROKEN_PIO (1) 37 #define CF_BROKEN_PIO (1)
38 #define CF_BROKEN_MWDMA (1 << 1) 38 #define CF_BROKEN_MWDMA (1 << 1)
39 #define CF_BROKEN_UDMA (1 << 2) 39 #define CF_BROKEN_UDMA (1 << 2)
40 /* This is platform specific data for the DMA controller */
41 void *dma_priv;
42}; 40};
43 41
44static inline void 42static inline void
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 22:19:28 -0500