diff options
author | Stephen Boyd <sboyd@codeaurora.org> | 2013-07-18 19:21:29 -0400 |
---|---|---|
committer | John Stultz <john.stultz@linaro.org> | 2013-07-30 14:24:56 -0400 |
commit | f4e6e1ea19737077d958f2bc6c196eb579d97544 (patch) | |
tree | 566ff9277990ca75e46e8584b47e2fa4a861ac1c | |
parent | 130e6b25a28ff5b2421d6cae5f2bac1f5afdcfb0 (diff) |
clocksource: vf_pit_timer: Switch to sched_clock_register()
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Jingchang Lu <b35083@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
-rw-r--r-- | drivers/clocksource/vf_pit_timer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c index 587e0202a70b..02821b06a39e 100644 --- a/drivers/clocksource/vf_pit_timer.c +++ b/drivers/clocksource/vf_pit_timer.c | |||
@@ -52,7 +52,7 @@ static inline void pit_irq_acknowledge(void) | |||
52 | __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); | 52 | __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); |
53 | } | 53 | } |
54 | 54 | ||
55 | static unsigned int pit_read_sched_clock(void) | 55 | static u64 pit_read_sched_clock(void) |
56 | { | 56 | { |
57 | return __raw_readl(clksrc_base + PITCVAL); | 57 | return __raw_readl(clksrc_base + PITCVAL); |
58 | } | 58 | } |
@@ -64,7 +64,7 @@ static int __init pit_clocksource_init(unsigned long rate) | |||
64 | __raw_writel(~0UL, clksrc_base + PITLDVAL); | 64 | __raw_writel(~0UL, clksrc_base + PITLDVAL); |
65 | __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); | 65 | __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); |
66 | 66 | ||
67 | setup_sched_clock(pit_read_sched_clock, 32, rate); | 67 | sched_clock_register(pit_read_sched_clock, 32, rate); |
68 | return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, | 68 | return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, |
69 | 300, 32, clocksource_mmio_readl_down); | 69 | 300, 32, clocksource_mmio_readl_down); |
70 | } | 70 | } |