diff options
author | Thomas Abraham <thomas.ab@samsung.com> | 2010-05-16 20:38:52 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-16 21:37:37 -0400 |
commit | f445dbd5af7863dd7dce4685e39980419d4144eb (patch) | |
tree | 194f8c8302003aaeef8d9df7e37b8156e5bcddb2 | |
parent | f44cf78b6b475116a4d3c98576f8697dd4ca7e79 (diff) |
ARM: S5PV210: Add support for VPLL
This patch adds the following.
1. Adds 'clk_sclk_hdmi27m' clock to represent the HDMI 27MHz clock.
2. Adds 'clk_vpllsrc; clock of type clksrc_clk to represent the
input clock for VPLL.
3. Adds 'clk_sclk_vpll' clock of type clksrc_clk to represent the
output of the MUX_VPLL mux.
4. Add clk_sclk_hdmi27m, clk_vpllsrc and clk_sclk_vpll to the list
of clocks to be registered.
5. Adds boot time print of 'clk_sclk_vpll' clock rate.
6. Adds 'clk_fout_vpll' clock to plat-s5p such that it is reusable
on other s5p platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
-rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 63 | ||||
-rw-r--r-- | arch/arm/plat-s5p/clock.c | 8 | ||||
-rw-r--r-- | arch/arm/plat-s5p/include/plat/s5p-clock.h | 1 |
3 files changed, 70 insertions, 2 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 315955da0d06..c86bff525dbe 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -173,6 +173,57 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) | |||
173 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | 173 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); |
174 | } | 174 | } |
175 | 175 | ||
176 | static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) | ||
177 | { | ||
178 | return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); | ||
179 | } | ||
180 | |||
181 | static struct clk clk_sclk_hdmi27m = { | ||
182 | .name = "sclk_hdmi27m", | ||
183 | .id = -1, | ||
184 | .rate = 27000000, | ||
185 | }; | ||
186 | |||
187 | static struct clk *clkset_vpllsrc_list[] = { | ||
188 | [0] = &clk_fin_vpll, | ||
189 | [1] = &clk_sclk_hdmi27m, | ||
190 | }; | ||
191 | |||
192 | static struct clksrc_sources clkset_vpllsrc = { | ||
193 | .sources = clkset_vpllsrc_list, | ||
194 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | ||
195 | }; | ||
196 | |||
197 | static struct clksrc_clk clk_vpllsrc = { | ||
198 | .clk = { | ||
199 | .name = "vpll_src", | ||
200 | .id = -1, | ||
201 | .enable = s5pv210_clk_mask0_ctrl, | ||
202 | .ctrlbit = (1 << 7), | ||
203 | }, | ||
204 | .sources = &clkset_vpllsrc, | ||
205 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, | ||
206 | }; | ||
207 | |||
208 | static struct clk *clkset_sclk_vpll_list[] = { | ||
209 | [0] = &clk_vpllsrc.clk, | ||
210 | [1] = &clk_fout_vpll, | ||
211 | }; | ||
212 | |||
213 | static struct clksrc_sources clkset_sclk_vpll = { | ||
214 | .sources = clkset_sclk_vpll_list, | ||
215 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | ||
216 | }; | ||
217 | |||
218 | static struct clksrc_clk clk_sclk_vpll = { | ||
219 | .clk = { | ||
220 | .name = "sclk_vpll", | ||
221 | .id = -1, | ||
222 | }, | ||
223 | .sources = &clkset_sclk_vpll, | ||
224 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | ||
225 | }; | ||
226 | |||
176 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) | 227 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) |
177 | { | 228 | { |
178 | return clk_get_rate(clk->parent) / 2; | 229 | return clk_get_rate(clk->parent) / 2; |
@@ -402,12 +453,15 @@ static struct clksrc_clk *sysclks[] = { | |||
402 | &clk_pclk_msys, | 453 | &clk_pclk_msys, |
403 | &clk_pclk_dsys, | 454 | &clk_pclk_dsys, |
404 | &clk_pclk_psys, | 455 | &clk_pclk_psys, |
456 | &clk_vpllsrc, | ||
457 | &clk_sclk_vpll, | ||
405 | }; | 458 | }; |
406 | 459 | ||
407 | void __init_or_cpufreq s5pv210_setup_clocks(void) | 460 | void __init_or_cpufreq s5pv210_setup_clocks(void) |
408 | { | 461 | { |
409 | struct clk *xtal_clk; | 462 | struct clk *xtal_clk; |
410 | unsigned long xtal; | 463 | unsigned long xtal; |
464 | unsigned long vpllsrc; | ||
411 | unsigned long armclk; | 465 | unsigned long armclk; |
412 | unsigned long hclk_msys; | 466 | unsigned long hclk_msys; |
413 | unsigned long hclk_dsys; | 467 | unsigned long hclk_dsys; |
@@ -418,6 +472,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
418 | unsigned long apll; | 472 | unsigned long apll; |
419 | unsigned long mpll; | 473 | unsigned long mpll; |
420 | unsigned long epll; | 474 | unsigned long epll; |
475 | unsigned long vpll; | ||
421 | unsigned int ptr; | 476 | unsigned int ptr; |
422 | u32 clkdiv0, clkdiv1; | 477 | u32 clkdiv0, clkdiv1; |
423 | 478 | ||
@@ -440,13 +495,16 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
440 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | 495 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); |
441 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | 496 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); |
442 | epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); | 497 | epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); |
498 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); | ||
499 | vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); | ||
443 | 500 | ||
444 | clk_fout_apll.rate = apll; | 501 | clk_fout_apll.rate = apll; |
445 | clk_fout_mpll.rate = mpll; | 502 | clk_fout_mpll.rate = mpll; |
446 | clk_fout_epll.rate = epll; | 503 | clk_fout_epll.rate = epll; |
504 | clk_fout_vpll.rate = vpll; | ||
447 | 505 | ||
448 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", | 506 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
449 | apll, mpll, epll); | 507 | apll, mpll, epll, vpll); |
450 | 508 | ||
451 | armclk = clk_get_rate(&clk_armclk.clk); | 509 | armclk = clk_get_rate(&clk_armclk.clk); |
452 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); | 510 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
@@ -470,6 +528,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
470 | } | 528 | } |
471 | 529 | ||
472 | static struct clk *clks[] __initdata = { | 530 | static struct clk *clks[] __initdata = { |
531 | &clk_sclk_hdmi27m, | ||
473 | }; | 532 | }; |
474 | 533 | ||
475 | void __init s5pv210_register_clocks(void) | 534 | void __init s5pv210_register_clocks(void) |
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index aa96e335073b..4ca0759fa228 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c | |||
@@ -69,6 +69,13 @@ struct clk clk_fout_epll = { | |||
69 | .ctrlbit = (1 << 31), | 69 | .ctrlbit = (1 << 31), |
70 | }; | 70 | }; |
71 | 71 | ||
72 | /* VPLL clock output */ | ||
73 | struct clk clk_fout_vpll = { | ||
74 | .name = "fout_vpll", | ||
75 | .id = -1, | ||
76 | .ctrlbit = (1 << 31), | ||
77 | }; | ||
78 | |||
72 | /* ARM clock */ | 79 | /* ARM clock */ |
73 | struct clk clk_arm = { | 80 | struct clk clk_arm = { |
74 | .name = "armclk", | 81 | .name = "armclk", |
@@ -133,6 +140,7 @@ static struct clk *s5p_clks[] __initdata = { | |||
133 | &clk_fout_apll, | 140 | &clk_fout_apll, |
134 | &clk_fout_mpll, | 141 | &clk_fout_mpll, |
135 | &clk_fout_epll, | 142 | &clk_fout_epll, |
143 | &clk_fout_vpll, | ||
136 | &clk_arm, | 144 | &clk_arm, |
137 | &clk_vpll, | 145 | &clk_vpll, |
138 | }; | 146 | }; |
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h index 56fb8b414d41..5ae8866b7989 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h | |||
@@ -27,6 +27,7 @@ extern struct clk clk_48m; | |||
27 | extern struct clk clk_fout_apll; | 27 | extern struct clk clk_fout_apll; |
28 | extern struct clk clk_fout_mpll; | 28 | extern struct clk clk_fout_mpll; |
29 | extern struct clk clk_fout_epll; | 29 | extern struct clk clk_fout_epll; |
30 | extern struct clk clk_fout_vpll; | ||
30 | extern struct clk clk_arm; | 31 | extern struct clk clk_arm; |
31 | extern struct clk clk_vpll; | 32 | extern struct clk clk_vpll; |
32 | 33 | ||