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authorDave Airlie <airlied@redhat.com>2015-01-26 18:14:15 -0500
committerDave Airlie <airlied@redhat.com>2015-01-26 18:14:15 -0500
commitf43dff0ee00a259f524ce17ba4f8030553c66590 (patch)
treea26355ed5a6a7df27e885b5beb4a9ff49b6b49fb
parente37bfa1aac6dd98ad17d98b4691c40ff561ba410 (diff)
parentf9dcced8d49804081850f78b2336c83cf050eeab (diff)
Merge tag 'drm-amdkfd-next-fixes-2015-01-25' of git://people.freedesktop.org/~gabbayo/linux into drm-next
Here is a pull request of fixes for 3.20 patches, including the fix you asked me when you merged the previous pull request. * tag 'drm-amdkfd-next-fixes-2015-01-25' of git://people.freedesktop.org/~gabbayo/linux: drm/amdkfd: change amdkfd version to 0.7.1 drm/radeon: cik_sdma_ctx_switch_enable() can be static drm/amdkfd: Fix sparse errors drm/amdkfd: Handle case of invalid queue type drm/amdkfd: Add break at the end of case drm/amdkfd: Remove negative check of uint variable
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_chardev.c16
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c38
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h20
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c3
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_module.c4
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c2
6 files changed, 42 insertions, 41 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 732087dcac91..5c50aa8a8908 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -141,8 +141,6 @@ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
141static int set_queue_properties_from_user(struct queue_properties *q_properties, 141static int set_queue_properties_from_user(struct queue_properties *q_properties,
142 struct kfd_ioctl_create_queue_args *args) 142 struct kfd_ioctl_create_queue_args *args)
143{ 143{
144 void *tmp;
145
146 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { 144 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
147 pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 145 pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
148 return -EINVAL; 146 return -EINVAL;
@@ -180,16 +178,18 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,
180 return -EFAULT; 178 return -EFAULT;
181 } 179 }
182 180
183 tmp = (void *)(uintptr_t)args->eop_buffer_address; 181 if (args->eop_buffer_address &&
184 if (tmp != NULL && 182 !access_ok(VERIFY_WRITE,
185 !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { 183 (const void __user *) args->eop_buffer_address,
184 sizeof(uint32_t))) {
186 pr_debug("kfd: can't access eop buffer"); 185 pr_debug("kfd: can't access eop buffer");
187 return -EFAULT; 186 return -EFAULT;
188 } 187 }
189 188
190 tmp = (void *)(uintptr_t)args->ctx_save_restore_address; 189 if (args->ctx_save_restore_address &&
191 if (tmp != NULL && 190 !access_ok(VERIFY_WRITE,
192 !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { 191 (const void __user *) args->ctx_save_restore_address,
192 sizeof(uint32_t))) {
193 pr_debug("kfd: can't access ctx save restore buffer"); 193 pr_debug("kfd: can't access ctx save restore buffer");
194 return -EFAULT; 194 return -EFAULT;
195 } 195 }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a5c69e96ba6f..b189f9791c90 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -62,12 +62,6 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
62 return KFD_MQD_TYPE_CP; 62 return KFD_MQD_TYPE_CP;
63} 63}
64 64
65inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
66{
67 BUG_ON(!dqm || !dqm->dev);
68 return dqm->dev->shared_resources.compute_pipe_count;
69}
70
71static inline unsigned int get_first_pipe(struct device_queue_manager *dqm) 65static inline unsigned int get_first_pipe(struct device_queue_manager *dqm)
72{ 66{
73 BUG_ON(!dqm); 67 BUG_ON(!dqm);
@@ -79,25 +73,6 @@ static inline unsigned int get_pipes_num_cpsch(void)
79 return PIPE_PER_ME_CP_SCHEDULING; 73 return PIPE_PER_ME_CP_SCHEDULING;
80} 74}
81 75
82inline unsigned int
83get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
84{
85 uint32_t nybble;
86
87 nybble = (pdd->lds_base >> 60) & 0x0E;
88
89 return nybble;
90}
91
92inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
93{
94 unsigned int shared_base;
95
96 shared_base = (pdd->lds_base >> 16) & 0xFF;
97
98 return shared_base;
99}
100
101void program_sh_mem_settings(struct device_queue_manager *dqm, 76void program_sh_mem_settings(struct device_queue_manager *dqm,
102 struct qcm_process_device *qpd) 77 struct qcm_process_device *qpd)
103{ 78{
@@ -301,6 +276,11 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
301 } 276 }
302 dqm->sdma_queue_count--; 277 dqm->sdma_queue_count--;
303 deallocate_sdma_queue(dqm, q->sdma_id); 278 deallocate_sdma_queue(dqm, q->sdma_id);
279 } else {
280 pr_debug("q->properties.type is invalid (%d)\n",
281 q->properties.type);
282 retval = -EINVAL;
283 goto out;
304 } 284 }
305 285
306 retval = mqd->destroy_mqd(mqd, q->mqd, 286 retval = mqd->destroy_mqd(mqd, q->mqd,
@@ -331,7 +311,8 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
331 BUG_ON(!dqm || !q || !q->mqd); 311 BUG_ON(!dqm || !q || !q->mqd);
332 312
333 mutex_lock(&dqm->lock); 313 mutex_lock(&dqm->lock);
334 mqd = dqm->ops.get_mqd_manager(dqm, q->properties.type); 314 mqd = dqm->ops.get_mqd_manager(dqm,
315 get_mqd_type_from_queue_type(q->properties.type));
335 if (mqd == NULL) { 316 if (mqd == NULL) {
336 mutex_unlock(&dqm->lock); 317 mutex_unlock(&dqm->lock);
337 return -ENOMEM; 318 return -ENOMEM;
@@ -587,7 +568,7 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,
587static void deallocate_sdma_queue(struct device_queue_manager *dqm, 568static void deallocate_sdma_queue(struct device_queue_manager *dqm,
588 unsigned int sdma_queue_id) 569 unsigned int sdma_queue_id)
589{ 570{
590 if (sdma_queue_id < 0 || sdma_queue_id >= CIK_SDMA_QUEUES) 571 if (sdma_queue_id >= CIK_SDMA_QUEUES)
591 return; 572 return;
592 set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap); 573 set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
593} 574}
@@ -1114,8 +1095,11 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1114 switch (dev->device_info->asic_family) { 1095 switch (dev->device_info->asic_family) {
1115 case CHIP_CARRIZO: 1096 case CHIP_CARRIZO:
1116 device_queue_manager_init_vi(&dqm->ops_asic_specific); 1097 device_queue_manager_init_vi(&dqm->ops_asic_specific);
1098 break;
1099
1117 case CHIP_KAVERI: 1100 case CHIP_KAVERI:
1118 device_queue_manager_init_cik(&dqm->ops_asic_specific); 1101 device_queue_manager_init_cik(&dqm->ops_asic_specific);
1102 break;
1119 } 1103 }
1120 1104
1121 if (dqm->ops.initialize(dqm) != 0) { 1105 if (dqm->ops.initialize(dqm) != 0) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index 19347956eeb9..e7b17b28330e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -160,10 +160,24 @@ void device_queue_manager_init_cik(struct device_queue_manager_ops *ops);
160void device_queue_manager_init_vi(struct device_queue_manager_ops *ops); 160void device_queue_manager_init_vi(struct device_queue_manager_ops *ops);
161void program_sh_mem_settings(struct device_queue_manager *dqm, 161void program_sh_mem_settings(struct device_queue_manager *dqm,
162 struct qcm_process_device *qpd); 162 struct qcm_process_device *qpd);
163inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *qpd);
164inline unsigned int get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd);
165int init_pipelines(struct device_queue_manager *dqm, 163int init_pipelines(struct device_queue_manager *dqm,
166 unsigned int pipes_num, unsigned int first_pipe); 164 unsigned int pipes_num, unsigned int first_pipe);
167inline unsigned int get_pipes_num(struct device_queue_manager *dqm); 165
166extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
167{
168 return (pdd->lds_base >> 16) & 0xFF;
169}
170
171extern inline unsigned int
172get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
173{
174 return (pdd->lds_base >> 60) & 0x0E;
175}
176
177extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
178{
179 BUG_ON(!dqm || !dqm->dev);
180 return dqm->dev->shared_resources.compute_pipe_count;
181}
168 182
169#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */ 183#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index c04b1ac60bd9..e415a2a9207e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -288,8 +288,11 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
288 switch (dev->device_info->asic_family) { 288 switch (dev->device_info->asic_family) {
289 case CHIP_CARRIZO: 289 case CHIP_CARRIZO:
290 kernel_queue_init_vi(&kq->ops_asic_specific); 290 kernel_queue_init_vi(&kq->ops_asic_specific);
291 break;
292
291 case CHIP_KAVERI: 293 case CHIP_KAVERI:
292 kernel_queue_init_cik(&kq->ops_asic_specific); 294 kernel_queue_init_cik(&kq->ops_asic_specific);
295 break;
293 } 296 }
294 297
295 if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { 298 if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 14c4115c4ae1..ac5445415667 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -29,10 +29,10 @@
29#define KFD_DRIVER_AUTHOR "AMD Inc. and others" 29#define KFD_DRIVER_AUTHOR "AMD Inc. and others"
30 30
31#define KFD_DRIVER_DESC "Standalone HSA driver for AMD's GPUs" 31#define KFD_DRIVER_DESC "Standalone HSA driver for AMD's GPUs"
32#define KFD_DRIVER_DATE "20141113" 32#define KFD_DRIVER_DATE "20150122"
33#define KFD_DRIVER_MAJOR 0 33#define KFD_DRIVER_MAJOR 0
34#define KFD_DRIVER_MINOR 7 34#define KFD_DRIVER_MINOR 7
35#define KFD_DRIVER_PATCHLEVEL 0 35#define KFD_DRIVER_PATCHLEVEL 1
36 36
37const struct kfd2kgd_calls *kfd2kgd; 37const struct kfd2kgd_calls *kfd2kgd;
38static const struct kgd2kfd_calls kgd2kfd = { 38static const struct kgd2kfd_calls kgd2kfd = {
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 479519c24a1f..7d2ff31c35a5 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -290,7 +290,7 @@ static void cik_sdma_rlc_stop(struct radeon_device *rdev)
290 * 290 *
291 * Halt or unhalt the async dma engines (CIK). 291 * Halt or unhalt the async dma engines (CIK).
292 */ 292 */
293void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable) 293static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
294{ 294{
295 uint32_t reg_offset, value; 295 uint32_t reg_offset, value;
296 int i; 296 int i;