diff options
author | Markos Chandras <markos.chandras@imgtec.com> | 2014-04-08 07:47:07 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-30 08:54:56 -0400 |
commit | f3ec7a23b640a064410e31afe9a203f7c125460e (patch) | |
tree | 801531cb2323295bbb3aac69e2da3d9ee2e813c5 | |
parent | 4c12a854d81db5454436c015ec30f39882e923a4 (diff) |
MIPS: uasm: Add mfhi uasm instruction
It will be used later on by bpf-jit
[ralf@linux-mips.org: Resolved conflict.]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6728/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/include/asm/uasm.h | 1 | ||||
-rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm-micromips.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm-mips.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm.c | 10 |
5 files changed, 10 insertions, 4 deletions
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 676c12370bab..38312d8cde57 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h | |||
@@ -131,6 +131,7 @@ Ip_u1s2(_lui); | |||
131 | Ip_u2s3u1(_lw); | 131 | Ip_u2s3u1(_lw); |
132 | Ip_u3u1u2(_lwx); | 132 | Ip_u3u1u2(_lwx); |
133 | Ip_u1u2u3(_mfc0); | 133 | Ip_u1u2u3(_mfc0); |
134 | Ip_u1(_mfhi); | ||
134 | Ip_u1u2u3(_mtc0); | 135 | Ip_u1u2u3(_mtc0); |
135 | Ip_u3u1u2(_or); | 136 | Ip_u3u1u2(_or); |
136 | Ip_u2u1u3(_ori); | 137 | Ip_u2u1u3(_ori); |
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index a4bef362d7a8..a7f6a16fd26c 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h | |||
@@ -300,6 +300,7 @@ enum mm_32axf_minor_op { | |||
300 | mm_mfc0_op = 0x003, | 300 | mm_mfc0_op = 0x003, |
301 | mm_mtc0_op = 0x00b, | 301 | mm_mtc0_op = 0x00b, |
302 | mm_tlbp_op = 0x00d, | 302 | mm_tlbp_op = 0x00d, |
303 | mm_mfhi32_op = 0x035, | ||
303 | mm_jalr_op = 0x03c, | 304 | mm_jalr_op = 0x03c, |
304 | mm_tlbr_op = 0x04d, | 305 | mm_tlbr_op = 0x04d, |
305 | mm_jalrhb_op = 0x07c, | 306 | mm_jalrhb_op = 0x07c, |
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c index aefe7441e620..c04c9c95c3c7 100644 --- a/arch/mips/mm/uasm-micromips.c +++ b/arch/mips/mm/uasm-micromips.c | |||
@@ -86,6 +86,7 @@ static struct insn insn_table_MM[] = { | |||
86 | { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, | 86 | { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, |
87 | { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, | 87 | { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, |
88 | { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, | 88 | { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, |
89 | { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, | ||
89 | { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, | 90 | { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, |
90 | { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, | 91 | { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, |
91 | { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, | 92 | { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, |
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index 6f51543dceac..07184927b733 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c | |||
@@ -94,6 +94,7 @@ static struct insn insn_table[] = { | |||
94 | { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 94 | { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
95 | { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, | 95 | { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, |
96 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, | 96 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, |
97 | { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD }, | ||
97 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, | 98 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
98 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, | 99 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
99 | { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, | 100 | { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, |
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 31873cdd8021..29fc43278801 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -51,10 +51,11 @@ enum opcode { | |||
51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, | 51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, |
52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, | 52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, |
53 | insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, | 53 | insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, |
54 | insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, | 54 | insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, |
55 | insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv, | 55 | insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, |
56 | insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, | 56 | insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, |
57 | insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield, | 57 | insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, |
58 | insn_xori, insn_yield, | ||
58 | }; | 59 | }; |
59 | 60 | ||
60 | struct insn { | 61 | struct insn { |
@@ -273,6 +274,7 @@ I_u2s3u1(_lld) | |||
273 | I_u1s2(_lui) | 274 | I_u1s2(_lui) |
274 | I_u2s3u1(_lw) | 275 | I_u2s3u1(_lw) |
275 | I_u1u2u3(_mfc0) | 276 | I_u1u2u3(_mfc0) |
277 | I_u1(_mfhi) | ||
276 | I_u1u2u3(_mtc0) | 278 | I_u1u2u3(_mtc0) |
277 | I_u2u1u3(_ori) | 279 | I_u2u1u3(_ori) |
278 | I_u3u1u2(_or) | 280 | I_u3u1u2(_or) |