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authorBen Skeggs <bskeggs@redhat.com>2015-01-13 08:37:38 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:42 -0500
commitf3867f439fd610db0cbcf1bb739001e95b7b25c6 (patch)
treec3421012674292cf01d94f66c14e72d9272ad424
parentc39f472e9f14e49a9bc091977ced0ec45fc00c57 (diff)
drm/nouveau/clk: rename from clock (no binary change)
Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/dispnv04/crtc.c4
-rw-r--r--drivers/gpu/drm/nouveau/dispnv04/hw.c4
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/device.h4
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/device.h2
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h166
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h166
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c34
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c20
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c)78
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c)80
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c)34
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c)64
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c)64
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h)16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c)14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c)106
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h20
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c)60
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c)108
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c)118
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h)0
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c)0
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c)2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h)0
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h20
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c12
45 files changed, 690 insertions, 690 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 38402ade6835..f8ddae26dfbf 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -41,7 +41,7 @@
41#include "disp.h" 41#include "disp.h"
42 42
43#include <subdev/bios/pll.h> 43#include <subdev/bios/pll.h>
44#include <subdev/clock.h> 44#include <subdev/clk.h>
45 45
46static int 46static int
47nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 47nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
@@ -113,7 +113,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
113 struct drm_device *dev = crtc->dev; 113 struct drm_device *dev = crtc->dev;
114 struct nouveau_drm *drm = nouveau_drm(dev); 114 struct nouveau_drm *drm = nouveau_drm(dev);
115 struct nouveau_bios *bios = nvkm_bios(&drm->device); 115 struct nouveau_bios *bios = nvkm_bios(&drm->device);
116 struct nouveau_clock *clk = nvkm_clock(&drm->device); 116 struct nouveau_clk *clk = nvkm_clk(&drm->device);
117 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 117 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
119 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 119 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index 3d4c19300768..f9491f926c14 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -253,7 +253,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
253 253
254 struct nouveau_drm *drm = nouveau_drm(dev); 254 struct nouveau_drm *drm = nouveau_drm(dev);
255 struct nvif_device *device = &drm->device; 255 struct nvif_device *device = &drm->device;
256 struct nouveau_clock *clk = nvkm_clock(device); 256 struct nouveau_clk *clk = nvkm_clk(device);
257 struct nouveau_bios *bios = nvkm_bios(device); 257 struct nouveau_bios *bios = nvkm_bios(device);
258 struct nvbios_pll pll_lim; 258 struct nvbios_pll pll_lim;
259 struct nouveau_pll_vals pv; 259 struct nouveau_pll_vals pv;
@@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
463 struct nv04_mode_state *state) 463 struct nv04_mode_state *state)
464{ 464{
465 struct nouveau_drm *drm = nouveau_drm(dev); 465 struct nouveau_drm *drm = nouveau_drm(dev);
466 struct nouveau_clock *clk = nvkm_clock(&drm->device); 466 struct nouveau_clk *clk = nvkm_clk(&drm->device);
467 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 467 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
468 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 468 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
469 int i; 469 int i;
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 4aa1b93a8cd4..e73a16dd97fa 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -32,7 +32,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
32#include <subdev/vm.h> 32#include <subdev/vm.h>
33#include <subdev/bar.h> 33#include <subdev/bar.h>
34#include <subdev/gpio.h> 34#include <subdev/gpio.h>
35#include <subdev/clock.h> 35#include <subdev/clk.h>
36#include <subdev/i2c.h> 36#include <subdev/i2c.h>
37#include <subdev/timer.h> 37#include <subdev/timer.h>
38#include <subdev/therm.h> 38#include <subdev/therm.h>
@@ -43,7 +43,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
43#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) 43#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a))
44#define nvkm_bar(a) nouveau_bar(nvkm_device(a)) 44#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
45#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) 45#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
46#define nvkm_clock(a) nouveau_clock(nvkm_device(a)) 46#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
47#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a)) 47#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a))
48#define nvkm_timer(a) nouveau_timer(nvkm_device(a)) 48#define nvkm_timer(a) nouveau_timer(nvkm_device(a))
49#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d)) 49#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 21a055aca513..87ecf6d23d9e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -38,7 +38,7 @@ enum nv_subdev_type {
38 NVDEV_SUBDEV_PWR, 38 NVDEV_SUBDEV_PWR,
39 NVDEV_SUBDEV_VOLT, 39 NVDEV_SUBDEV_VOLT,
40 NVDEV_SUBDEV_THERM, 40 NVDEV_SUBDEV_THERM,
41 NVDEV_SUBDEV_CLOCK, 41 NVDEV_SUBDEV_CLK,
42 42
43 NVDEV_ENGINE_FIRST, 43 NVDEV_ENGINE_FIRST,
44 NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, 44 NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
new file mode 100644
index 000000000000..4524d4eea2f1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -0,0 +1,166 @@
1#ifndef __NOUVEAU_CLK_H__
2#define __NOUVEAU_CLK_H__
3
4#include <core/device.h>
5#include <core/subdev.h>
6
7struct nouveau_pll_vals;
8struct nvbios_pll;
9
10enum nv_clk_src {
11 nv_clk_src_crystal,
12 nv_clk_src_href,
13
14 nv_clk_src_hclk,
15 nv_clk_src_hclkm3,
16 nv_clk_src_hclkm3d2,
17 nv_clk_src_hclkm2d3, /* NVAA */
18 nv_clk_src_hclkm4, /* NVAA */
19 nv_clk_src_cclk, /* NVAA */
20
21 nv_clk_src_host,
22
23 nv_clk_src_sppll0,
24 nv_clk_src_sppll1,
25
26 nv_clk_src_mpllsrcref,
27 nv_clk_src_mpllsrc,
28 nv_clk_src_mpll,
29 nv_clk_src_mdiv,
30
31 nv_clk_src_core,
32 nv_clk_src_core_intm,
33 nv_clk_src_shader,
34
35 nv_clk_src_mem,
36
37 nv_clk_src_gpc,
38 nv_clk_src_rop,
39 nv_clk_src_hubk01,
40 nv_clk_src_hubk06,
41 nv_clk_src_hubk07,
42 nv_clk_src_copy,
43 nv_clk_src_daemon,
44 nv_clk_src_disp,
45 nv_clk_src_vdec,
46
47 nv_clk_src_dom6,
48
49 nv_clk_src_max,
50};
51
52struct nouveau_cstate {
53 struct list_head head;
54 u8 voltage;
55 u32 domain[nv_clk_src_max];
56};
57
58struct nouveau_pstate {
59 struct list_head head;
60 struct list_head list; /* c-states */
61 struct nouveau_cstate base;
62 u8 pstate;
63 u8 fanspeed;
64};
65
66struct nouveau_clk {
67 struct nouveau_subdev base;
68
69 struct nouveau_domain *domains;
70 struct nouveau_pstate bstate;
71
72 struct list_head states;
73 int state_nr;
74
75 struct work_struct work;
76 wait_queue_head_t wait;
77 atomic_t waiting;
78
79 struct nvkm_notify pwrsrc_ntfy;
80 int pwrsrc;
81 int pstate; /* current */
82 int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
83 int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
84 int astate; /* perfmon adjustment (base) */
85 int tstate; /* thermal adjustment (max-) */
86 int dstate; /* display adjustment (min+) */
87
88 bool allow_reclock;
89
90 int (*read)(struct nouveau_clk *, enum nv_clk_src);
91 int (*calc)(struct nouveau_clk *, struct nouveau_cstate *);
92 int (*prog)(struct nouveau_clk *);
93 void (*tidy)(struct nouveau_clk *);
94
95 /*XXX: die, these are here *only* to support the completely
96 * bat-shit insane what-was-nouveau_hw.c code
97 */
98 int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *,
99 int clk, struct nouveau_pll_vals *pv);
100 int (*pll_prog)(struct nouveau_clk *, u32 reg1,
101 struct nouveau_pll_vals *pv);
102};
103
104static inline struct nouveau_clk *
105nouveau_clk(void *obj)
106{
107 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK);
108}
109
110struct nouveau_domain {
111 enum nv_clk_src name;
112 u8 bios; /* 0xff for none */
113#define NVKM_CLK_DOM_FLAG_CORE 0x01
114 u8 flags;
115 const char *mname;
116 int mdiv;
117};
118
119#define nouveau_clk_create(p,e,o,i,r,s,n,d) \
120 nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
121 (void **)d)
122#define nouveau_clk_destroy(p) ({ \
123 struct nouveau_clk *clk = (p); \
124 _nouveau_clk_dtor(nv_object(clk)); \
125})
126#define nouveau_clk_init(p) ({ \
127 struct nouveau_clk *clk = (p); \
128 _nouveau_clk_init(nv_object(clk)); \
129})
130#define nouveau_clk_fini(p,s) ({ \
131 struct nouveau_clk *clk = (p); \
132 _nouveau_clk_fini(nv_object(clk), (s)); \
133})
134
135int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *,
136 struct nouveau_oclass *,
137 struct nouveau_domain *, struct nouveau_pstate *,
138 int, bool, int, void **);
139void _nouveau_clk_dtor(struct nouveau_object *);
140int _nouveau_clk_init(struct nouveau_object *);
141int _nouveau_clk_fini(struct nouveau_object *, bool);
142
143extern struct nouveau_oclass nv04_clk_oclass;
144extern struct nouveau_oclass nv40_clk_oclass;
145extern struct nouveau_oclass *nv50_clk_oclass;
146extern struct nouveau_oclass *nv84_clk_oclass;
147extern struct nouveau_oclass *nvaa_clk_oclass;
148extern struct nouveau_oclass nva3_clk_oclass;
149extern struct nouveau_oclass nvc0_clk_oclass;
150extern struct nouveau_oclass nve0_clk_oclass;
151extern struct nouveau_oclass gk20a_clk_oclass;
152
153int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq);
154int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
155 int clk, struct nouveau_pll_vals *);
156int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1,
157 struct nouveau_pll_vals *);
158int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
159 int clk, struct nouveau_pll_vals *);
160
161int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr);
162int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait);
163int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel);
164int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel);
165
166#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
deleted file mode 100644
index 39ad2d2cee2a..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
+++ /dev/null
@@ -1,166 +0,0 @@
1#ifndef __NOUVEAU_CLOCK_H__
2#define __NOUVEAU_CLOCK_H__
3
4#include <core/device.h>
5#include <core/subdev.h>
6
7struct nouveau_pll_vals;
8struct nvbios_pll;
9
10enum nv_clk_src {
11 nv_clk_src_crystal,
12 nv_clk_src_href,
13
14 nv_clk_src_hclk,
15 nv_clk_src_hclkm3,
16 nv_clk_src_hclkm3d2,
17 nv_clk_src_hclkm2d3, /* NVAA */
18 nv_clk_src_hclkm4, /* NVAA */
19 nv_clk_src_cclk, /* NVAA */
20
21 nv_clk_src_host,
22
23 nv_clk_src_sppll0,
24 nv_clk_src_sppll1,
25
26 nv_clk_src_mpllsrcref,
27 nv_clk_src_mpllsrc,
28 nv_clk_src_mpll,
29 nv_clk_src_mdiv,
30
31 nv_clk_src_core,
32 nv_clk_src_core_intm,
33 nv_clk_src_shader,
34
35 nv_clk_src_mem,
36
37 nv_clk_src_gpc,
38 nv_clk_src_rop,
39 nv_clk_src_hubk01,
40 nv_clk_src_hubk06,
41 nv_clk_src_hubk07,
42 nv_clk_src_copy,
43 nv_clk_src_daemon,
44 nv_clk_src_disp,
45 nv_clk_src_vdec,
46
47 nv_clk_src_dom6,
48
49 nv_clk_src_max,
50};
51
52struct nouveau_cstate {
53 struct list_head head;
54 u8 voltage;
55 u32 domain[nv_clk_src_max];
56};
57
58struct nouveau_pstate {
59 struct list_head head;
60 struct list_head list; /* c-states */
61 struct nouveau_cstate base;
62 u8 pstate;
63 u8 fanspeed;
64};
65
66struct nouveau_clock {
67 struct nouveau_subdev base;
68
69 struct nouveau_clocks *domains;
70 struct nouveau_pstate bstate;
71
72 struct list_head states;
73 int state_nr;
74
75 struct work_struct work;
76 wait_queue_head_t wait;
77 atomic_t waiting;
78
79 struct nvkm_notify pwrsrc_ntfy;
80 int pwrsrc;
81 int pstate; /* current */
82 int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
83 int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
84 int astate; /* perfmon adjustment (base) */
85 int tstate; /* thermal adjustment (max-) */
86 int dstate; /* display adjustment (min+) */
87
88 bool allow_reclock;
89
90 int (*read)(struct nouveau_clock *, enum nv_clk_src);
91 int (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
92 int (*prog)(struct nouveau_clock *);
93 void (*tidy)(struct nouveau_clock *);
94
95 /*XXX: die, these are here *only* to support the completely
96 * bat-shit insane what-was-nouveau_hw.c code
97 */
98 int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
99 int clk, struct nouveau_pll_vals *pv);
100 int (*pll_prog)(struct nouveau_clock *, u32 reg1,
101 struct nouveau_pll_vals *pv);
102};
103
104static inline struct nouveau_clock *
105nouveau_clock(void *obj)
106{
107 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLOCK);
108}
109
110struct nouveau_clocks {
111 enum nv_clk_src name;
112 u8 bios; /* 0xff for none */
113#define NVKM_CLK_DOM_FLAG_CORE 0x01
114 u8 flags;
115 const char *mname;
116 int mdiv;
117};
118
119#define nouveau_clock_create(p,e,o,i,r,s,n,d) \
120 nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
121 (void **)d)
122#define nouveau_clock_destroy(p) ({ \
123 struct nouveau_clock *clk = (p); \
124 _nouveau_clock_dtor(nv_object(clk)); \
125})
126#define nouveau_clock_init(p) ({ \
127 struct nouveau_clock *clk = (p); \
128 _nouveau_clock_init(nv_object(clk)); \
129})
130#define nouveau_clock_fini(p,s) ({ \
131 struct nouveau_clock *clk = (p); \
132 _nouveau_clock_fini(nv_object(clk), (s)); \
133})
134
135int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
136 struct nouveau_oclass *,
137 struct nouveau_clocks *, struct nouveau_pstate *,
138 int, bool, int, void **);
139void _nouveau_clock_dtor(struct nouveau_object *);
140int _nouveau_clock_init(struct nouveau_object *);
141int _nouveau_clock_fini(struct nouveau_object *, bool);
142
143extern struct nouveau_oclass nv04_clock_oclass;
144extern struct nouveau_oclass nv40_clock_oclass;
145extern struct nouveau_oclass *nv50_clock_oclass;
146extern struct nouveau_oclass *nv84_clock_oclass;
147extern struct nouveau_oclass *nvaa_clock_oclass;
148extern struct nouveau_oclass nva3_clock_oclass;
149extern struct nouveau_oclass nvc0_clock_oclass;
150extern struct nouveau_oclass nve0_clock_oclass;
151extern struct nouveau_oclass gk20a_clock_oclass;
152
153int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
154int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
155 int clk, struct nouveau_pll_vals *);
156int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
157 struct nouveau_pll_vals *);
158int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
159 int clk, struct nouveau_pll_vals *);
160
161int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
162int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait);
163int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
164int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
165
166#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index f74f9cbbf3d8..f9589e8935d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -209,7 +209,7 @@ static const u64 disable_map[] = {
209 [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, 209 [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE,
210 [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, 210 [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE,
211 [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, 211 [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE,
212 [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE, 212 [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE,
213 [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, 213 [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE,
214 [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, 214 [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE,
215 [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, 215 [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
index e34101a3490e..7a7632e65c77 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
@@ -28,7 +28,7 @@
28#include <nvif/class.h> 28#include <nvif/class.h>
29#include <nvif/ioctl.h> 29#include <nvif/ioctl.h>
30 30
31#include <subdev/clock.h> 31#include <subdev/clk.h>
32 32
33#include "priv.h" 33#include "priv.h"
34 34
@@ -39,7 +39,7 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object,
39 union { 39 union {
40 struct nvif_control_pstate_info_v0 v0; 40 struct nvif_control_pstate_info_v0 v0;
41 } *args = data; 41 } *args = data;
42 struct nouveau_clock *clk = nouveau_clock(object); 42 struct nouveau_clk *clk = nouveau_clk(object);
43 int ret; 43 int ret;
44 44
45 nv_ioctl(object, "control pstate info size %d\n", size); 45 nv_ioctl(object, "control pstate info size %d\n", size);
@@ -73,8 +73,8 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object,
73 union { 73 union {
74 struct nvif_control_pstate_attr_v0 v0; 74 struct nvif_control_pstate_attr_v0 v0;
75 } *args = data; 75 } *args = data;
76 struct nouveau_clock *clk = nouveau_clock(object); 76 struct nouveau_clk *clk = nouveau_clk(object);
77 struct nouveau_clocks *domain; 77 struct nouveau_domain *domain;
78 struct nouveau_pstate *pstate; 78 struct nouveau_pstate *pstate;
79 struct nouveau_cstate *cstate; 79 struct nouveau_cstate *cstate;
80 int i = 0, j = -1; 80 int i = 0, j = -1;
@@ -147,7 +147,7 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object,
147 union { 147 union {
148 struct nvif_control_pstate_user_v0 v0; 148 struct nvif_control_pstate_user_v0 v0;
149 } *args = data; 149 } *args = data;
150 struct nouveau_clock *clk = nouveau_clock(object); 150 struct nouveau_clk *clk = nouveau_clk(object);
151 int ret; 151 int ret;
152 152
153 nv_ioctl(object, "control pstate user size %d\n", size); 153 nv_ioctl(object, "control pstate user size %d\n", size);
@@ -161,10 +161,10 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object,
161 return ret; 161 return ret;
162 162
163 if (args->v0.pwrsrc >= 0) { 163 if (args->v0.pwrsrc >= 0) {
164 ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc); 164 ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
165 } else { 165 } else {
166 ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0); 166 ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0);
167 ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1); 167 ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1);
168 } 168 }
169 169
170 return ret; 170 return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 4e74a3376de8..e453a52135d7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -27,7 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/fuse.h> 29#include <subdev/fuse.h>
30#include <subdev/clock.h> 30#include <subdev/clk.h>
31#include <subdev/therm.h> 31#include <subdev/therm.h>
32#include <subdev/mxm.h> 32#include <subdev/mxm.h>
33#include <subdev/devinit.h> 33#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ gm100_identify(struct nouveau_device *device)
64 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 64 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
65 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; 65 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; 66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
67 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 67 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
68 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; 68 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
@@ -106,7 +106,7 @@ gm100_identify(struct nouveau_device *device)
106 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; 106 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
107#if 0 107#if 0
108 /* looks to be some non-trivial changes */ 108 /* looks to be some non-trivial changes */
109 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 109 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
110 /* priv ring says no to 0x10eb14 writes */ 110 /* priv ring says no to 0x10eb14 writes */
111 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; 111 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
112#endif 112#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 573b55f5c2f9..dff51984ea94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -25,7 +25,7 @@
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bus.h> 26#include <subdev/bus.h>
27#include <subdev/i2c.h> 27#include <subdev/i2c.h>
28#include <subdev/clock.h> 28#include <subdev/clk.h>
29#include <subdev/devinit.h> 29#include <subdev/devinit.h>
30#include <subdev/mc.h> 30#include <subdev/mc.h>
31#include <subdev/timer.h> 31#include <subdev/timer.h>
@@ -48,7 +48,7 @@ nv04_identify(struct nouveau_device *device)
48 device->cname = "NV04"; 48 device->cname = "NV04";
49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 50 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 51 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
52 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; 52 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -66,7 +66,7 @@ nv04_identify(struct nouveau_device *device)
66 device->cname = "NV05"; 66 device->cname = "NV05";
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 68 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 69 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 183a85a6204e..af63f5b95f01 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -26,7 +26,7 @@
26#include <subdev/bus.h> 26#include <subdev/bus.h>
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clk.h>
30#include <subdev/devinit.h> 30#include <subdev/devinit.h>
31#include <subdev/mc.h> 31#include <subdev/mc.h>
32#include <subdev/timer.h> 32#include <subdev/timer.h>
@@ -50,7 +50,7 @@ nv10_identify(struct nouveau_device *device)
50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
51 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 51 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
52 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 52 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 53 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
54 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 54 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -67,7 +67,7 @@ nv10_identify(struct nouveau_device *device)
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 70 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
71 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -86,7 +86,7 @@ nv10_identify(struct nouveau_device *device)
86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 90 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -105,7 +105,7 @@ nv10_identify(struct nouveau_device *device)
105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
108 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 108 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
109 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 109 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -124,7 +124,7 @@ nv10_identify(struct nouveau_device *device)
124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 127 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
128 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -143,7 +143,7 @@ nv10_identify(struct nouveau_device *device)
143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
145 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 145 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
146 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 146 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
147 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 147 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -162,7 +162,7 @@ nv10_identify(struct nouveau_device *device)
162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
164 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 164 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 165 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
166 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -181,7 +181,7 @@ nv10_identify(struct nouveau_device *device)
181 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 181 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
182 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 182 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
183 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 183 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
184 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 184 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
185 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index aa564c68a920..eddeb126c7ec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -26,7 +26,7 @@
26#include <subdev/bus.h> 26#include <subdev/bus.h>
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clk.h>
30#include <subdev/therm.h> 30#include <subdev/therm.h>
31#include <subdev/devinit.h> 31#include <subdev/devinit.h>
32#include <subdev/mc.h> 32#include <subdev/mc.h>
@@ -51,7 +51,7 @@ nv20_identify(struct nouveau_device *device)
51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@ nv20_identify(struct nouveau_device *device)
70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@ nv20_identify(struct nouveau_device *device)
89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -108,7 +108,7 @@ nv20_identify(struct nouveau_device *device)
108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
109 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 109 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 110 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 111 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
112 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 112 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 11bd31da82ab..6fe2d130a2ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -26,7 +26,7 @@
26#include <subdev/bus.h> 26#include <subdev/bus.h>
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clk.h>
30#include <subdev/devinit.h> 30#include <subdev/devinit.h>
31#include <subdev/mc.h> 31#include <subdev/mc.h>
32#include <subdev/timer.h> 32#include <subdev/timer.h>
@@ -51,7 +51,7 @@ nv30_identify(struct nouveau_device *device)
51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@ nv30_identify(struct nouveau_device *device)
70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@ nv30_identify(struct nouveau_device *device)
89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -109,7 +109,7 @@ nv30_identify(struct nouveau_device *device)
109 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 109 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
110 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 110 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
111 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 111 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
112 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 112 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
113 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; 113 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -129,7 +129,7 @@ nv30_identify(struct nouveau_device *device)
129 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 129 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
131 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 131 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
132 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 132 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
133 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 133 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index e96c223cb797..d85edd87cec8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -27,7 +27,7 @@
27#include <subdev/vm.h> 27#include <subdev/vm.h>
28#include <subdev/gpio.h> 28#include <subdev/gpio.h>
29#include <subdev/i2c.h> 29#include <subdev/i2c.h>
30#include <subdev/clock.h> 30#include <subdev/clk.h>
31#include <subdev/therm.h> 31#include <subdev/therm.h>
32#include <subdev/devinit.h> 32#include <subdev/devinit.h>
33#include <subdev/mc.h> 33#include <subdev/mc.h>
@@ -55,7 +55,7 @@ nv40_identify(struct nouveau_device *device)
55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
56 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 56 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
57 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 57 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
58 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 58 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
60 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 60 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -78,7 +78,7 @@ nv40_identify(struct nouveau_device *device)
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 79 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 80 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 81 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 83 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -101,7 +101,7 @@ nv40_identify(struct nouveau_device *device)
101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
102 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 102 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
103 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 103 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
104 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 104 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -124,7 +124,7 @@ nv40_identify(struct nouveau_device *device)
124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 127 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
129 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 129 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -147,7 +147,7 @@ nv40_identify(struct nouveau_device *device)
147 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 147 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
149 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 149 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
150 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 150 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
152 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 152 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -170,7 +170,7 @@ nv40_identify(struct nouveau_device *device)
170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
171 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 171 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
172 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 172 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 173 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
175 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 175 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -193,7 +193,7 @@ nv40_identify(struct nouveau_device *device)
193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
194 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 194 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
195 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 195 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
196 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 196 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
198 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 198 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -216,7 +216,7 @@ nv40_identify(struct nouveau_device *device)
216 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 216 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
217 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 217 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
218 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 218 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
219 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 219 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
221 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 221 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -239,7 +239,7 @@ nv40_identify(struct nouveau_device *device)
239 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 239 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
240 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 240 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
241 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 241 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
242 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 242 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
244 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -262,7 +262,7 @@ nv40_identify(struct nouveau_device *device)
262 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 262 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
263 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 263 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
264 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 264 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
265 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 265 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
267 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 267 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -285,7 +285,7 @@ nv40_identify(struct nouveau_device *device)
285 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 285 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
286 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 286 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
287 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 287 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
288 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 288 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -308,7 +308,7 @@ nv40_identify(struct nouveau_device *device)
308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
309 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 309 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
310 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 310 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 311 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
314 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; 314 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -331,7 +331,7 @@ nv40_identify(struct nouveau_device *device)
331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
332 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 332 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
333 device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; 333 device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 334 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
337 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; 337 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -354,7 +354,7 @@ nv40_identify(struct nouveau_device *device)
354 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 354 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
355 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 355 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
356 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 356 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 357 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
360 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; 360 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -377,7 +377,7 @@ nv40_identify(struct nouveau_device *device)
377 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 377 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
378 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 378 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
379 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 379 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 380 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
383 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; 383 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -400,7 +400,7 @@ nv40_identify(struct nouveau_device *device)
400 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 400 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
401 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 401 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
402 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 402 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 403 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
406 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; 406 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 96f568d1321b..ccf82ab16881 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -27,7 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/fuse.h> 29#include <subdev/fuse.h>
30#include <subdev/clock.h> 30#include <subdev/clk.h>
31#include <subdev/therm.h> 31#include <subdev/therm.h>
32#include <subdev/mxm.h> 32#include <subdev/mxm.h>
33#include <subdev/devinit.h> 33#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nv50_identify(struct nouveau_device *device)
64 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 64 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
65 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 65 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
66 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 66 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
67 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; 67 device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
68 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; 68 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
@@ -90,7 +90,7 @@ nv50_identify(struct nouveau_device *device)
90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 91 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
92 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 92 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
93 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 93 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
94 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 94 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
95 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 95 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
96 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 96 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -119,7 +119,7 @@ nv50_identify(struct nouveau_device *device)
119 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 119 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
120 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 120 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
121 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 121 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
122 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 122 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
123 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 123 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
124 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 124 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
125 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 125 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -148,7 +148,7 @@ nv50_identify(struct nouveau_device *device)
148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
149 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 149 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
150 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 150 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
151 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 151 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
152 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 152 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
153 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 153 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
154 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 154 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -177,7 +177,7 @@ nv50_identify(struct nouveau_device *device)
177 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 177 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
178 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 178 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
179 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 179 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
180 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 180 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
181 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 181 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
182 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 182 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
183 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 183 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -206,7 +206,7 @@ nv50_identify(struct nouveau_device *device)
206 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 206 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
207 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 207 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
208 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 208 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
209 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 209 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
210 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 210 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
211 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 211 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
212 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 212 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -235,7 +235,7 @@ nv50_identify(struct nouveau_device *device)
235 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 235 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
236 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 236 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
237 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 237 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
238 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 238 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
239 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 239 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
240 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 240 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
241 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; 241 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -264,7 +264,7 @@ nv50_identify(struct nouveau_device *device)
264 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 264 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
265 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 265 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
266 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 266 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
267 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 267 device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
268 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 268 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
269 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 269 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
270 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; 270 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -293,7 +293,7 @@ nv50_identify(struct nouveau_device *device)
293 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 293 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
294 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 294 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
295 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 295 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
296 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; 296 device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
297 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 297 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
298 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 298 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
299 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; 299 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device)
322 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 322 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
323 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 323 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
324 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 324 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
325 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; 325 device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
326 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 326 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
327 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 327 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
328 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; 328 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -351,7 +351,7 @@ nv50_identify(struct nouveau_device *device)
351 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 351 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
352 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 352 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
353 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 353 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
354 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 354 device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
355 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 355 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
356 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 356 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
357 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; 357 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -382,7 +382,7 @@ nv50_identify(struct nouveau_device *device)
382 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 382 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
383 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 383 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
384 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 384 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
385 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 385 device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
386 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 386 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
387 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 387 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
388 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; 388 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -412,7 +412,7 @@ nv50_identify(struct nouveau_device *device)
412 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 412 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
413 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 413 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
414 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 414 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
415 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 415 device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
416 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 416 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
417 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 417 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
418 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; 418 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -442,7 +442,7 @@ nv50_identify(struct nouveau_device *device)
442 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 442 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
443 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 443 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
444 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; 444 device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
445 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 445 device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
446 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 446 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
447 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 447 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
448 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; 448 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 72a40f95d048..ff5b2ab674bd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -27,7 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/fuse.h> 29#include <subdev/fuse.h>
30#include <subdev/clock.h> 30#include <subdev/clk.h>
31#include <subdev/therm.h> 31#include <subdev/therm.h>
32#include <subdev/mxm.h> 32#include <subdev/mxm.h>
33#include <subdev/devinit.h> 33#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nvc0_identify(struct nouveau_device *device)
64 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 64 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
65 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 65 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
67 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 67 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
68 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 68 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -97,7 +97,7 @@ nvc0_identify(struct nouveau_device *device)
97 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 97 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
98 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 98 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
99 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 99 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
100 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 100 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
101 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 101 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
102 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 102 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
103 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 103 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -130,7 +130,7 @@ nvc0_identify(struct nouveau_device *device)
130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
131 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 131 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
132 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 132 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
133 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 133 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
134 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 134 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
135 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 135 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
136 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 136 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@ nvc0_identify(struct nouveau_device *device)
162 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 162 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
163 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 163 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
164 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 164 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 165 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
166 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 166 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
167 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 167 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
168 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 168 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -195,7 +195,7 @@ nvc0_identify(struct nouveau_device *device)
195 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 195 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
196 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 196 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
197 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 197 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
198 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 198 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
199 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 199 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
200 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 200 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
201 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 201 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -227,7 +227,7 @@ nvc0_identify(struct nouveau_device *device)
227 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 227 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
228 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 228 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
229 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 229 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
230 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 230 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
231 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 231 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
233 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 233 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -259,7 +259,7 @@ nvc0_identify(struct nouveau_device *device)
259 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; 259 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
260 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; 260 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
261 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 261 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
262 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 262 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
263 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 263 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
264 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 264 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
265 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 265 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -292,7 +292,7 @@ nvc0_identify(struct nouveau_device *device)
292 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; 292 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
293 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; 293 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
294 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 294 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
295 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 295 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
296 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 296 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
297 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 297 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
298 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 298 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -324,7 +324,7 @@ nvc0_identify(struct nouveau_device *device)
324 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; 324 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
325 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; 325 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
326 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 326 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
327 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 327 device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
328 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 328 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
329 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 329 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
330 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 330 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index d308aee028f0..7c02ff5b13ed 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -27,7 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/fuse.h> 29#include <subdev/fuse.h>
30#include <subdev/clock.h> 30#include <subdev/clk.h>
31#include <subdev/therm.h> 31#include <subdev/therm.h>
32#include <subdev/mxm.h> 32#include <subdev/mxm.h>
33#include <subdev/devinit.h> 33#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nve0_identify(struct nouveau_device *device)
64 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 64 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
65 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 65 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 66 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
67 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 67 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
68 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 68 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -98,7 +98,7 @@ nve0_identify(struct nouveau_device *device)
98 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 98 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
99 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 99 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
100 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 100 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
101 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 101 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
102 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 102 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
103 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 103 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
104 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 104 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -132,7 +132,7 @@ nve0_identify(struct nouveau_device *device)
132 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 132 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
133 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 133 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
134 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 134 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
135 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 135 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
136 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 136 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
137 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 137 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
138 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 138 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@ nve0_identify(struct nouveau_device *device)
162 break; 162 break;
163 case 0xea: 163 case 0xea:
164 device->cname = "GK20A"; 164 device->cname = "GK20A";
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; 165 device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
166 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; 166 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
167 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 167 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
168 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 168 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -188,7 +188,7 @@ nve0_identify(struct nouveau_device *device)
188 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 188 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
189 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 189 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
190 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 190 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
191 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 191 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
192 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 192 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
193 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 193 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
194 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 194 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -222,7 +222,7 @@ nve0_identify(struct nouveau_device *device)
222 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 222 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
223 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; 223 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
224 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 224 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
225 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 225 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
226 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 226 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
227 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 227 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
228 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 228 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -256,7 +256,7 @@ nve0_identify(struct nouveau_device *device)
256 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 256 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
257 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 257 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
258 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 258 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
259 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 259 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
260 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 260 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
261 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 261 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
262 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 262 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -289,7 +289,7 @@ nve0_identify(struct nouveau_device *device)
289 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; 289 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
290 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; 290 device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
291 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; 291 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
292 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 292 device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
293 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 293 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
294 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 294 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
295 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; 295 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
index 63013812f7c9..3a9359e29179 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
@@ -28,7 +28,7 @@
28#include <nvif/class.h> 28#include <nvif/class.h>
29#include <nvif/ioctl.h> 29#include <nvif/ioctl.h>
30 30
31#include <subdev/clock.h> 31#include <subdev/clk.h>
32 32
33#include "priv.h" 33#include "priv.h"
34 34
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 10ef07cf3f91..39f800a6f1e4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -1,7 +1,7 @@
1include $(src)/nvkm/subdev/bar/Kbuild 1include $(src)/nvkm/subdev/bar/Kbuild
2include $(src)/nvkm/subdev/bios/Kbuild 2include $(src)/nvkm/subdev/bios/Kbuild
3include $(src)/nvkm/subdev/bus/Kbuild 3include $(src)/nvkm/subdev/bus/Kbuild
4include $(src)/nvkm/subdev/clock/Kbuild 4include $(src)/nvkm/subdev/clk/Kbuild
5include $(src)/nvkm/subdev/devinit/Kbuild 5include $(src)/nvkm/subdev/devinit/Kbuild
6include $(src)/nvkm/subdev/fb/Kbuild 6include $(src)/nvkm/subdev/fb/Kbuild
7include $(src)/nvkm/subdev/fuse/Kbuild 7include $(src)/nvkm/subdev/fuse/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
new file mode 100644
index 000000000000..94d10a9e637a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
@@ -0,0 +1,12 @@
1nvkm-y += nvkm/subdev/clk/base.o
2nvkm-y += nvkm/subdev/clk/nv04.o
3nvkm-y += nvkm/subdev/clk/nv40.o
4nvkm-y += nvkm/subdev/clk/nv50.o
5nvkm-y += nvkm/subdev/clk/nv84.o
6nvkm-y += nvkm/subdev/clk/nva3.o
7nvkm-y += nvkm/subdev/clk/nvaa.o
8nvkm-y += nvkm/subdev/clk/nvc0.o
9nvkm-y += nvkm/subdev/clk/nve0.o
10nvkm-y += nvkm/subdev/clk/gk20a.o
11nvkm-y += nvkm/subdev/clk/pllnv04.o
12nvkm-y += nvkm/subdev/clk/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index bc095b470121..a0c21ec3f61d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -24,7 +24,7 @@
24 24
25#include <core/option.h> 25#include <core/option.h>
26 26
27#include <subdev/clock.h> 27#include <subdev/clk.h>
28#include <subdev/therm.h> 28#include <subdev/therm.h>
29#include <subdev/volt.h> 29#include <subdev/volt.h>
30#include <subdev/fb.h> 30#include <subdev/fb.h>
@@ -38,7 +38,7 @@
38 * misc 38 * misc
39 *****************************************************************************/ 39 *****************************************************************************/
40static u32 40static u32
41nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust, 41nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
42 u8 pstate, u8 domain, u32 input) 42 u8 pstate, u8 domain, u32 input)
43{ 43{
44 struct nouveau_bios *bios = nouveau_bios(clk); 44 struct nouveau_bios *bios = nouveau_bios(clk);
@@ -76,7 +76,7 @@ nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
76 * C-States 76 * C-States
77 *****************************************************************************/ 77 *****************************************************************************/
78static int 78static int
79nouveau_cstate_prog(struct nouveau_clock *clk, 79nouveau_cstate_prog(struct nouveau_clk *clk,
80 struct nouveau_pstate *pstate, int cstatei) 80 struct nouveau_pstate *pstate, int cstatei)
81{ 81{
82 struct nouveau_therm *ptherm = nouveau_therm(clk); 82 struct nouveau_therm *ptherm = nouveau_therm(clk);
@@ -135,11 +135,11 @@ nouveau_cstate_del(struct nouveau_cstate *cstate)
135} 135}
136 136
137static int 137static int
138nouveau_cstate_new(struct nouveau_clock *clk, int idx, 138nouveau_cstate_new(struct nouveau_clk *clk, int idx,
139 struct nouveau_pstate *pstate) 139 struct nouveau_pstate *pstate)
140{ 140{
141 struct nouveau_bios *bios = nouveau_bios(clk); 141 struct nouveau_bios *bios = nouveau_bios(clk);
142 struct nouveau_clocks *domain = clk->domains; 142 struct nouveau_domain *domain = clk->domains;
143 struct nouveau_cstate *cstate = NULL; 143 struct nouveau_cstate *cstate = NULL;
144 struct nvbios_cstepX cstepX; 144 struct nvbios_cstepX cstepX;
145 u8 ver, hdr; 145 u8 ver, hdr;
@@ -158,7 +158,7 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx,
158 158
159 while (domain && domain->name != nv_clk_src_max) { 159 while (domain && domain->name != nv_clk_src_max) {
160 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { 160 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
161 u32 freq = nouveau_clock_adjust(clk, true, 161 u32 freq = nouveau_clk_adjust(clk, true,
162 pstate->pstate, 162 pstate->pstate,
163 domain->bios, 163 domain->bios,
164 cstepX.freq); 164 cstepX.freq);
@@ -175,7 +175,7 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx,
175 * P-States 175 * P-States
176 *****************************************************************************/ 176 *****************************************************************************/
177static int 177static int
178nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) 178nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
179{ 179{
180 struct nouveau_fb *pfb = nouveau_fb(clk); 180 struct nouveau_fb *pfb = nouveau_fb(clk);
181 struct nouveau_pstate *pstate; 181 struct nouveau_pstate *pstate;
@@ -205,7 +205,7 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
205static void 205static void
206nouveau_pstate_work(struct work_struct *work) 206nouveau_pstate_work(struct work_struct *work)
207{ 207{
208 struct nouveau_clock *clk = container_of(work, typeof(*clk), work); 208 struct nouveau_clk *clk = container_of(work, typeof(*clk), work);
209 int pstate; 209 int pstate;
210 210
211 if (!atomic_xchg(&clk->waiting, 0)) 211 if (!atomic_xchg(&clk->waiting, 0))
@@ -239,7 +239,7 @@ nouveau_pstate_work(struct work_struct *work)
239} 239}
240 240
241static int 241static int
242nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) 242nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
243{ 243{
244 atomic_set(&clk->waiting, 1); 244 atomic_set(&clk->waiting, 1);
245 schedule_work(&clk->work); 245 schedule_work(&clk->work);
@@ -249,9 +249,9 @@ nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
249} 249}
250 250
251static void 251static void
252nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate) 252nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
253{ 253{
254 struct nouveau_clocks *clock = clk->domains - 1; 254 struct nouveau_domain *clock = clk->domains - 1;
255 struct nouveau_cstate *cstate; 255 struct nouveau_cstate *cstate;
256 char info[3][32] = { "", "", "" }; 256 char info[3][32] = { "", "", "" };
257 char name[4] = "--"; 257 char name[4] = "--";
@@ -304,10 +304,10 @@ nouveau_pstate_del(struct nouveau_pstate *pstate)
304} 304}
305 305
306static int 306static int
307nouveau_pstate_new(struct nouveau_clock *clk, int idx) 307nouveau_pstate_new(struct nouveau_clk *clk, int idx)
308{ 308{
309 struct nouveau_bios *bios = nouveau_bios(clk); 309 struct nouveau_bios *bios = nouveau_bios(clk);
310 struct nouveau_clocks *domain = clk->domains - 1; 310 struct nouveau_domain *domain = clk->domains - 1;
311 struct nouveau_pstate *pstate; 311 struct nouveau_pstate *pstate;
312 struct nouveau_cstate *cstate; 312 struct nouveau_cstate *cstate;
313 struct nvbios_cstepE cstepE; 313 struct nvbios_cstepE cstepE;
@@ -346,7 +346,7 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx)
346 continue; 346 continue;
347 347
348 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { 348 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
349 perfS.v40.freq = nouveau_clock_adjust(clk, false, 349 perfS.v40.freq = nouveau_clk_adjust(clk, false,
350 pstate->pstate, 350 pstate->pstate,
351 domain->bios, 351 domain->bios,
352 perfS.v40.freq); 352 perfS.v40.freq);
@@ -373,7 +373,7 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx)
373 * Adjustment triggers 373 * Adjustment triggers
374 *****************************************************************************/ 374 *****************************************************************************/
375static int 375static int
376nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) 376nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
377{ 377{
378 struct nouveau_pstate *pstate; 378 struct nouveau_pstate *pstate;
379 int i = 0; 379 int i = 0;
@@ -397,7 +397,7 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
397} 397}
398 398
399static int 399static int
400nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) 400nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
401{ 401{
402 int ret = 1; 402 int ret = 1;
403 403
@@ -410,7 +410,7 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
410 410
411 ((char *)mode)[arglen] = '\0'; 411 ((char *)mode)[arglen] = '\0';
412 if (!kstrtol(mode, 0, &v)) { 412 if (!kstrtol(mode, 0, &v)) {
413 ret = nouveau_clock_ustate_update(clk, v); 413 ret = nouveau_clk_ustate_update(clk, v);
414 if (ret < 0) 414 if (ret < 0)
415 ret = 1; 415 ret = 1;
416 } 416 }
@@ -421,9 +421,9 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
421} 421}
422 422
423int 423int
424nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr) 424nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr)
425{ 425{
426 int ret = nouveau_clock_ustate_update(clk, req); 426 int ret = nouveau_clk_ustate_update(clk, req);
427 if (ret >= 0) { 427 if (ret >= 0) {
428 if (ret -= 2, pwr) clk->ustate_ac = ret; 428 if (ret -= 2, pwr) clk->ustate_ac = ret;
429 else clk->ustate_dc = ret; 429 else clk->ustate_dc = ret;
@@ -433,7 +433,7 @@ nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
433} 433}
434 434
435int 435int
436nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait) 436nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait)
437{ 437{
438 if (!rel) clk->astate = req; 438 if (!rel) clk->astate = req;
439 if ( rel) clk->astate += rel; 439 if ( rel) clk->astate += rel;
@@ -443,7 +443,7 @@ nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
443} 443}
444 444
445int 445int
446nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel) 446nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel)
447{ 447{
448 if (!rel) clk->tstate = req; 448 if (!rel) clk->tstate = req;
449 if ( rel) clk->tstate += rel; 449 if ( rel) clk->tstate += rel;
@@ -453,7 +453,7 @@ nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
453} 453}
454 454
455int 455int
456nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel) 456nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel)
457{ 457{
458 if (!rel) clk->dstate = req; 458 if (!rel) clk->dstate = req;
459 if ( rel) clk->dstate += rel; 459 if ( rel) clk->dstate += rel;
@@ -463,9 +463,9 @@ nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
463} 463}
464 464
465static int 465static int
466nouveau_clock_pwrsrc(struct nvkm_notify *notify) 466nouveau_clk_pwrsrc(struct nvkm_notify *notify)
467{ 467{
468 struct nouveau_clock *clk = 468 struct nouveau_clk *clk =
469 container_of(notify, typeof(*clk), pwrsrc_ntfy); 469 container_of(notify, typeof(*clk), pwrsrc_ntfy);
470 nouveau_pstate_calc(clk, false); 470 nouveau_pstate_calc(clk, false);
471 return NVKM_NOTIFY_DROP; 471 return NVKM_NOTIFY_DROP;
@@ -476,18 +476,18 @@ nouveau_clock_pwrsrc(struct nvkm_notify *notify)
476 *****************************************************************************/ 476 *****************************************************************************/
477 477
478int 478int
479_nouveau_clock_fini(struct nouveau_object *object, bool suspend) 479_nouveau_clk_fini(struct nouveau_object *object, bool suspend)
480{ 480{
481 struct nouveau_clock *clk = (void *)object; 481 struct nouveau_clk *clk = (void *)object;
482 nvkm_notify_put(&clk->pwrsrc_ntfy); 482 nvkm_notify_put(&clk->pwrsrc_ntfy);
483 return nouveau_subdev_fini(&clk->base, suspend); 483 return nouveau_subdev_fini(&clk->base, suspend);
484} 484}
485 485
486int 486int
487_nouveau_clock_init(struct nouveau_object *object) 487_nouveau_clk_init(struct nouveau_object *object)
488{ 488{
489 struct nouveau_clock *clk = (void *)object; 489 struct nouveau_clk *clk = (void *)object;
490 struct nouveau_clocks *clock = clk->domains; 490 struct nouveau_domain *clock = clk->domains;
491 int ret; 491 int ret;
492 492
493 ret = nouveau_subdev_init(&clk->base); 493 ret = nouveau_subdev_init(&clk->base);
@@ -519,9 +519,9 @@ _nouveau_clock_init(struct nouveau_object *object)
519} 519}
520 520
521void 521void
522_nouveau_clock_dtor(struct nouveau_object *object) 522_nouveau_clk_dtor(struct nouveau_object *object)
523{ 523{
524 struct nouveau_clock *clk = (void *)object; 524 struct nouveau_clk *clk = (void *)object;
525 struct nouveau_pstate *pstate, *temp; 525 struct nouveau_pstate *pstate, *temp;
526 526
527 nvkm_notify_fini(&clk->pwrsrc_ntfy); 527 nvkm_notify_fini(&clk->pwrsrc_ntfy);
@@ -534,16 +534,16 @@ _nouveau_clock_dtor(struct nouveau_object *object)
534} 534}
535 535
536int 536int
537nouveau_clock_create_(struct nouveau_object *parent, 537nouveau_clk_create_(struct nouveau_object *parent,
538 struct nouveau_object *engine, 538 struct nouveau_object *engine,
539 struct nouveau_oclass *oclass, 539 struct nouveau_oclass *oclass,
540 struct nouveau_clocks *clocks, 540 struct nouveau_domain *clocks,
541 struct nouveau_pstate *pstates, int nb_pstates, 541 struct nouveau_pstate *pstates, int nb_pstates,
542 bool allow_reclock, 542 bool allow_reclock,
543 int length, void **object) 543 int length, void **object)
544{ 544{
545 struct nouveau_device *device = nv_device(parent); 545 struct nouveau_device *device = nv_device(parent);
546 struct nouveau_clock *clk; 546 struct nouveau_clk *clk;
547 int ret, idx, arglen; 547 int ret, idx, arglen;
548 const char *mode; 548 const char *mode;
549 549
@@ -576,24 +576,24 @@ nouveau_clock_create_(struct nouveau_object *parent,
576 576
577 clk->allow_reclock = allow_reclock; 577 clk->allow_reclock = allow_reclock;
578 578
579 ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true, 579 ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true,
580 NULL, 0, 0, &clk->pwrsrc_ntfy); 580 NULL, 0, 0, &clk->pwrsrc_ntfy);
581 if (ret) 581 if (ret)
582 return ret; 582 return ret;
583 583
584 mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); 584 mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
585 if (mode) { 585 if (mode) {
586 clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); 586 clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
587 clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); 587 clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
588 } 588 }
589 589
590 mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); 590 mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
591 if (mode) 591 if (mode)
592 clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); 592 clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
593 593
594 mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); 594 mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
595 if (mode) 595 if (mode)
596 clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); 596 clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
597 597
598 598
599 return 0; 599 return 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
index fb4fad374bdd..4529ba20af5e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -87,7 +87,7 @@
87#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 87#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
88 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 88 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
89 89
90#include <subdev/clock.h> 90#include <subdev/clk.h>
91#include <subdev/timer.h> 91#include <subdev/timer.h>
92 92
93#ifdef __KERNEL__ 93#ifdef __KERNEL__
@@ -116,16 +116,16 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
116 .min_pl = 1, .max_pl = 32, 116 .min_pl = 1, .max_pl = 32,
117}; 117};
118 118
119struct gk20a_clock_priv { 119struct gk20a_clk_priv {
120 struct nouveau_clock base; 120 struct nouveau_clk base;
121 const struct gk20a_clk_pllg_params *params; 121 const struct gk20a_clk_pllg_params *params;
122 u32 m, n, pl; 122 u32 m, n, pl;
123 u32 parent_rate; 123 u32 parent_rate;
124}; 124};
125#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) 125#define to_gk20a_clk(base) container_of(base, struct gk20a_clk_priv, base)
126 126
127static void 127static void
128gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) 128gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv)
129{ 129{
130 u32 val; 130 u32 val;
131 131
@@ -136,7 +136,7 @@ gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
136} 136}
137 137
138static u32 138static u32
139gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) 139gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv)
140{ 140{
141 u32 rate; 141 u32 rate;
142 u32 divider; 142 u32 divider;
@@ -149,7 +149,7 @@ gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
149} 149}
150 150
151static int 151static int
152gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) 152gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate)
153{ 153{
154 u32 target_clk_f, ref_clk_f, target_freq; 154 u32 target_clk_f, ref_clk_f, target_freq;
155 u32 min_vco_f, max_vco_f; 155 u32 min_vco_f, max_vco_f;
@@ -265,7 +265,7 @@ found_match:
265} 265}
266 266
267static int 267static int
268gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) 268gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n)
269{ 269{
270 u32 val; 270 u32 val;
271 int ramp_timeout; 271 int ramp_timeout;
@@ -322,21 +322,21 @@ gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
322} 322}
323 323
324static void 324static void
325_gk20a_pllg_enable(struct gk20a_clock_priv *priv) 325_gk20a_pllg_enable(struct gk20a_clk_priv *priv)
326{ 326{
327 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 327 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
328 nv_rd32(priv, GPCPLL_CFG); 328 nv_rd32(priv, GPCPLL_CFG);
329} 329}
330 330
331static void 331static void
332_gk20a_pllg_disable(struct gk20a_clock_priv *priv) 332_gk20a_pllg_disable(struct gk20a_clk_priv *priv)
333{ 333{
334 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 334 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
335 nv_rd32(priv, GPCPLL_CFG); 335 nv_rd32(priv, GPCPLL_CFG);
336} 336}
337 337
338static int 338static int
339_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) 339_gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide)
340{ 340{
341 u32 val, cfg; 341 u32 val, cfg;
342 u32 m_old, pl_old, n_lo; 342 u32 m_old, pl_old, n_lo;
@@ -422,7 +422,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
422} 422}
423 423
424static int 424static int
425gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) 425gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv)
426{ 426{
427 int err; 427 int err;
428 428
@@ -434,7 +434,7 @@ gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
434} 434}
435 435
436static void 436static void
437gk20a_pllg_disable(struct gk20a_clock_priv *priv) 437gk20a_pllg_disable(struct gk20a_clk_priv *priv)
438{ 438{
439 u32 val; 439 u32 val;
440 440
@@ -458,7 +458,7 @@ gk20a_pllg_disable(struct gk20a_clock_priv *priv)
458 458
459#define GK20A_CLK_GPC_MDIV 1000 459#define GK20A_CLK_GPC_MDIV 1000
460 460
461static struct nouveau_clocks 461static struct nouveau_domain
462gk20a_domains[] = { 462gk20a_domains[] = {
463 { nv_clk_src_crystal, 0xff }, 463 { nv_clk_src_crystal, 0xff },
464 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 464 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
@@ -560,9 +560,9 @@ gk20a_pstates[] = {
560}; 560};
561 561
562static int 562static int
563gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 563gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
564{ 564{
565 struct gk20a_clock_priv *priv = (void *)clk; 565 struct gk20a_clk_priv *priv = (void *)clk;
566 566
567 switch (src) { 567 switch (src) {
568 case nv_clk_src_crystal: 568 case nv_clk_src_crystal:
@@ -577,34 +577,34 @@ gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
577} 577}
578 578
579static int 579static int
580gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 580gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
581{ 581{
582 struct gk20a_clock_priv *priv = (void *)clk; 582 struct gk20a_clk_priv *priv = (void *)clk;
583 583
584 return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * 584 return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
585 GK20A_CLK_GPC_MDIV); 585 GK20A_CLK_GPC_MDIV);
586} 586}
587 587
588static int 588static int
589gk20a_clock_prog(struct nouveau_clock *clk) 589gk20a_clk_prog(struct nouveau_clk *clk)
590{ 590{
591 struct gk20a_clock_priv *priv = (void *)clk; 591 struct gk20a_clk_priv *priv = (void *)clk;
592 592
593 return gk20a_pllg_program_mnp(priv); 593 return gk20a_pllg_program_mnp(priv);
594} 594}
595 595
596static void 596static void
597gk20a_clock_tidy(struct nouveau_clock *clk) 597gk20a_clk_tidy(struct nouveau_clk *clk)
598{ 598{
599} 599}
600 600
601static int 601static int
602gk20a_clock_fini(struct nouveau_object *object, bool suspend) 602gk20a_clk_fini(struct nouveau_object *object, bool suspend)
603{ 603{
604 struct gk20a_clock_priv *priv = (void *)object; 604 struct gk20a_clk_priv *priv = (void *)object;
605 int ret; 605 int ret;
606 606
607 ret = nouveau_clock_fini(&priv->base, false); 607 ret = nouveau_clk_fini(&priv->base, false);
608 608
609 gk20a_pllg_disable(priv); 609 gk20a_pllg_disable(priv);
610 610
@@ -612,18 +612,18 @@ gk20a_clock_fini(struct nouveau_object *object, bool suspend)
612} 612}
613 613
614static int 614static int
615gk20a_clock_init(struct nouveau_object *object) 615gk20a_clk_init(struct nouveau_object *object)
616{ 616{
617 struct gk20a_clock_priv *priv = (void *)object; 617 struct gk20a_clk_priv *priv = (void *)object;
618 int ret; 618 int ret;
619 619
620 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 620 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
621 621
622 ret = nouveau_clock_init(&priv->base); 622 ret = nouveau_clk_init(&priv->base);
623 if (ret) 623 if (ret)
624 return ret; 624 return ret;
625 625
626 ret = gk20a_clock_prog(&priv->base); 626 ret = gk20a_clk_prog(&priv->base);
627 if (ret) { 627 if (ret) {
628 nv_error(priv, "cannot initialize clock\n"); 628 nv_error(priv, "cannot initialize clock\n");
629 return ret; 629 return ret;
@@ -633,11 +633,11 @@ gk20a_clock_init(struct nouveau_object *object)
633} 633}
634 634
635static int 635static int
636gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 636gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
637 struct nouveau_oclass *oclass, void *data, u32 size, 637 struct nouveau_oclass *oclass, void *data, u32 size,
638 struct nouveau_object **pobject) 638 struct nouveau_object **pobject)
639{ 639{
640 struct gk20a_clock_priv *priv; 640 struct gk20a_clk_priv *priv;
641 struct nouveau_platform_device *plat; 641 struct nouveau_platform_device *plat;
642 int ret; 642 int ret;
643 int i; 643 int i;
@@ -648,7 +648,7 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
648 gk20a_pstates[i].pstate = i + 1; 648 gk20a_pstates[i].pstate = i + 1;
649 } 649 }
650 650
651 ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, 651 ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains,
652 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); 652 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
653 *pobject = nv_object(priv); 653 *pobject = nv_object(priv);
654 if (ret) 654 if (ret)
@@ -660,21 +660,21 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
660 priv->parent_rate = clk_get_rate(plat->gpu->clk); 660 priv->parent_rate = clk_get_rate(plat->gpu->clk);
661 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); 661 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
662 662
663 priv->base.read = gk20a_clock_read; 663 priv->base.read = gk20a_clk_read;
664 priv->base.calc = gk20a_clock_calc; 664 priv->base.calc = gk20a_clk_calc;
665 priv->base.prog = gk20a_clock_prog; 665 priv->base.prog = gk20a_clk_prog;
666 priv->base.tidy = gk20a_clock_tidy; 666 priv->base.tidy = gk20a_clk_tidy;
667 667
668 return 0; 668 return 0;
669} 669}
670 670
671struct nouveau_oclass 671struct nouveau_oclass
672gk20a_clock_oclass = { 672gk20a_clk_oclass = {
673 .handle = NV_SUBDEV(CLOCK, 0xea), 673 .handle = NV_SUBDEV(CLK, 0xea),
674 .ofuncs = &(struct nouveau_ofuncs) { 674 .ofuncs = &(struct nouveau_ofuncs) {
675 .ctor = gk20a_clock_ctor, 675 .ctor = gk20a_clk_ctor,
676 .dtor = _nouveau_subdev_dtor, 676 .dtor = _nouveau_subdev_dtor,
677 .init = gk20a_clock_init, 677 .init = gk20a_clk_init,
678 .fini = gk20a_clock_fini, 678 .fini = gk20a_clk_fini,
679 }, 679 },
680}; 680};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
index 4c48232686be..de68f2f53204 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
@@ -24,17 +24,17 @@
24 24
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bios/pll.h> 26#include <subdev/bios/pll.h>
27#include <subdev/clock.h> 27#include <subdev/clk.h>
28#include <subdev/devinit/nv04.h> 28#include <subdev/devinit/nv04.h>
29 29
30#include "pll.h" 30#include "pll.h"
31 31
32struct nv04_clock_priv { 32struct nv04_clk_priv {
33 struct nouveau_clock base; 33 struct nouveau_clk base;
34}; 34};
35 35
36int 36int
37nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, 37nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
38 int clk, struct nouveau_pll_vals *pv) 38 int clk, struct nouveau_pll_vals *pv)
39{ 39{
40 int N1, M1, N2, M2, P; 40 int N1, M1, N2, M2, P;
@@ -51,7 +51,7 @@ nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
51} 51}
52 52
53int 53int
54nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, 54nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
55 struct nouveau_pll_vals *pv) 55 struct nouveau_pll_vals *pv)
56{ 56{
57 struct nouveau_devinit *devinit = nouveau_devinit(clk); 57 struct nouveau_devinit *devinit = nouveau_devinit(clk);
@@ -69,37 +69,37 @@ nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
69 return 0; 69 return 0;
70} 70}
71 71
72static struct nouveau_clocks 72static struct nouveau_domain
73nv04_domain[] = { 73nv04_domain[] = {
74 { nv_clk_src_max } 74 { nv_clk_src_max }
75}; 75};
76 76
77static int 77static int
78nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 78nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
79 struct nouveau_oclass *oclass, void *data, u32 size, 79 struct nouveau_oclass *oclass, void *data, u32 size,
80 struct nouveau_object **pobject) 80 struct nouveau_object **pobject)
81{ 81{
82 struct nv04_clock_priv *priv; 82 struct nv04_clk_priv *priv;
83 int ret; 83 int ret;
84 84
85 ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0, 85 ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0,
86 false, &priv); 86 false, &priv);
87 *pobject = nv_object(priv); 87 *pobject = nv_object(priv);
88 if (ret) 88 if (ret)
89 return ret; 89 return ret;
90 90
91 priv->base.pll_calc = nv04_clock_pll_calc; 91 priv->base.pll_calc = nv04_clk_pll_calc;
92 priv->base.pll_prog = nv04_clock_pll_prog; 92 priv->base.pll_prog = nv04_clk_pll_prog;
93 return 0; 93 return 0;
94} 94}
95 95
96struct nouveau_oclass 96struct nouveau_oclass
97nv04_clock_oclass = { 97nv04_clk_oclass = {
98 .handle = NV_SUBDEV(CLOCK, 0x04), 98 .handle = NV_SUBDEV(CLK, 0x04),
99 .ofuncs = &(struct nouveau_ofuncs) { 99 .ofuncs = &(struct nouveau_ofuncs) {
100 .ctor = nv04_clock_ctor, 100 .ctor = nv04_clk_ctor,
101 .dtor = _nouveau_clock_dtor, 101 .dtor = _nouveau_clk_dtor,
102 .init = _nouveau_clock_init, 102 .init = _nouveau_clk_init,
103 .fini = _nouveau_clock_fini, 103 .fini = _nouveau_clk_fini,
104 }, 104 },
105}; 105};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
index 08368fe97029..460ca4ab603b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
@@ -22,21 +22,21 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <subdev/clock.h> 25#include <subdev/clk.h>
26#include <subdev/bios.h> 26#include <subdev/bios.h>
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28 28
29#include "pll.h" 29#include "pll.h"
30 30
31struct nv40_clock_priv { 31struct nv40_clk_priv {
32 struct nouveau_clock base; 32 struct nouveau_clk base;
33 u32 ctrl; 33 u32 ctrl;
34 u32 npll_ctrl; 34 u32 npll_ctrl;
35 u32 npll_coef; 35 u32 npll_coef;
36 u32 spll; 36 u32 spll;
37}; 37};
38 38
39static struct nouveau_clocks 39static struct nouveau_domain
40nv40_domain[] = { 40nv40_domain[] = {
41 { nv_clk_src_crystal, 0xff }, 41 { nv_clk_src_crystal, 0xff },
42 { nv_clk_src_href , 0xff }, 42 { nv_clk_src_href , 0xff },
@@ -47,7 +47,7 @@ nv40_domain[] = {
47}; 47};
48 48
49static u32 49static u32
50read_pll_1(struct nv40_clock_priv *priv, u32 reg) 50read_pll_1(struct nv40_clk_priv *priv, u32 reg)
51{ 51{
52 u32 ctrl = nv_rd32(priv, reg + 0x00); 52 u32 ctrl = nv_rd32(priv, reg + 0x00);
53 int P = (ctrl & 0x00070000) >> 16; 53 int P = (ctrl & 0x00070000) >> 16;
@@ -62,7 +62,7 @@ read_pll_1(struct nv40_clock_priv *priv, u32 reg)
62} 62}
63 63
64static u32 64static u32
65read_pll_2(struct nv40_clock_priv *priv, u32 reg) 65read_pll_2(struct nv40_clk_priv *priv, u32 reg)
66{ 66{
67 u32 ctrl = nv_rd32(priv, reg + 0x00); 67 u32 ctrl = nv_rd32(priv, reg + 0x00);
68 u32 coef = nv_rd32(priv, reg + 0x04); 68 u32 coef = nv_rd32(priv, reg + 0x04);
@@ -87,7 +87,7 @@ read_pll_2(struct nv40_clock_priv *priv, u32 reg)
87} 87}
88 88
89static u32 89static u32
90read_clk(struct nv40_clock_priv *priv, u32 src) 90read_clk(struct nv40_clk_priv *priv, u32 src)
91{ 91{
92 switch (src) { 92 switch (src) {
93 case 3: 93 case 3:
@@ -102,9 +102,9 @@ read_clk(struct nv40_clock_priv *priv, u32 src)
102} 102}
103 103
104static int 104static int
105nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 105nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
106{ 106{
107 struct nv40_clock_priv *priv = (void *)clk; 107 struct nv40_clk_priv *priv = (void *)clk;
108 u32 mast = nv_rd32(priv, 0x00c040); 108 u32 mast = nv_rd32(priv, 0x00c040);
109 109
110 switch (src) { 110 switch (src) {
@@ -127,7 +127,7 @@ nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
127} 127}
128 128
129static int 129static int
130nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, 130nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
131 int *N1, int *M1, int *N2, int *M2, int *log2P) 131 int *N1, int *M1, int *N2, int *M2, int *log2P)
132{ 132{
133 struct nouveau_bios *bios = nouveau_bios(priv); 133 struct nouveau_bios *bios = nouveau_bios(priv);
@@ -148,16 +148,16 @@ nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
148} 148}
149 149
150static int 150static int
151nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 151nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
152{ 152{
153 struct nv40_clock_priv *priv = (void *)clk; 153 struct nv40_clk_priv *priv = (void *)clk;
154 int gclk = cstate->domain[nv_clk_src_core]; 154 int gclk = cstate->domain[nv_clk_src_core];
155 int sclk = cstate->domain[nv_clk_src_shader]; 155 int sclk = cstate->domain[nv_clk_src_shader];
156 int N1, M1, N2, M2, log2P; 156 int N1, M1, N2, M2, log2P;
157 int ret; 157 int ret;
158 158
159 /* core/geometric clock */ 159 /* core/geometric clock */
160 ret = nv40_clock_calc_pll(priv, 0x004000, gclk, 160 ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
161 &N1, &M1, &N2, &M2, &log2P); 161 &N1, &M1, &N2, &M2, &log2P);
162 if (ret < 0) 162 if (ret < 0)
163 return ret; 163 return ret;
@@ -172,7 +172,7 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
172 172
173 /* use the second pll for shader/rop clock, if it differs from core */ 173 /* use the second pll for shader/rop clock, if it differs from core */
174 if (sclk && sclk != gclk) { 174 if (sclk && sclk != gclk) {
175 ret = nv40_clock_calc_pll(priv, 0x004008, sclk, 175 ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
176 &N1, &M1, NULL, NULL, &log2P); 176 &N1, &M1, NULL, NULL, &log2P);
177 if (ret < 0) 177 if (ret < 0)
178 return ret; 178 return ret;
@@ -188,9 +188,9 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
188} 188}
189 189
190static int 190static int
191nv40_clock_prog(struct nouveau_clock *clk) 191nv40_clk_prog(struct nouveau_clk *clk)
192{ 192{
193 struct nv40_clock_priv *priv = (void *)clk; 193 struct nv40_clk_priv *priv = (void *)clk;
194 nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); 194 nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
195 nv_wr32(priv, 0x004004, priv->npll_coef); 195 nv_wr32(priv, 0x004004, priv->npll_coef);
196 nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); 196 nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
@@ -201,40 +201,40 @@ nv40_clock_prog(struct nouveau_clock *clk)
201} 201}
202 202
203static void 203static void
204nv40_clock_tidy(struct nouveau_clock *clk) 204nv40_clk_tidy(struct nouveau_clk *clk)
205{ 205{
206} 206}
207 207
208static int 208static int
209nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 209nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
210 struct nouveau_oclass *oclass, void *data, u32 size, 210 struct nouveau_oclass *oclass, void *data, u32 size,
211 struct nouveau_object **pobject) 211 struct nouveau_object **pobject)
212{ 212{
213 struct nv40_clock_priv *priv; 213 struct nv40_clk_priv *priv;
214 int ret; 214 int ret;
215 215
216 ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0, 216 ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0,
217 true, &priv); 217 true, &priv);
218 *pobject = nv_object(priv); 218 *pobject = nv_object(priv);
219 if (ret) 219 if (ret)
220 return ret; 220 return ret;
221 221
222 priv->base.pll_calc = nv04_clock_pll_calc; 222 priv->base.pll_calc = nv04_clk_pll_calc;
223 priv->base.pll_prog = nv04_clock_pll_prog; 223 priv->base.pll_prog = nv04_clk_pll_prog;
224 priv->base.read = nv40_clock_read; 224 priv->base.read = nv40_clk_read;
225 priv->base.calc = nv40_clock_calc; 225 priv->base.calc = nv40_clk_calc;
226 priv->base.prog = nv40_clock_prog; 226 priv->base.prog = nv40_clk_prog;
227 priv->base.tidy = nv40_clock_tidy; 227 priv->base.tidy = nv40_clk_tidy;
228 return 0; 228 return 0;
229} 229}
230 230
231struct nouveau_oclass 231struct nouveau_oclass
232nv40_clock_oclass = { 232nv40_clk_oclass = {
233 .handle = NV_SUBDEV(CLOCK, 0x40), 233 .handle = NV_SUBDEV(CLK, 0x40),
234 .ofuncs = &(struct nouveau_ofuncs) { 234 .ofuncs = &(struct nouveau_ofuncs) {
235 .ctor = nv40_clock_ctor, 235 .ctor = nv40_clk_ctor,
236 .dtor = _nouveau_clock_dtor, 236 .dtor = _nouveau_clk_dtor,
237 .init = _nouveau_clock_init, 237 .init = _nouveau_clk_init,
238 .fini = _nouveau_clock_fini, 238 .fini = _nouveau_clk_fini,
239 }, 239 },
240}; 240};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
index 5070ebc260f8..3c462a24922c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
@@ -30,7 +30,7 @@
30#include "seq.h" 30#include "seq.h"
31 31
32static u32 32static u32
33read_div(struct nv50_clock_priv *priv) 33read_div(struct nv50_clk_priv *priv)
34{ 34{
35 switch (nv_device(priv)->chipset) { 35 switch (nv_device(priv)->chipset) {
36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
@@ -49,9 +49,9 @@ read_div(struct nv50_clock_priv *priv)
49} 49}
50 50
51static u32 51static u32
52read_pll_src(struct nv50_clock_priv *priv, u32 base) 52read_pll_src(struct nv50_clk_priv *priv, u32 base)
53{ 53{
54 struct nouveau_clock *clk = &priv->base; 54 struct nouveau_clk *clk = &priv->base;
55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal); 55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
56 u32 rsel = nv_rd32(priv, 0x00e18c); 56 u32 rsel = nv_rd32(priv, 0x00e18c);
57 int P, N, M, id; 57 int P, N, M, id;
@@ -120,9 +120,9 @@ read_pll_src(struct nv50_clock_priv *priv, u32 base)
120} 120}
121 121
122static u32 122static u32
123read_pll_ref(struct nv50_clock_priv *priv, u32 base) 123read_pll_ref(struct nv50_clk_priv *priv, u32 base)
124{ 124{
125 struct nouveau_clock *clk = &priv->base; 125 struct nouveau_clk *clk = &priv->base;
126 u32 src, mast = nv_rd32(priv, 0x00c040); 126 u32 src, mast = nv_rd32(priv, 0x00c040);
127 127
128 switch (base) { 128 switch (base) {
@@ -151,9 +151,9 @@ read_pll_ref(struct nv50_clock_priv *priv, u32 base)
151} 151}
152 152
153static u32 153static u32
154read_pll(struct nv50_clock_priv *priv, u32 base) 154read_pll(struct nv50_clk_priv *priv, u32 base)
155{ 155{
156 struct nouveau_clock *clk = &priv->base; 156 struct nouveau_clk *clk = &priv->base;
157 u32 mast = nv_rd32(priv, 0x00c040); 157 u32 mast = nv_rd32(priv, 0x00c040);
158 u32 ctrl = nv_rd32(priv, base + 0); 158 u32 ctrl = nv_rd32(priv, base + 0);
159 u32 coef = nv_rd32(priv, base + 4); 159 u32 coef = nv_rd32(priv, base + 4);
@@ -185,9 +185,9 @@ read_pll(struct nv50_clock_priv *priv, u32 base)
185} 185}
186 186
187static int 187static int
188nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 188nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
189{ 189{
190 struct nv50_clock_priv *priv = (void *)clk; 190 struct nv50_clk_priv *priv = (void *)clk;
191 u32 mast = nv_rd32(priv, 0x00c040); 191 u32 mast = nv_rd32(priv, 0x00c040);
192 u32 P = 0; 192 u32 P = 0;
193 193
@@ -316,7 +316,7 @@ nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
316} 316}
317 317
318static u32 318static u32
319calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) 319calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
320{ 320{
321 struct nouveau_bios *bios = nouveau_bios(priv); 321 struct nouveau_bios *bios = nouveau_bios(priv);
322 struct nvbios_pll pll; 322 struct nvbios_pll pll;
@@ -359,10 +359,10 @@ clk_same(u32 a, u32 b)
359} 359}
360 360
361static int 361static int
362nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 362nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
363{ 363{
364 struct nv50_clock_priv *priv = (void *)clk; 364 struct nv50_clk_priv *priv = (void *)clk;
365 struct nv50_clock_hwsq *hwsq = &priv->hwsq; 365 struct nv50_clk_hwsq *hwsq = &priv->hwsq;
366 const int shader = cstate->domain[nv_clk_src_shader]; 366 const int shader = cstate->domain[nv_clk_src_shader];
367 const int core = cstate->domain[nv_clk_src_core]; 367 const int core = cstate->domain[nv_clk_src_core];
368 const int vdec = cstate->domain[nv_clk_src_vdec]; 368 const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -484,29 +484,29 @@ nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
484} 484}
485 485
486static int 486static int
487nv50_clock_prog(struct nouveau_clock *clk) 487nv50_clk_prog(struct nouveau_clk *clk)
488{ 488{
489 struct nv50_clock_priv *priv = (void *)clk; 489 struct nv50_clk_priv *priv = (void *)clk;
490 return clk_exec(&priv->hwsq, true); 490 return clk_exec(&priv->hwsq, true);
491} 491}
492 492
493static void 493static void
494nv50_clock_tidy(struct nouveau_clock *clk) 494nv50_clk_tidy(struct nouveau_clk *clk)
495{ 495{
496 struct nv50_clock_priv *priv = (void *)clk; 496 struct nv50_clk_priv *priv = (void *)clk;
497 clk_exec(&priv->hwsq, false); 497 clk_exec(&priv->hwsq, false);
498} 498}
499 499
500int 500int
501nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 501nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
502 struct nouveau_oclass *oclass, void *data, u32 size, 502 struct nouveau_oclass *oclass, void *data, u32 size,
503 struct nouveau_object **pobject) 503 struct nouveau_object **pobject)
504{ 504{
505 struct nv50_clock_oclass *pclass = (void *)oclass; 505 struct nv50_clk_oclass *pclass = (void *)oclass;
506 struct nv50_clock_priv *priv; 506 struct nv50_clk_priv *priv;
507 int ret; 507 int ret;
508 508
509 ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, 509 ret = nouveau_clk_create(parent, engine, oclass, pclass->domains,
510 NULL, 0, false, &priv); 510 NULL, 0, false, &priv);
511 *pobject = nv_object(priv); 511 *pobject = nv_object(priv);
512 if (ret) 512 if (ret)
@@ -529,14 +529,14 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
529 } 529 }
530 priv->hwsq.r_mast = hwsq_reg(0x00c040); 530 priv->hwsq.r_mast = hwsq_reg(0x00c040);
531 531
532 priv->base.read = nv50_clock_read; 532 priv->base.read = nv50_clk_read;
533 priv->base.calc = nv50_clock_calc; 533 priv->base.calc = nv50_clk_calc;
534 priv->base.prog = nv50_clock_prog; 534 priv->base.prog = nv50_clk_prog;
535 priv->base.tidy = nv50_clock_tidy; 535 priv->base.tidy = nv50_clk_tidy;
536 return 0; 536 return 0;
537} 537}
538 538
539static struct nouveau_clocks 539static struct nouveau_domain
540nv50_domains[] = { 540nv50_domains[] = {
541 { nv_clk_src_crystal, 0xff }, 541 { nv_clk_src_crystal, 0xff },
542 { nv_clk_src_href , 0xff }, 542 { nv_clk_src_href , 0xff },
@@ -547,13 +547,13 @@ nv50_domains[] = {
547}; 547};
548 548
549struct nouveau_oclass * 549struct nouveau_oclass *
550nv50_clock_oclass = &(struct nv50_clock_oclass) { 550nv50_clk_oclass = &(struct nv50_clk_oclass) {
551 .base.handle = NV_SUBDEV(CLOCK, 0x50), 551 .base.handle = NV_SUBDEV(CLK, 0x50),
552 .base.ofuncs = &(struct nouveau_ofuncs) { 552 .base.ofuncs = &(struct nouveau_ofuncs) {
553 .ctor = nv50_clock_ctor, 553 .ctor = nv50_clk_ctor,
554 .dtor = _nouveau_clock_dtor, 554 .dtor = _nouveau_clk_dtor,
555 .init = _nouveau_clock_init, 555 .init = _nouveau_clk_init,
556 .fini = _nouveau_clock_fini, 556 .fini = _nouveau_clk_fini,
557 }, 557 },
558 .domains = nv50_domains, 558 .domains = nv50_domains,
559}.base; 559}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
index f10917d789e8..ae6421fd28f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
@@ -3,9 +3,9 @@
3 3
4#include <subdev/bus.h> 4#include <subdev/bus.h>
5#include <subdev/bus/hwsq.h> 5#include <subdev/bus/hwsq.h>
6#include <subdev/clock.h> 6#include <subdev/clk.h>
7 7
8struct nv50_clock_hwsq { 8struct nv50_clk_hwsq {
9 struct hwsq base; 9 struct hwsq base;
10 struct hwsq_reg r_fifo; 10 struct hwsq_reg r_fifo;
11 struct hwsq_reg r_spll[2]; 11 struct hwsq_reg r_spll[2];
@@ -14,18 +14,18 @@ struct nv50_clock_hwsq {
14 struct hwsq_reg r_mast; 14 struct hwsq_reg r_mast;
15}; 15};
16 16
17struct nv50_clock_priv { 17struct nv50_clk_priv {
18 struct nouveau_clock base; 18 struct nouveau_clk base;
19 struct nv50_clock_hwsq hwsq; 19 struct nv50_clk_hwsq hwsq;
20}; 20};
21 21
22int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *, 22int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *,
23 struct nouveau_oclass *, void *, u32, 23 struct nouveau_oclass *, void *, u32,
24 struct nouveau_object **); 24 struct nouveau_object **);
25 25
26struct nv50_clock_oclass { 26struct nv50_clk_oclass {
27 struct nouveau_oclass base; 27 struct nouveau_oclass base;
28 struct nouveau_clocks *domains; 28 struct nouveau_domain *domains;
29}; 29};
30 30
31#endif 31#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
index b0b7c1437f10..b5b00b3df6c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
@@ -24,7 +24,7 @@
24 24
25#include "nv50.h" 25#include "nv50.h"
26 26
27static struct nouveau_clocks 27static struct nouveau_domain
28nv84_domains[] = { 28nv84_domains[] = {
29 { nv_clk_src_crystal, 0xff }, 29 { nv_clk_src_crystal, 0xff },
30 { nv_clk_src_href , 0xff }, 30 { nv_clk_src_href , 0xff },
@@ -36,13 +36,13 @@ nv84_domains[] = {
36}; 36};
37 37
38struct nouveau_oclass * 38struct nouveau_oclass *
39nv84_clock_oclass = &(struct nv50_clock_oclass) { 39nv84_clk_oclass = &(struct nv50_clk_oclass) {
40 .base.handle = NV_SUBDEV(CLOCK, 0x84), 40 .base.handle = NV_SUBDEV(CLK, 0x84),
41 .base.ofuncs = &(struct nouveau_ofuncs) { 41 .base.ofuncs = &(struct nouveau_ofuncs) {
42 .ctor = nv50_clock_ctor, 42 .ctor = nv50_clk_ctor,
43 .dtor = _nouveau_clock_dtor, 43 .dtor = _nouveau_clk_dtor,
44 .init = _nouveau_clock_init, 44 .init = _nouveau_clk_init,
45 .fini = _nouveau_clock_fini, 45 .fini = _nouveau_clk_fini,
46 }, 46 },
47 .domains = nv84_domains, 47 .domains = nv84_domains,
48}.base; 48}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
index 07ad01247675..3002c60a3993 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
@@ -32,16 +32,16 @@
32 32
33#include "nva3.h" 33#include "nva3.h"
34 34
35struct nva3_clock_priv { 35struct nva3_clk_priv {
36 struct nouveau_clock base; 36 struct nouveau_clk base;
37 struct nva3_clock_info eng[nv_clk_src_max]; 37 struct nva3_clk_info eng[nv_clk_src_max];
38}; 38};
39 39
40static u32 read_clk(struct nva3_clock_priv *, int, bool); 40static u32 read_clk(struct nva3_clk_priv *, int, bool);
41static u32 read_pll(struct nva3_clock_priv *, int, u32); 41static u32 read_pll(struct nva3_clk_priv *, int, u32);
42 42
43static u32 43static u32
44read_vco(struct nva3_clock_priv *priv, int clk) 44read_vco(struct nva3_clk_priv *priv, int clk)
45{ 45{
46 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); 46 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
47 47
@@ -58,7 +58,7 @@ read_vco(struct nva3_clock_priv *priv, int clk)
58} 58}
59 59
60static u32 60static u32
61read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) 61read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en)
62{ 62{
63 u32 sctl, sdiv, sclk; 63 u32 sctl, sdiv, sclk;
64 64
@@ -104,7 +104,7 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
104} 104}
105 105
106static u32 106static u32
107read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) 107read_pll(struct nva3_clk_priv *priv, int clk, u32 pll)
108{ 108{
109 u32 ctrl = nv_rd32(priv, pll + 0); 109 u32 ctrl = nv_rd32(priv, pll + 0);
110 u32 sclk = 0, P = 1, N = 1, M = 1; 110 u32 sclk = 0, P = 1, N = 1, M = 1;
@@ -134,9 +134,9 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
134} 134}
135 135
136static int 136static int
137nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 137nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
138{ 138{
139 struct nva3_clock_priv *priv = (void *)clk; 139 struct nva3_clk_priv *priv = (void *)clk;
140 u32 hsrc; 140 u32 hsrc;
141 141
142 switch (src) { 142 switch (src) {
@@ -176,10 +176,10 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
176} 176}
177 177
178int 178int
179nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, 179nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz,
180 struct nva3_clock_info *info) 180 struct nva3_clk_info *info)
181{ 181{
182 struct nva3_clock_priv *priv = (void *)clock; 182 struct nva3_clk_priv *priv = (void *)clock;
183 u32 oclk, sclk, sdiv, diff; 183 u32 oclk, sclk, sdiv, diff;
184 184
185 info->clk = 0; 185 info->clk = 0;
@@ -223,11 +223,11 @@ nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
223} 223}
224 224
225int 225int
226nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, 226nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
227 struct nva3_clock_info *info) 227 struct nva3_clk_info *info)
228{ 228{
229 struct nouveau_bios *bios = nouveau_bios(clock); 229 struct nouveau_bios *bios = nouveau_bios(clock);
230 struct nva3_clock_priv *priv = (void *)clock; 230 struct nva3_clk_priv *priv = (void *)clock;
231 struct nvbios_pll limits; 231 struct nvbios_pll limits;
232 int P, N, M, diff; 232 int P, N, M, diff;
233 int ret; 233 int ret;
@@ -263,7 +263,7 @@ out:
263} 263}
264 264
265static int 265static int
266calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, 266calc_clk(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate,
267 int clk, u32 pll, int idx) 267 int clk, u32 pll, int idx)
268{ 268{
269 int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], 269 int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
@@ -274,11 +274,11 @@ calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
274} 274}
275 275
276static int 276static int
277calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) 277calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate)
278{ 278{
279 int ret = 0; 279 int ret = 0;
280 u32 kHz = cstate->domain[nv_clk_src_host]; 280 u32 kHz = cstate->domain[nv_clk_src_host];
281 struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; 281 struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
282 282
283 if (kHz == 277000) { 283 if (kHz == 277000) {
284 info->clk = 0; 284 info->clk = 0;
@@ -295,7 +295,7 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
295} 295}
296 296
297int 297int
298nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) 298nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags)
299{ 299{
300 struct nouveau_fifo *pfifo = nouveau_fifo(clk); 300 struct nouveau_fifo *pfifo = nouveau_fifo(clk);
301 301
@@ -318,7 +318,7 @@ nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
318} 318}
319 319
320void 320void
321nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) 321nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags)
322{ 322{
323 struct nouveau_fifo *pfifo = nouveau_fifo(clk); 323 struct nouveau_fifo *pfifo = nouveau_fifo(clk);
324 324
@@ -330,16 +330,16 @@ nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
330} 330}
331 331
332static void 332static void
333disable_clk_src(struct nva3_clock_priv *priv, u32 src) 333disable_clk_src(struct nva3_clk_priv *priv, u32 src)
334{ 334{
335 nv_mask(priv, src, 0x00000100, 0x00000000); 335 nv_mask(priv, src, 0x00000100, 0x00000000);
336 nv_mask(priv, src, 0x00000001, 0x00000000); 336 nv_mask(priv, src, 0x00000001, 0x00000000);
337} 337}
338 338
339static void 339static void
340prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) 340prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx)
341{ 341{
342 struct nva3_clock_info *info = &priv->eng[idx]; 342 struct nva3_clk_info *info = &priv->eng[idx];
343 const u32 src0 = 0x004120 + (clk * 4); 343 const u32 src0 = 0x004120 + (clk * 4);
344 const u32 src1 = 0x004160 + (clk * 4); 344 const u32 src1 = 0x004160 + (clk * 4);
345 const u32 ctrl = pll + 0; 345 const u32 ctrl = pll + 0;
@@ -377,16 +377,16 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
377} 377}
378 378
379static void 379static void
380prog_clk(struct nva3_clock_priv *priv, int clk, int idx) 380prog_clk(struct nva3_clk_priv *priv, int clk, int idx)
381{ 381{
382 struct nva3_clock_info *info = &priv->eng[idx]; 382 struct nva3_clk_info *info = &priv->eng[idx];
383 nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); 383 nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
384} 384}
385 385
386static void 386static void
387prog_host(struct nva3_clock_priv *priv) 387prog_host(struct nva3_clk_priv *priv)
388{ 388{
389 struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; 389 struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
390 u32 hsrc = (nv_rd32(priv, 0xc040)); 390 u32 hsrc = (nv_rd32(priv, 0xc040));
391 391
392 switch (info->host_out) { 392 switch (info->host_out) {
@@ -411,9 +411,9 @@ prog_host(struct nva3_clock_priv *priv)
411} 411}
412 412
413static void 413static void
414prog_core(struct nva3_clock_priv *priv, int idx) 414prog_core(struct nva3_clk_priv *priv, int idx)
415{ 415{
416 struct nva3_clock_info *info = &priv->eng[idx]; 416 struct nva3_clk_info *info = &priv->eng[idx];
417 u32 fb_delay = nv_rd32(priv, 0x10002c); 417 u32 fb_delay = nv_rd32(priv, 0x10002c);
418 418
419 if (fb_delay < info->fb_delay) 419 if (fb_delay < info->fb_delay)
@@ -426,10 +426,10 @@ prog_core(struct nva3_clock_priv *priv, int idx)
426} 426}
427 427
428static int 428static int
429nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 429nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
430{ 430{
431 struct nva3_clock_priv *priv = (void *)clk; 431 struct nva3_clk_priv *priv = (void *)clk;
432 struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; 432 struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
433 int ret; 433 int ret;
434 434
435 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || 435 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
@@ -453,15 +453,15 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
453} 453}
454 454
455static int 455static int
456nva3_clock_prog(struct nouveau_clock *clk) 456nva3_clk_prog(struct nouveau_clk *clk)
457{ 457{
458 struct nva3_clock_priv *priv = (void *)clk; 458 struct nva3_clk_priv *priv = (void *)clk;
459 struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; 459 struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
460 int ret = 0; 460 int ret = 0;
461 unsigned long flags; 461 unsigned long flags;
462 unsigned long *f = &flags; 462 unsigned long *f = &flags;
463 463
464 ret = nva3_clock_pre(clk, f); 464 ret = nva3_clk_pre(clk, f);
465 if (ret) 465 if (ret)
466 goto out; 466 goto out;
467 467
@@ -478,17 +478,17 @@ out:
478 if (ret == -EBUSY) 478 if (ret == -EBUSY)
479 f = NULL; 479 f = NULL;
480 480
481 nva3_clock_post(clk, f); 481 nva3_clk_post(clk, f);
482 482
483 return ret; 483 return ret;
484} 484}
485 485
486static void 486static void
487nva3_clock_tidy(struct nouveau_clock *clk) 487nva3_clk_tidy(struct nouveau_clk *clk)
488{ 488{
489} 489}
490 490
491static struct nouveau_clocks 491static struct nouveau_domain
492nva3_domain[] = { 492nva3_domain[] = {
493 { nv_clk_src_crystal , 0xff }, 493 { nv_clk_src_crystal , 0xff },
494 { nv_clk_src_core , 0x00, 0, "core", 1000 }, 494 { nv_clk_src_core , 0x00, 0, "core", 1000 },
@@ -502,33 +502,33 @@ nva3_domain[] = {
502}; 502};
503 503
504static int 504static int
505nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 505nva3_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
506 struct nouveau_oclass *oclass, void *data, u32 size, 506 struct nouveau_oclass *oclass, void *data, u32 size,
507 struct nouveau_object **pobject) 507 struct nouveau_object **pobject)
508{ 508{
509 struct nva3_clock_priv *priv; 509 struct nva3_clk_priv *priv;
510 int ret; 510 int ret;
511 511
512 ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, 512 ret = nouveau_clk_create(parent, engine, oclass, nva3_domain, NULL, 0,
513 true, &priv); 513 true, &priv);
514 *pobject = nv_object(priv); 514 *pobject = nv_object(priv);
515 if (ret) 515 if (ret)
516 return ret; 516 return ret;
517 517
518 priv->base.read = nva3_clock_read; 518 priv->base.read = nva3_clk_read;
519 priv->base.calc = nva3_clock_calc; 519 priv->base.calc = nva3_clk_calc;
520 priv->base.prog = nva3_clock_prog; 520 priv->base.prog = nva3_clk_prog;
521 priv->base.tidy = nva3_clock_tidy; 521 priv->base.tidy = nva3_clk_tidy;
522 return 0; 522 return 0;
523} 523}
524 524
525struct nouveau_oclass 525struct nouveau_oclass
526nva3_clock_oclass = { 526nva3_clk_oclass = {
527 .handle = NV_SUBDEV(CLOCK, 0xa3), 527 .handle = NV_SUBDEV(CLK, 0xa3),
528 .ofuncs = &(struct nouveau_ofuncs) { 528 .ofuncs = &(struct nouveau_ofuncs) {
529 .ctor = nva3_clock_ctor, 529 .ctor = nva3_clk_ctor,
530 .dtor = _nouveau_clock_dtor, 530 .dtor = _nouveau_clk_dtor,
531 .init = _nouveau_clock_init, 531 .init = _nouveau_clk_init,
532 .fini = _nouveau_clock_fini, 532 .fini = _nouveau_clk_fini,
533 }, 533 },
534}; 534};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
new file mode 100644
index 000000000000..ce0fc83345e3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
@@ -0,0 +1,20 @@
1#ifndef __NVKM_CLK_NVA3_H__
2#define __NVKM_CLK_NVA3_H__
3
4#include <subdev/clk.h>
5
6struct nva3_clk_info {
7 u32 clk;
8 u32 pll;
9 enum {
10 NVA3_HOST_277,
11 NVA3_HOST_CLK,
12 } host_out;
13 u32 fb_delay;
14};
15
16int nva3_pll_info(struct nouveau_clk *, int, u32, u32,
17 struct nva3_clk_info *);
18int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags);
19void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags);
20#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
index 54aeab8005a0..d6d2bd190144 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
@@ -26,13 +26,13 @@
26#include <subdev/bios.h> 26#include <subdev/bios.h>
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/clock.h> 29#include <subdev/clk.h>
30 30
31#include "nva3.h" 31#include "nva3.h"
32#include "pll.h" 32#include "pll.h"
33 33
34struct nvaa_clock_priv { 34struct nvaa_clk_priv {
35 struct nouveau_clock base; 35 struct nouveau_clk base;
36 enum nv_clk_src csrc, ssrc, vsrc; 36 enum nv_clk_src csrc, ssrc, vsrc;
37 u32 cctrl, sctrl; 37 u32 cctrl, sctrl;
38 u32 ccoef, scoef; 38 u32 ccoef, scoef;
@@ -41,13 +41,13 @@ struct nvaa_clock_priv {
41}; 41};
42 42
43static u32 43static u32
44read_div(struct nouveau_clock *clk) 44read_div(struct nouveau_clk *clk)
45{ 45{
46 return nv_rd32(clk, 0x004600); 46 return nv_rd32(clk, 0x004600);
47} 47}
48 48
49static u32 49static u32
50read_pll(struct nouveau_clock *clk, u32 base) 50read_pll(struct nouveau_clk *clk, u32 base)
51{ 51{
52 u32 ctrl = nv_rd32(clk, base + 0); 52 u32 ctrl = nv_rd32(clk, base + 0);
53 u32 coef = nv_rd32(clk, base + 4); 53 u32 coef = nv_rd32(clk, base + 4);
@@ -78,9 +78,9 @@ read_pll(struct nouveau_clock *clk, u32 base)
78} 78}
79 79
80static int 80static int
81nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 81nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
82{ 82{
83 struct nvaa_clock_priv *priv = (void *)clk; 83 struct nvaa_clk_priv *priv = (void *)clk;
84 u32 mast = nv_rd32(clk, 0x00c054); 84 u32 mast = nv_rd32(clk, 0x00c054);
85 u32 P = 0; 85 u32 P = 0;
86 86
@@ -160,12 +160,12 @@ nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
160} 160}
161 161
162static u32 162static u32
163calc_pll(struct nvaa_clock_priv *priv, u32 reg, 163calc_pll(struct nvaa_clk_priv *priv, u32 reg,
164 u32 clock, int *N, int *M, int *P) 164 u32 clock, int *N, int *M, int *P)
165{ 165{
166 struct nouveau_bios *bios = nouveau_bios(priv); 166 struct nouveau_bios *bios = nouveau_bios(priv);
167 struct nvbios_pll pll; 167 struct nvbios_pll pll;
168 struct nouveau_clock *clk = &priv->base; 168 struct nouveau_clk *clk = &priv->base;
169 int ret; 169 int ret;
170 170
171 ret = nvbios_pll_parse(bios, reg, &pll); 171 ret = nvbios_pll_parse(bios, reg, &pll);
@@ -199,9 +199,9 @@ calc_P(u32 src, u32 target, int *div)
199} 199}
200 200
201static int 201static int
202nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 202nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
203{ 203{
204 struct nvaa_clock_priv *priv = (void *)clk; 204 struct nvaa_clk_priv *priv = (void *)clk;
205 const int shader = cstate->domain[nv_clk_src_shader]; 205 const int shader = cstate->domain[nv_clk_src_shader];
206 const int core = cstate->domain[nv_clk_src_core]; 206 const int core = cstate->domain[nv_clk_src_core];
207 const int vdec = cstate->domain[nv_clk_src_vdec]; 207 const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -297,15 +297,15 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
297} 297}
298 298
299static int 299static int
300nvaa_clock_prog(struct nouveau_clock *clk) 300nvaa_clk_prog(struct nouveau_clk *clk)
301{ 301{
302 struct nvaa_clock_priv *priv = (void *)clk; 302 struct nvaa_clk_priv *priv = (void *)clk;
303 u32 pllmask = 0, mast; 303 u32 pllmask = 0, mast;
304 unsigned long flags; 304 unsigned long flags;
305 unsigned long *f = &flags; 305 unsigned long *f = &flags;
306 int ret = 0; 306 int ret = 0;
307 307
308 ret = nva3_clock_pre(clk, f); 308 ret = nva3_clk_pre(clk, f);
309 if (ret) 309 if (ret)
310 goto out; 310 goto out;
311 311
@@ -382,17 +382,17 @@ out:
382 if (ret == -EBUSY) 382 if (ret == -EBUSY)
383 f = NULL; 383 f = NULL;
384 384
385 nva3_clock_post(clk, f); 385 nva3_clk_post(clk, f);
386 386
387 return ret; 387 return ret;
388} 388}
389 389
390static void 390static void
391nvaa_clock_tidy(struct nouveau_clock *clk) 391nvaa_clk_tidy(struct nouveau_clk *clk)
392{ 392{
393} 393}
394 394
395static struct nouveau_clocks 395static struct nouveau_domain
396nvaa_domains[] = { 396nvaa_domains[] = {
397 { nv_clk_src_crystal, 0xff }, 397 { nv_clk_src_crystal, 0xff },
398 { nv_clk_src_href , 0xff }, 398 { nv_clk_src_href , 0xff },
@@ -403,33 +403,33 @@ nvaa_domains[] = {
403}; 403};
404 404
405static int 405static int
406nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 406nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
407 struct nouveau_oclass *oclass, void *data, u32 size, 407 struct nouveau_oclass *oclass, void *data, u32 size,
408 struct nouveau_object **pobject) 408 struct nouveau_object **pobject)
409{ 409{
410 struct nvaa_clock_priv *priv; 410 struct nvaa_clk_priv *priv;
411 int ret; 411 int ret;
412 412
413 ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL, 413 ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL,
414 0, true, &priv); 414 0, true, &priv);
415 *pobject = nv_object(priv); 415 *pobject = nv_object(priv);
416 if (ret) 416 if (ret)
417 return ret; 417 return ret;
418 418
419 priv->base.read = nvaa_clock_read; 419 priv->base.read = nvaa_clk_read;
420 priv->base.calc = nvaa_clock_calc; 420 priv->base.calc = nvaa_clk_calc;
421 priv->base.prog = nvaa_clock_prog; 421 priv->base.prog = nvaa_clk_prog;
422 priv->base.tidy = nvaa_clock_tidy; 422 priv->base.tidy = nvaa_clk_tidy;
423 return 0; 423 return 0;
424} 424}
425 425
426struct nouveau_oclass * 426struct nouveau_oclass *
427nvaa_clock_oclass = &(struct nouveau_oclass) { 427nvaa_clk_oclass = &(struct nouveau_oclass) {
428 .handle = NV_SUBDEV(CLOCK, 0xaa), 428 .handle = NV_SUBDEV(CLK, 0xaa),
429 .ofuncs = &(struct nouveau_ofuncs) { 429 .ofuncs = &(struct nouveau_ofuncs) {
430 .ctor = nvaa_clock_ctor, 430 .ctor = nvaa_clk_ctor,
431 .dtor = _nouveau_clock_dtor, 431 .dtor = _nouveau_clk_dtor,
432 .init = _nouveau_clock_init, 432 .init = _nouveau_clk_init,
433 .fini = _nouveau_clock_fini, 433 .fini = _nouveau_clk_fini,
434 }, 434 },
435}; 435};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
index 1234abaab2db..791a9f5198eb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
@@ -22,14 +22,14 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <subdev/clock.h> 25#include <subdev/clk.h>
26#include <subdev/bios.h> 26#include <subdev/bios.h>
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29 29
30#include "pll.h" 30#include "pll.h"
31 31
32struct nvc0_clock_info { 32struct nvc0_clk_info {
33 u32 freq; 33 u32 freq;
34 u32 ssel; 34 u32 ssel;
35 u32 mdiv; 35 u32 mdiv;
@@ -38,17 +38,17 @@ struct nvc0_clock_info {
38 u32 coef; 38 u32 coef;
39}; 39};
40 40
41struct nvc0_clock_priv { 41struct nvc0_clk_priv {
42 struct nouveau_clock base; 42 struct nouveau_clk base;
43 struct nvc0_clock_info eng[16]; 43 struct nvc0_clk_info eng[16];
44}; 44};
45 45
46static u32 read_div(struct nvc0_clock_priv *, int, u32, u32); 46static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
47 47
48static u32 48static u32
49read_vco(struct nvc0_clock_priv *priv, u32 dsrc) 49read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
50{ 50{
51 struct nouveau_clock *clk = &priv->base; 51 struct nouveau_clk *clk = &priv->base;
52 u32 ssrc = nv_rd32(priv, dsrc); 52 u32 ssrc = nv_rd32(priv, dsrc);
53 if (!(ssrc & 0x00000100)) 53 if (!(ssrc & 0x00000100))
54 return clk->read(clk, nv_clk_src_sppll0); 54 return clk->read(clk, nv_clk_src_sppll0);
@@ -56,9 +56,9 @@ read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
56} 56}
57 57
58static u32 58static u32
59read_pll(struct nvc0_clock_priv *priv, u32 pll) 59read_pll(struct nvc0_clk_priv *priv, u32 pll)
60{ 60{
61 struct nouveau_clock *clk = &priv->base; 61 struct nouveau_clk *clk = &priv->base;
62 u32 ctrl = nv_rd32(priv, pll + 0x00); 62 u32 ctrl = nv_rd32(priv, pll + 0x00);
63 u32 coef = nv_rd32(priv, pll + 0x04); 63 u32 coef = nv_rd32(priv, pll + 0x04);
64 u32 P = (coef & 0x003f0000) >> 16; 64 u32 P = (coef & 0x003f0000) >> 16;
@@ -95,7 +95,7 @@ read_pll(struct nvc0_clock_priv *priv, u32 pll)
95} 95}
96 96
97static u32 97static u32
98read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) 98read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
99{ 99{
100 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); 100 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
101 u32 sctl = nv_rd32(priv, dctl + (doff * 4)); 101 u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -121,7 +121,7 @@ read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
121} 121}
122 122
123static u32 123static u32
124read_clk(struct nvc0_clock_priv *priv, int clk) 124read_clk(struct nvc0_clk_priv *priv, int clk)
125{ 125{
126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); 126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
127 u32 ssel = nv_rd32(priv, 0x137100); 127 u32 ssel = nv_rd32(priv, 0x137100);
@@ -145,10 +145,10 @@ read_clk(struct nvc0_clock_priv *priv, int clk)
145} 145}
146 146
147static int 147static int
148nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 148nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
149{ 149{
150 struct nouveau_device *device = nv_device(clk); 150 struct nouveau_device *device = nv_device(clk);
151 struct nvc0_clock_priv *priv = (void *)clk; 151 struct nvc0_clk_priv *priv = (void *)clk;
152 152
153 switch (src) { 153 switch (src) {
154 case nv_clk_src_crystal: 154 case nv_clk_src_crystal:
@@ -196,7 +196,7 @@ nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
196} 196}
197 197
198static u32 198static u32
199calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) 199calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
200{ 200{
201 u32 div = min((ref * 2) / freq, (u32)65); 201 u32 div = min((ref * 2) / freq, (u32)65);
202 if (div < 2) 202 if (div < 2)
@@ -207,7 +207,7 @@ calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
207} 207}
208 208
209static u32 209static u32
210calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) 210calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
211{ 211{
212 u32 sclk; 212 u32 sclk;
213 213
@@ -236,7 +236,7 @@ calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
236} 236}
237 237
238static u32 238static u32
239calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) 239calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
240{ 240{
241 struct nouveau_bios *bios = nouveau_bios(priv); 241 struct nouveau_bios *bios = nouveau_bios(priv);
242 struct nvbios_pll limits; 242 struct nvbios_pll limits;
@@ -259,10 +259,10 @@ calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
259} 259}
260 260
261static int 261static int
262calc_clk(struct nvc0_clock_priv *priv, 262calc_clk(struct nvc0_clk_priv *priv,
263 struct nouveau_cstate *cstate, int clk, int dom) 263 struct nouveau_cstate *cstate, int clk, int dom)
264{ 264{
265 struct nvc0_clock_info *info = &priv->eng[clk]; 265 struct nvc0_clk_info *info = &priv->eng[clk];
266 u32 freq = cstate->domain[dom]; 266 u32 freq = cstate->domain[dom];
267 u32 src0, div0, div1D, div1P = 0; 267 u32 src0, div0, div1D, div1P = 0;
268 u32 clk0, clk1 = 0; 268 u32 clk0, clk1 = 0;
@@ -311,9 +311,9 @@ calc_clk(struct nvc0_clock_priv *priv,
311} 311}
312 312
313static int 313static int
314nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 314nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
315{ 315{
316 struct nvc0_clock_priv *priv = (void *)clk; 316 struct nvc0_clk_priv *priv = (void *)clk;
317 int ret; 317 int ret;
318 318
319 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || 319 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -330,9 +330,9 @@ nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
330} 330}
331 331
332static void 332static void
333nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) 333nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
334{ 334{
335 struct nvc0_clock_info *info = &priv->eng[clk]; 335 struct nvc0_clk_info *info = &priv->eng[clk];
336 if (clk < 7 && !info->ssel) { 336 if (clk < 7 && !info->ssel) {
337 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); 337 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
338 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); 338 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -340,16 +340,16 @@ nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
340} 340}
341 341
342static void 342static void
343nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk) 343nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
344{ 344{
345 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); 345 nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
346 nv_wait(priv, 0x137100, (1 << clk), 0x00000000); 346 nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
347} 347}
348 348
349static void 349static void
350nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) 350nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
351{ 351{
352 struct nvc0_clock_info *info = &priv->eng[clk]; 352 struct nvc0_clk_info *info = &priv->eng[clk];
353 const u32 addr = 0x137000 + (clk * 0x20); 353 const u32 addr = 0x137000 + (clk * 0x20);
354 if (clk <= 7) { 354 if (clk <= 7) {
355 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); 355 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
@@ -364,9 +364,9 @@ nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
364} 364}
365 365
366static void 366static void
367nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) 367nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
368{ 368{
369 struct nvc0_clock_info *info = &priv->eng[clk]; 369 struct nvc0_clk_info *info = &priv->eng[clk];
370 if (info->ssel) { 370 if (info->ssel) {
371 nv_mask(priv, 0x137100, (1 << clk), info->ssel); 371 nv_mask(priv, 0x137100, (1 << clk), info->ssel);
372 nv_wait(priv, 0x137100, (1 << clk), info->ssel); 372 nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -374,24 +374,24 @@ nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
374} 374}
375 375
376static void 376static void
377nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk) 377nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
378{ 378{
379 struct nvc0_clock_info *info = &priv->eng[clk]; 379 struct nvc0_clk_info *info = &priv->eng[clk];
380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); 380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
381} 381}
382 382
383static int 383static int
384nvc0_clock_prog(struct nouveau_clock *clk) 384nvc0_clk_prog(struct nouveau_clk *clk)
385{ 385{
386 struct nvc0_clock_priv *priv = (void *)clk; 386 struct nvc0_clk_priv *priv = (void *)clk;
387 struct { 387 struct {
388 void (*exec)(struct nvc0_clock_priv *, int); 388 void (*exec)(struct nvc0_clk_priv *, int);
389 } stage[] = { 389 } stage[] = {
390 { nvc0_clock_prog_0 }, /* div programming */ 390 { nvc0_clk_prog_0 }, /* div programming */
391 { nvc0_clock_prog_1 }, /* select div mode */ 391 { nvc0_clk_prog_1 }, /* select div mode */
392 { nvc0_clock_prog_2 }, /* (maybe) program pll */ 392 { nvc0_clk_prog_2 }, /* (maybe) program pll */
393 { nvc0_clock_prog_3 }, /* (maybe) select pll mode */ 393 { nvc0_clk_prog_3 }, /* (maybe) select pll mode */
394 { nvc0_clock_prog_4 }, /* final divider */ 394 { nvc0_clk_prog_4 }, /* final divider */
395 }; 395 };
396 int i, j; 396 int i, j;
397 397
@@ -407,13 +407,13 @@ nvc0_clock_prog(struct nouveau_clock *clk)
407} 407}
408 408
409static void 409static void
410nvc0_clock_tidy(struct nouveau_clock *clk) 410nvc0_clk_tidy(struct nouveau_clk *clk)
411{ 411{
412 struct nvc0_clock_priv *priv = (void *)clk; 412 struct nvc0_clk_priv *priv = (void *)clk;
413 memset(priv->eng, 0x00, sizeof(priv->eng)); 413 memset(priv->eng, 0x00, sizeof(priv->eng));
414} 414}
415 415
416static struct nouveau_clocks 416static struct nouveau_domain
417nvc0_domain[] = { 417nvc0_domain[] = {
418 { nv_clk_src_crystal, 0xff }, 418 { nv_clk_src_crystal, 0xff },
419 { nv_clk_src_href , 0xff }, 419 { nv_clk_src_href , 0xff },
@@ -430,33 +430,33 @@ nvc0_domain[] = {
430}; 430};
431 431
432static int 432static int
433nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 433nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
434 struct nouveau_oclass *oclass, void *data, u32 size, 434 struct nouveau_oclass *oclass, void *data, u32 size,
435 struct nouveau_object **pobject) 435 struct nouveau_object **pobject)
436{ 436{
437 struct nvc0_clock_priv *priv; 437 struct nvc0_clk_priv *priv;
438 int ret; 438 int ret;
439 439
440 ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0, 440 ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
441 false, &priv); 441 false, &priv);
442 *pobject = nv_object(priv); 442 *pobject = nv_object(priv);
443 if (ret) 443 if (ret)
444 return ret; 444 return ret;
445 445
446 priv->base.read = nvc0_clock_read; 446 priv->base.read = nvc0_clk_read;
447 priv->base.calc = nvc0_clock_calc; 447 priv->base.calc = nvc0_clk_calc;
448 priv->base.prog = nvc0_clock_prog; 448 priv->base.prog = nvc0_clk_prog;
449 priv->base.tidy = nvc0_clock_tidy; 449 priv->base.tidy = nvc0_clk_tidy;
450 return 0; 450 return 0;
451} 451}
452 452
453struct nouveau_oclass 453struct nouveau_oclass
454nvc0_clock_oclass = { 454nvc0_clk_oclass = {
455 .handle = NV_SUBDEV(CLOCK, 0xc0), 455 .handle = NV_SUBDEV(CLK, 0xc0),
456 .ofuncs = &(struct nouveau_ofuncs) { 456 .ofuncs = &(struct nouveau_ofuncs) {
457 .ctor = nvc0_clock_ctor, 457 .ctor = nvc0_clk_ctor,
458 .dtor = _nouveau_clock_dtor, 458 .dtor = _nouveau_clk_dtor,
459 .init = _nouveau_clock_init, 459 .init = _nouveau_clk_init,
460 .fini = _nouveau_clock_fini, 460 .fini = _nouveau_clk_fini,
461 }, 461 },
462}; 462};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
index 7eccad57512e..ffd2139e0a49 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
@@ -22,14 +22,14 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <subdev/clock.h> 25#include <subdev/clk.h>
26#include <subdev/timer.h> 26#include <subdev/timer.h>
27#include <subdev/bios.h> 27#include <subdev/bios.h>
28#include <subdev/bios/pll.h> 28#include <subdev/bios/pll.h>
29 29
30#include "pll.h" 30#include "pll.h"
31 31
32struct nve0_clock_info { 32struct nve0_clk_info {
33 u32 freq; 33 u32 freq;
34 u32 ssel; 34 u32 ssel;
35 u32 mdiv; 35 u32 mdiv;
@@ -38,16 +38,16 @@ struct nve0_clock_info {
38 u32 coef; 38 u32 coef;
39}; 39};
40 40
41struct nve0_clock_priv { 41struct nve0_clk_priv {
42 struct nouveau_clock base; 42 struct nouveau_clk base;
43 struct nve0_clock_info eng[16]; 43 struct nve0_clk_info eng[16];
44}; 44};
45 45
46static u32 read_div(struct nve0_clock_priv *, int, u32, u32); 46static u32 read_div(struct nve0_clk_priv *, int, u32, u32);
47static u32 read_pll(struct nve0_clock_priv *, u32); 47static u32 read_pll(struct nve0_clk_priv *, u32);
48 48
49static u32 49static u32
50read_vco(struct nve0_clock_priv *priv, u32 dsrc) 50read_vco(struct nve0_clk_priv *priv, u32 dsrc)
51{ 51{
52 u32 ssrc = nv_rd32(priv, dsrc); 52 u32 ssrc = nv_rd32(priv, dsrc);
53 if (!(ssrc & 0x00000100)) 53 if (!(ssrc & 0x00000100))
@@ -56,7 +56,7 @@ read_vco(struct nve0_clock_priv *priv, u32 dsrc)
56} 56}
57 57
58static u32 58static u32
59read_pll(struct nve0_clock_priv *priv, u32 pll) 59read_pll(struct nve0_clk_priv *priv, u32 pll)
60{ 60{
61 u32 ctrl = nv_rd32(priv, pll + 0x00); 61 u32 ctrl = nv_rd32(priv, pll + 0x00);
62 u32 coef = nv_rd32(priv, pll + 0x04); 62 u32 coef = nv_rd32(priv, pll + 0x04);
@@ -101,7 +101,7 @@ read_pll(struct nve0_clock_priv *priv, u32 pll)
101} 101}
102 102
103static u32 103static u32
104read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) 104read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
105{ 105{
106 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); 106 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
107 u32 sctl = nv_rd32(priv, dctl + (doff * 4)); 107 u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -127,7 +127,7 @@ read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
127} 127}
128 128
129static u32 129static u32
130read_mem(struct nve0_clock_priv *priv) 130read_mem(struct nve0_clk_priv *priv)
131{ 131{
132 switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { 132 switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
133 case 1: return read_pll(priv, 0x132020); 133 case 1: return read_pll(priv, 0x132020);
@@ -138,7 +138,7 @@ read_mem(struct nve0_clock_priv *priv)
138} 138}
139 139
140static u32 140static u32
141read_clk(struct nve0_clock_priv *priv, int clk) 141read_clk(struct nve0_clk_priv *priv, int clk)
142{ 142{
143 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); 143 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
144 u32 sclk, sdiv; 144 u32 sclk, sdiv;
@@ -181,10 +181,10 @@ read_clk(struct nve0_clock_priv *priv, int clk)
181} 181}
182 182
183static int 183static int
184nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 184nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
185{ 185{
186 struct nouveau_device *device = nv_device(clk); 186 struct nouveau_device *device = nv_device(clk);
187 struct nve0_clock_priv *priv = (void *)clk; 187 struct nve0_clk_priv *priv = (void *)clk;
188 188
189 switch (src) { 189 switch (src) {
190 case nv_clk_src_crystal: 190 case nv_clk_src_crystal:
@@ -214,7 +214,7 @@ nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
214} 214}
215 215
216static u32 216static u32
217calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) 217calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
218{ 218{
219 u32 div = min((ref * 2) / freq, (u32)65); 219 u32 div = min((ref * 2) / freq, (u32)65);
220 if (div < 2) 220 if (div < 2)
@@ -225,7 +225,7 @@ calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
225} 225}
226 226
227static u32 227static u32
228calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) 228calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
229{ 229{
230 u32 sclk; 230 u32 sclk;
231 231
@@ -254,7 +254,7 @@ calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
254} 254}
255 255
256static u32 256static u32
257calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) 257calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
258{ 258{
259 struct nouveau_bios *bios = nouveau_bios(priv); 259 struct nouveau_bios *bios = nouveau_bios(priv);
260 struct nvbios_pll limits; 260 struct nvbios_pll limits;
@@ -277,10 +277,10 @@ calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
277} 277}
278 278
279static int 279static int
280calc_clk(struct nve0_clock_priv *priv, 280calc_clk(struct nve0_clk_priv *priv,
281 struct nouveau_cstate *cstate, int clk, int dom) 281 struct nouveau_cstate *cstate, int clk, int dom)
282{ 282{
283 struct nve0_clock_info *info = &priv->eng[clk]; 283 struct nve0_clk_info *info = &priv->eng[clk];
284 u32 freq = cstate->domain[dom]; 284 u32 freq = cstate->domain[dom];
285 u32 src0, div0, div1D, div1P = 0; 285 u32 src0, div0, div1D, div1P = 0;
286 u32 clk0, clk1 = 0; 286 u32 clk0, clk1 = 0;
@@ -329,9 +329,9 @@ calc_clk(struct nve0_clock_priv *priv,
329} 329}
330 330
331static int 331static int
332nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 332nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
333{ 333{
334 struct nve0_clock_priv *priv = (void *)clk; 334 struct nve0_clk_priv *priv = (void *)clk;
335 int ret; 335 int ret;
336 336
337 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || 337 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -347,9 +347,9 @@ nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
347} 347}
348 348
349static void 349static void
350nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) 350nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
351{ 351{
352 struct nve0_clock_info *info = &priv->eng[clk]; 352 struct nve0_clk_info *info = &priv->eng[clk];
353 if (!info->ssel) { 353 if (!info->ssel) {
354 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); 354 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
355 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); 355 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -357,22 +357,22 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
357} 357}
358 358
359static void 359static void
360nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk) 360nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk)
361{ 361{
362 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); 362 nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
363 nv_wait(priv, 0x137100, (1 << clk), 0x00000000); 363 nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
364} 364}
365 365
366static void 366static void
367nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk) 367nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk)
368{ 368{
369 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); 369 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
370} 370}
371 371
372static void 372static void
373nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) 373nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
374{ 374{
375 struct nve0_clock_info *info = &priv->eng[clk]; 375 struct nve0_clk_info *info = &priv->eng[clk];
376 const u32 addr = 0x137000 + (clk * 0x20); 376 const u32 addr = 0x137000 + (clk * 0x20);
377 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); 377 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
378 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); 378 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
@@ -385,9 +385,9 @@ nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
385} 385}
386 386
387static void 387static void
388nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) 388nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
389{ 389{
390 struct nve0_clock_info *info = &priv->eng[clk]; 390 struct nve0_clk_info *info = &priv->eng[clk];
391 if (info->ssel) 391 if (info->ssel)
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); 392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
393 else 393 else
@@ -395,9 +395,9 @@ nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
395} 395}
396 396
397static void 397static void
398nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) 398nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
399{ 399{
400 struct nve0_clock_info *info = &priv->eng[clk]; 400 struct nve0_clk_info *info = &priv->eng[clk];
401 if (info->ssel) { 401 if (info->ssel) {
402 nv_mask(priv, 0x137100, (1 << clk), info->ssel); 402 nv_mask(priv, 0x137100, (1 << clk), info->ssel);
403 nv_wait(priv, 0x137100, (1 << clk), info->ssel); 403 nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -405,9 +405,9 @@ nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
405} 405}
406 406
407static void 407static void
408nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) 408nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
409{ 409{
410 struct nve0_clock_info *info = &priv->eng[clk]; 410 struct nve0_clk_info *info = &priv->eng[clk];
411 if (info->ssel) { 411 if (info->ssel) {
412 nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); 412 nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
413 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); 413 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
@@ -415,20 +415,20 @@ nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
415} 415}
416 416
417static int 417static int
418nve0_clock_prog(struct nouveau_clock *clk) 418nve0_clk_prog(struct nouveau_clk *clk)
419{ 419{
420 struct nve0_clock_priv *priv = (void *)clk; 420 struct nve0_clk_priv *priv = (void *)clk;
421 struct { 421 struct {
422 u32 mask; 422 u32 mask;
423 void (*exec)(struct nve0_clock_priv *, int); 423 void (*exec)(struct nve0_clk_priv *, int);
424 } stage[] = { 424 } stage[] = {
425 { 0x007f, nve0_clock_prog_0 }, /* div programming */ 425 { 0x007f, nve0_clk_prog_0 }, /* div programming */
426 { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */ 426 { 0x007f, nve0_clk_prog_1_0 }, /* select div mode */
427 { 0xff80, nve0_clock_prog_1_1 }, 427 { 0xff80, nve0_clk_prog_1_1 },
428 { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ 428 { 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */
429 { 0xff80, nve0_clock_prog_3 }, /* final divider */ 429 { 0xff80, nve0_clk_prog_3 }, /* final divider */
430 { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */ 430 { 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */
431 { 0xff80, nve0_clock_prog_4_1 }, 431 { 0xff80, nve0_clk_prog_4_1 },
432 }; 432 };
433 int i, j; 433 int i, j;
434 434
@@ -446,13 +446,13 @@ nve0_clock_prog(struct nouveau_clock *clk)
446} 446}
447 447
448static void 448static void
449nve0_clock_tidy(struct nouveau_clock *clk) 449nve0_clk_tidy(struct nouveau_clk *clk)
450{ 450{
451 struct nve0_clock_priv *priv = (void *)clk; 451 struct nve0_clk_priv *priv = (void *)clk;
452 memset(priv->eng, 0x00, sizeof(priv->eng)); 452 memset(priv->eng, 0x00, sizeof(priv->eng));
453} 453}
454 454
455static struct nouveau_clocks 455static struct nouveau_domain
456nve0_domain[] = { 456nve0_domain[] = {
457 { nv_clk_src_crystal, 0xff }, 457 { nv_clk_src_crystal, 0xff },
458 { nv_clk_src_href , 0xff }, 458 { nv_clk_src_href , 0xff },
@@ -468,33 +468,33 @@ nve0_domain[] = {
468}; 468};
469 469
470static int 470static int
471nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 471nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
472 struct nouveau_oclass *oclass, void *data, u32 size, 472 struct nouveau_oclass *oclass, void *data, u32 size,
473 struct nouveau_object **pobject) 473 struct nouveau_object **pobject)
474{ 474{
475 struct nve0_clock_priv *priv; 475 struct nve0_clk_priv *priv;
476 int ret; 476 int ret;
477 477
478 ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0, 478 ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0,
479 true, &priv); 479 true, &priv);
480 *pobject = nv_object(priv); 480 *pobject = nv_object(priv);
481 if (ret) 481 if (ret)
482 return ret; 482 return ret;
483 483
484 priv->base.read = nve0_clock_read; 484 priv->base.read = nve0_clk_read;
485 priv->base.calc = nve0_clock_calc; 485 priv->base.calc = nve0_clk_calc;
486 priv->base.prog = nve0_clock_prog; 486 priv->base.prog = nve0_clk_prog;
487 priv->base.tidy = nve0_clock_tidy; 487 priv->base.tidy = nve0_clk_tidy;
488 return 0; 488 return 0;
489} 489}
490 490
491struct nouveau_oclass 491struct nouveau_oclass
492nve0_clock_oclass = { 492nve0_clk_oclass = {
493 .handle = NV_SUBDEV(CLOCK, 0xe0), 493 .handle = NV_SUBDEV(CLK, 0xe0),
494 .ofuncs = &(struct nouveau_ofuncs) { 494 .ofuncs = &(struct nouveau_ofuncs) {
495 .ctor = nve0_clock_ctor, 495 .ctor = nve0_clk_ctor,
496 .dtor = _nouveau_clock_dtor, 496 .dtor = _nouveau_clk_dtor,
497 .init = _nouveau_clock_init, 497 .init = _nouveau_clk_init,
498 .fini = _nouveau_clock_fini, 498 .fini = _nouveau_clk_fini,
499 }, 499 },
500}; 500};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
index 445b14c33a98..445b14c33a98 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
index b47d543ab2e3..b47d543ab2e3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
index 8eca457c2814..bc17fcc83bfe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <subdev/clock.h> 25#include <subdev/clk.h>
26#include <subdev/bios.h> 26#include <subdev/bios.h>
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28 28
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
index fb33f06ebd59..fb33f06ebd59 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
deleted file mode 100644
index f0a86021fbb1..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
+++ /dev/null
@@ -1,12 +0,0 @@
1nvkm-y += nvkm/subdev/clock/base.o
2nvkm-y += nvkm/subdev/clock/nv04.o
3nvkm-y += nvkm/subdev/clock/nv40.o
4nvkm-y += nvkm/subdev/clock/nv50.o
5nvkm-y += nvkm/subdev/clock/nv84.o
6nvkm-y += nvkm/subdev/clock/nva3.o
7nvkm-y += nvkm/subdev/clock/nvaa.o
8nvkm-y += nvkm/subdev/clock/nvc0.o
9nvkm-y += nvkm/subdev/clock/nve0.o
10nvkm-y += nvkm/subdev/clock/gk20a.o
11nvkm-y += nvkm/subdev/clock/pllnv04.o
12nvkm-y += nvkm/subdev/clock/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
deleted file mode 100644
index a45a1038b12f..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __NVKM_CLK_NVA3_H__
2#define __NVKM_CLK_NVA3_H__
3
4#include <subdev/clock.h>
5
6struct nva3_clock_info {
7 u32 clk;
8 u32 pll;
9 enum {
10 NVA3_HOST_277,
11 NVA3_HOST_CLK,
12 } host_out;
13 u32 fb_delay;
14};
15
16int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
17 struct nva3_clock_info *);
18int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
19void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
20#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
index cbcd51852472..7a768afba813 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
@@ -4,7 +4,7 @@
4#include <subdev/bios.h> 4#include <subdev/bios.h>
5#include <subdev/bios/pll.h> 5#include <subdev/bios/pll.h>
6#include <subdev/bios/init.h> 6#include <subdev/bios/init.h>
7#include <subdev/clock/pll.h> 7#include <subdev/clk/pll.h>
8#include <subdev/devinit.h> 8#include <subdev/devinit.h>
9 9
10struct nouveau_devinit_impl { 10struct nouveau_devinit_impl {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
index 7648beb11199..50cbc3804eaf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
@@ -26,8 +26,8 @@
26#include <subdev/bios/bit.h> 26#include <subdev/bios/bit.h>
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28#include <subdev/bios/init.h> 28#include <subdev/bios/init.h>
29#include <subdev/clock.h> 29#include <subdev/clk.h>
30#include <subdev/clock/pll.h> 30#include <subdev/clk/pll.h>
31#include <subdev/timer.h> 31#include <subdev/timer.h>
32 32
33#include <engine/fifo.h> 33#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 64a983c96625..8d2970c27715 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -27,7 +27,7 @@
27#include <subdev/bios/pll.h> 27#include <subdev/bios/pll.h>
28#include <subdev/bios/perf.h> 28#include <subdev/bios/perf.h>
29#include <subdev/bios/timing.h> 29#include <subdev/bios/timing.h>
30#include <subdev/clock/pll.h> 30#include <subdev/clk/pll.h>
31#include <subdev/fb.h> 31#include <subdev/fb.h>
32 32
33#include <core/option.h> 33#include <core/option.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
index 3b38a538845d..50e8dee513cc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
@@ -30,8 +30,8 @@
30#include <subdev/bios/M0205.h> 30#include <subdev/bios/M0205.h>
31#include <subdev/bios/timing.h> 31#include <subdev/bios/timing.h>
32 32
33#include <subdev/clock/nva3.h> 33#include <subdev/clk/nva3.h>
34#include <subdev/clock/pll.h> 34#include <subdev/clk/pll.h>
35 35
36#include <subdev/gpio.h> 36#include <subdev/gpio.h>
37 37
@@ -168,7 +168,7 @@ nva3_link_train(struct nouveau_fb *pfb)
168{ 168{
169 struct nouveau_bios *bios = nouveau_bios(pfb); 169 struct nouveau_bios *bios = nouveau_bios(pfb);
170 struct nva3_ram *ram = (void *)pfb->ram; 170 struct nva3_ram *ram = (void *)pfb->ram;
171 struct nouveau_clock *clk = nouveau_clock(pfb); 171 struct nouveau_clk *clk = nouveau_clk(pfb);
172 struct nva3_ltrain *train = &ram->ltrain; 172 struct nva3_ltrain *train = &ram->ltrain;
173 struct nouveau_device *device = nv_device(pfb); 173 struct nouveau_device *device = nv_device(pfb);
174 struct nva3_ramfuc *fuc = &ram->fuc; 174 struct nva3_ramfuc *fuc = &ram->fuc;
@@ -197,7 +197,7 @@ nva3_link_train(struct nouveau_fb *pfb)
197 197
198 clk_current = clk->read(clk, nv_clk_src_mem); 198 clk_current = clk->read(clk, nv_clk_src_mem);
199 199
200 ret = nva3_clock_pre(clk, f); 200 ret = nva3_clk_pre(clk, f);
201 if (ret) 201 if (ret)
202 goto out; 202 goto out;
203 203
@@ -252,7 +252,7 @@ nva3_link_train(struct nouveau_fb *pfb)
252 nv_mask(pfb, 0x616308, 0x10, 0x10); 252 nv_mask(pfb, 0x616308, 0x10, 0x10);
253 nv_mask(pfb, 0x616b08, 0x10, 0x10); 253 nv_mask(pfb, 0x616b08, 0x10, 0x10);
254 254
255 nva3_clock_post(clk, f); 255 nva3_clk_post(clk, f);
256 256
257 ram_train_result(pfb, result, 64); 257 ram_train_result(pfb, result, 64);
258 for (i = 0; i < 64; i++) 258 for (i = 0; i < 64; i++)
@@ -274,7 +274,7 @@ out:
274 274
275 train->state = NVA3_TRAIN_UNSUPPORTED; 275 train->state = NVA3_TRAIN_UNSUPPORTED;
276 276
277 nva3_clock_post(clk, f); 277 nva3_clk_post(clk, f);
278 return ret; 278 return ret;
279} 279}
280 280
@@ -465,7 +465,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
465} 465}
466 466
467static void 467static void
468nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk) 468nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
469{ 469{
470 ram_wr32(fuc, 0x004004, mclk->pll); 470 ram_wr32(fuc, 0x004004, mclk->pll);
471 ram_mask(fuc, 0x004000, 0x00000001, 0x00000001); 471 ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
@@ -504,7 +504,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
504 struct nva3_ram *ram = (void *)pfb->ram; 504 struct nva3_ram *ram = (void *)pfb->ram;
505 struct nva3_ramfuc *fuc = &ram->fuc; 505 struct nva3_ramfuc *fuc = &ram->fuc;
506 struct nva3_ltrain *train = &ram->ltrain; 506 struct nva3_ltrain *train = &ram->ltrain;
507 struct nva3_clock_info mclk; 507 struct nva3_clk_info mclk;
508 struct nouveau_ram_data *next; 508 struct nouveau_ram_data *next;
509 u8 ver, hdr, cnt, len, strap; 509 u8 ver, hdr, cnt, len, strap;
510 u32 data; 510 u32 data;
@@ -555,7 +555,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
555 } 555 }
556 } 556 }
557 557
558 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); 558 ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk);
559 if (ret < 0) { 559 if (ret < 0) {
560 nv_error(pfb, "failed mclk calculation\n"); 560 nv_error(pfb, "failed mclk calculation\n");
561 return ret; 561 return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
index 735cb9580abe..d08eacd580d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
@@ -28,8 +28,8 @@
28#include <subdev/bios/timing.h> 28#include <subdev/bios/timing.h>
29#include <subdev/ltc.h> 29#include <subdev/ltc.h>
30 30
31#include <subdev/clock.h> 31#include <subdev/clk.h>
32#include <subdev/clock/pll.h> 32#include <subdev/clk/pll.h>
33 33
34#include <core/option.h> 34#include <core/option.h>
35 35
@@ -129,7 +129,7 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
129static int 129static int
130nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) 130nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
131{ 131{
132 struct nouveau_clock *clk = nouveau_clock(pfb); 132 struct nouveau_clk *clk = nouveau_clk(pfb);
133 struct nouveau_bios *bios = nouveau_bios(pfb); 133 struct nouveau_bios *bios = nouveau_bios(pfb);
134 struct nvc0_ram *ram = (void *)pfb->ram; 134 struct nvc0_ram *ram = (void *)pfb->ram;
135 struct nvc0_ramfuc *fuc = &ram->fuc; 135 struct nvc0_ramfuc *fuc = &ram->fuc;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
index 6bae474abb44..60050aab84b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
@@ -32,8 +32,8 @@
32#include <subdev/bios/M0205.h> 32#include <subdev/bios/M0205.h>
33#include <subdev/bios/M0209.h> 33#include <subdev/bios/M0209.h>
34 34
35#include <subdev/clock.h> 35#include <subdev/clk.h>
36#include <subdev/clock/pll.h> 36#include <subdev/clk/pll.h>
37 37
38#include <subdev/timer.h> 38#include <subdev/timer.h>
39 39
@@ -1033,7 +1033,7 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
1033static int 1033static int
1034nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) 1034nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
1035{ 1035{
1036 struct nouveau_clock *clk = nouveau_clock(pfb); 1036 struct nouveau_clk *clk = nouveau_clk(pfb);
1037 struct nve0_ram *ram = (void *)pfb->ram; 1037 struct nve0_ram *ram = (void *)pfb->ram;
1038 struct nouveau_ram_data *xits = &ram->base.xition; 1038 struct nouveau_ram_data *xits = &ram->base.xition;
1039 struct nouveau_ram_data *copy; 1039 struct nouveau_ram_data *copy;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
index f6b7df1b1686..a4e3a9b57306 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
@@ -21,7 +21,7 @@
21 */ 21 */
22#include "priv.h" 22#include "priv.h"
23 23
24#include <subdev/clock.h> 24#include <subdev/clk.h>
25#include <subdev/timer.h> 25#include <subdev/timer.h>
26#include <subdev/volt.h> 26#include <subdev/volt.h>
27 27
@@ -50,15 +50,15 @@ struct gk20a_pwr_dvfs_dev_status {
50static int 50static int
51gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state) 51gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
52{ 52{
53 struct nouveau_clock *clk = nouveau_clock(priv); 53 struct nouveau_clk *clk = nouveau_clk(priv);
54 54
55 return nouveau_clock_astate(clk, *state, 0, false); 55 return nouveau_clk_astate(clk, *state, 0, false);
56} 56}
57 57
58static int 58static int
59gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state) 59gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
60{ 60{
61 struct nouveau_clock *clk = nouveau_clock(priv); 61 struct nouveau_clk *clk = nouveau_clk(priv);
62 62
63 *state = clk->pstate; 63 *state = clk->pstate;
64 return 0; 64 return 0;
@@ -69,7 +69,7 @@ gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
69 int *state, int load) 69 int *state, int load)
70{ 70{
71 struct gk20a_pwr_dvfs_data *data = priv->data; 71 struct gk20a_pwr_dvfs_data *data = priv->data;
72 struct nouveau_clock *clk = nouveau_clock(priv); 72 struct nouveau_clk *clk = nouveau_clk(priv);
73 int cur_level, level; 73 int cur_level, level;
74 74
75 /* For GK20A, the performance level is directly mapped to pstate */ 75 /* For GK20A, the performance level is directly mapped to pstate */
@@ -117,7 +117,7 @@ gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
117 struct gk20a_pwr_priv, alarm); 117 struct gk20a_pwr_priv, alarm);
118 struct gk20a_pwr_dvfs_data *data = priv->data; 118 struct gk20a_pwr_dvfs_data *data = priv->data;
119 struct gk20a_pwr_dvfs_dev_status status; 119 struct gk20a_pwr_dvfs_dev_status status;
120 struct nouveau_clock *clk = nouveau_clock(priv); 120 struct nouveau_clk *clk = nouveau_clk(priv);
121 struct nouveau_volt *volt = nouveau_volt(priv); 121 struct nouveau_volt *volt = nouveau_volt(priv);
122 u32 utilization = 0; 122 u32 utilization = 0;
123 int state, ret; 123 int state, ret;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 14:39:34 -0400