diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2014-02-20 06:11:30 -0500 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-21 23:10:52 -0500 |
commit | f327d43da130fe6a4a0b3ecf6ad27eff7fd92877 (patch) | |
tree | 17fb2dc21f4279d52d64c2c01b5288b5c1603cc5 | |
parent | a2be1561a3f6ea5e7ffb1ce42c0db9cb1bc7ab28 (diff) |
ARM: mvebu: use GIC_{SPI,PPI} in Armada 375/38x DTs
Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts,
use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to
clarify the Device Tree code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r-- | arch/arm/boot/dts/armada-375.dtsi | 53 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-380.dtsi | 6 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-385.dtsi | 8 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 41 |
4 files changed, 55 insertions, 53 deletions
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c89fee488319..23d497f3f3bc 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi | |||
@@ -12,6 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include "skeleton.dtsi" | 14 | #include "skeleton.dtsi" |
15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
15 | 16 | ||
16 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | 17 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
17 | 18 | ||
@@ -129,7 +130,7 @@ | |||
129 | timer@c600 { | 130 | timer@c600 { |
130 | compatible = "arm,cortex-a9-twd-timer"; | 131 | compatible = "arm,cortex-a9-twd-timer"; |
131 | reg = <0xc600 0x20>; | 132 | reg = <0xc600 0x20>; |
132 | interrupts = <1 13 0x301>; | 133 | interrupts = <GIC_PPI 13 0x301>; |
133 | clocks = <&coreclk 2>; | 134 | clocks = <&coreclk 2>; |
134 | }; | 135 | }; |
135 | 136 | ||
@@ -148,7 +149,7 @@ | |||
148 | #address-cells = <1>; | 149 | #address-cells = <1>; |
149 | #size-cells = <0>; | 150 | #size-cells = <0>; |
150 | cell-index = <0>; | 151 | cell-index = <0>; |
151 | interrupts = <0 1 0x4>; | 152 | interrupts = <GIC_SPI 1 0x4>; |
152 | clocks = <&coreclk 0>; | 153 | clocks = <&coreclk 0>; |
153 | status = "disabled"; | 154 | status = "disabled"; |
154 | }; | 155 | }; |
@@ -159,7 +160,7 @@ | |||
159 | #address-cells = <1>; | 160 | #address-cells = <1>; |
160 | #size-cells = <0>; | 161 | #size-cells = <0>; |
161 | cell-index = <1>; | 162 | cell-index = <1>; |
162 | interrupts = <0 63 0x4>; | 163 | interrupts = <GIC_SPI 63 0x4>; |
163 | clocks = <&coreclk 0>; | 164 | clocks = <&coreclk 0>; |
164 | status = "disabled"; | 165 | status = "disabled"; |
165 | }; | 166 | }; |
@@ -169,7 +170,7 @@ | |||
169 | reg = <0x11000 0x20>; | 170 | reg = <0x11000 0x20>; |
170 | #address-cells = <1>; | 171 | #address-cells = <1>; |
171 | #size-cells = <0>; | 172 | #size-cells = <0>; |
172 | interrupts = <0 2 0x4>; | 173 | interrupts = <GIC_SPI 2 0x4>; |
173 | timeout-ms = <1000>; | 174 | timeout-ms = <1000>; |
174 | clocks = <&coreclk 0>; | 175 | clocks = <&coreclk 0>; |
175 | status = "disabled"; | 176 | status = "disabled"; |
@@ -180,7 +181,7 @@ | |||
180 | reg = <0x11100 0x20>; | 181 | reg = <0x11100 0x20>; |
181 | #address-cells = <1>; | 182 | #address-cells = <1>; |
182 | #size-cells = <0>; | 183 | #size-cells = <0>; |
183 | interrupts = <0 3 0x4>; | 184 | interrupts = <GIC_SPI 3 0x4>; |
184 | timeout-ms = <1000>; | 185 | timeout-ms = <1000>; |
185 | clocks = <&coreclk 0>; | 186 | clocks = <&coreclk 0>; |
186 | status = "disabled"; | 187 | status = "disabled"; |
@@ -190,7 +191,7 @@ | |||
190 | compatible = "snps,dw-apb-uart"; | 191 | compatible = "snps,dw-apb-uart"; |
191 | reg = <0x12000 0x100>; | 192 | reg = <0x12000 0x100>; |
192 | reg-shift = <2>; | 193 | reg-shift = <2>; |
193 | interrupts = <0 12 4>; | 194 | interrupts = <GIC_SPI 12 4>; |
194 | reg-io-width = <1>; | 195 | reg-io-width = <1>; |
195 | status = "disabled"; | 196 | status = "disabled"; |
196 | }; | 197 | }; |
@@ -199,7 +200,7 @@ | |||
199 | compatible = "snps,dw-apb-uart"; | 200 | compatible = "snps,dw-apb-uart"; |
200 | reg = <0x12100 0x100>; | 201 | reg = <0x12100 0x100>; |
201 | reg-shift = <2>; | 202 | reg-shift = <2>; |
202 | interrupts = <0 13 4>; | 203 | interrupts = <GIC_SPI 13 4>; |
203 | reg-io-width = <1>; | 204 | reg-io-width = <1>; |
204 | status = "disabled"; | 205 | status = "disabled"; |
205 | }; | 206 | }; |
@@ -248,8 +249,8 @@ | |||
248 | #gpio-cells = <2>; | 249 | #gpio-cells = <2>; |
249 | interrupt-controller; | 250 | interrupt-controller; |
250 | #interrupt-cells = <2>; | 251 | #interrupt-cells = <2>; |
251 | interrupts = <0 53 0x4>, <0 54 0x4>, | 252 | interrupts = <GIC_SPI 53 0x4>, <GIC_SPI 54 0x4>, |
252 | <0 55 0x4>, <0 56 0x4>; | 253 | <GIC_SPI 55 0x4>, <GIC_SPI 56 0x4>; |
253 | }; | 254 | }; |
254 | 255 | ||
255 | gpio1: gpio@18140 { | 256 | gpio1: gpio@18140 { |
@@ -260,8 +261,8 @@ | |||
260 | #gpio-cells = <2>; | 261 | #gpio-cells = <2>; |
261 | interrupt-controller; | 262 | interrupt-controller; |
262 | #interrupt-cells = <2>; | 263 | #interrupt-cells = <2>; |
263 | interrupts = <0 58 0x4>, <0 59 0x4>, | 264 | interrupts = <GIC_SPI 58 0x4>, <GIC_SPI 59 0x4>, |
264 | <0 60 0x4>, <0 61 0x4>; | 265 | <GIC_SPI 60 0x4>, <GIC_SPI 61 0x4>; |
265 | }; | 266 | }; |
266 | 267 | ||
267 | gpio2: gpio@18180 { | 268 | gpio2: gpio@18180 { |
@@ -272,7 +273,7 @@ | |||
272 | #gpio-cells = <2>; | 273 | #gpio-cells = <2>; |
273 | interrupt-controller; | 274 | interrupt-controller; |
274 | #interrupt-cells = <2>; | 275 | #interrupt-cells = <2>; |
275 | interrupts = <0 62 0x4>; | 276 | interrupts = <GIC_SPI 62 0x4>; |
276 | }; | 277 | }; |
277 | 278 | ||
278 | system-controller@18200 { | 279 | system-controller@18200 { |
@@ -299,16 +300,16 @@ | |||
299 | #size-cells = <1>; | 300 | #size-cells = <1>; |
300 | interrupt-controller; | 301 | interrupt-controller; |
301 | msi-controller; | 302 | msi-controller; |
302 | interrupts = <1 15 0x4>; | 303 | interrupts = <GIC_PPI 15 0x4>; |
303 | }; | 304 | }; |
304 | 305 | ||
305 | timer@20300 { | 306 | timer@20300 { |
306 | compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; | 307 | compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; |
307 | reg = <0x20300 0x30>, <0x21040 0x30>; | 308 | reg = <0x20300 0x30>, <0x21040 0x30>; |
308 | interrupts-extended = <&gic 0 8 4>, | 309 | interrupts-extended = <&gic GIC_SPI 8 4>, |
309 | <&gic 0 9 4>, | 310 | <&gic GIC_SPI 9 4>, |
310 | <&gic 0 10 4>, | 311 | <&gic GIC_SPI 10 4>, |
311 | <&gic 0 11 4>, | 312 | <&gic GIC_SPI 11 4>, |
312 | <&mpic 5>, | 313 | <&mpic 5>, |
313 | <&mpic 6>; | 314 | <&mpic 6>; |
314 | clocks = <&coreclk 0>; | 315 | clocks = <&coreclk 0>; |
@@ -322,12 +323,12 @@ | |||
322 | status = "okay"; | 323 | status = "okay"; |
323 | 324 | ||
324 | xor00 { | 325 | xor00 { |
325 | interrupts = <0 22 0x4>; | 326 | interrupts = <GIC_SPI 22 0x4>; |
326 | dmacap,memcpy; | 327 | dmacap,memcpy; |
327 | dmacap,xor; | 328 | dmacap,xor; |
328 | }; | 329 | }; |
329 | xor01 { | 330 | xor01 { |
330 | interrupts = <0 23 0x4>; | 331 | interrupts = <GIC_SPI 23 0x4>; |
331 | dmacap,memcpy; | 332 | dmacap,memcpy; |
332 | dmacap,xor; | 333 | dmacap,xor; |
333 | dmacap,memset; | 334 | dmacap,memset; |
@@ -342,12 +343,12 @@ | |||
342 | status = "okay"; | 343 | status = "okay"; |
343 | 344 | ||
344 | xor10 { | 345 | xor10 { |
345 | interrupts = <0 65 0x4>; | 346 | interrupts = <GIC_SPI 65 0x4>; |
346 | dmacap,memcpy; | 347 | dmacap,memcpy; |
347 | dmacap,xor; | 348 | dmacap,xor; |
348 | }; | 349 | }; |
349 | xor11 { | 350 | xor11 { |
350 | interrupts = <0 66 0x4>; | 351 | interrupts = <GIC_SPI 66 0x4>; |
351 | dmacap,memcpy; | 352 | dmacap,memcpy; |
352 | dmacap,xor; | 353 | dmacap,xor; |
353 | dmacap,memset; | 354 | dmacap,memset; |
@@ -357,7 +358,7 @@ | |||
357 | sata@a0000 { | 358 | sata@a0000 { |
358 | compatible = "marvell,orion-sata"; | 359 | compatible = "marvell,orion-sata"; |
359 | reg = <0xa0000 0x5000>; | 360 | reg = <0xa0000 0x5000>; |
360 | interrupts = <0 26 0x4>; | 361 | interrupts = <GIC_SPI 26 0x4>; |
361 | clocks = <&gateclk 14>, <&gateclk 20>; | 362 | clocks = <&gateclk 14>, <&gateclk 20>; |
362 | clock-names = "0", "1"; | 363 | clock-names = "0", "1"; |
363 | status = "disabled"; | 364 | status = "disabled"; |
@@ -368,7 +369,7 @@ | |||
368 | reg = <0xd0000 0x54>; | 369 | reg = <0xd0000 0x54>; |
369 | #address-cells = <1>; | 370 | #address-cells = <1>; |
370 | #size-cells = <1>; | 371 | #size-cells = <1>; |
371 | interrupts = <0 84 0x4>; | 372 | interrupts = <GIC_SPI 84 0x4>; |
372 | clocks = <&gateclk 11>; | 373 | clocks = <&gateclk 11>; |
373 | status = "disabled"; | 374 | status = "disabled"; |
374 | }; | 375 | }; |
@@ -376,7 +377,7 @@ | |||
376 | mvsdio@d4000 { | 377 | mvsdio@d4000 { |
377 | compatible = "marvell,orion-sdio"; | 378 | compatible = "marvell,orion-sdio"; |
378 | reg = <0xd4000 0x200>; | 379 | reg = <0xd4000 0x200>; |
379 | interrupts = <0 25 0x4>; | 380 | interrupts = <GIC_SPI 25 0x4>; |
380 | clocks = <&gateclk 17>; | 381 | clocks = <&gateclk 17>; |
381 | bus-width = <4>; | 382 | bus-width = <4>; |
382 | cap-sdio-irq; | 383 | cap-sdio-irq; |
@@ -429,7 +430,7 @@ | |||
429 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | 430 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
430 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | 431 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
431 | interrupt-map-mask = <0 0 0 0>; | 432 | interrupt-map-mask = <0 0 0 0>; |
432 | interrupt-map = <0 0 0 0 &gic 0 29 0x4>; | 433 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; |
433 | marvell,pcie-port = <0>; | 434 | marvell,pcie-port = <0>; |
434 | marvell,pcie-lane = <0>; | 435 | marvell,pcie-lane = <0>; |
435 | clocks = <&gateclk 5>; | 436 | clocks = <&gateclk 5>; |
@@ -446,7 +447,7 @@ | |||
446 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | 447 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
447 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | 448 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
448 | interrupt-map-mask = <0 0 0 0>; | 449 | interrupt-map-mask = <0 0 0 0>; |
449 | interrupt-map = <0 0 0 0 &gic 0 33 0x4>; | 450 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; |
450 | marvell,pcie-port = <0>; | 451 | marvell,pcie-port = <0>; |
451 | marvell,pcie-lane = <1>; | 452 | marvell,pcie-lane = <1>; |
452 | clocks = <&gateclk 6>; | 453 | clocks = <&gateclk 6>; |
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 82b33473a146..678ba3d0c485 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi | |||
@@ -70,7 +70,7 @@ | |||
70 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | 70 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
71 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | 71 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
72 | interrupt-map-mask = <0 0 0 0>; | 72 | interrupt-map-mask = <0 0 0 0>; |
73 | interrupt-map = <0 0 0 0 &gic 0 29 0x4>; | 73 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; |
74 | marvell,pcie-port = <0>; | 74 | marvell,pcie-port = <0>; |
75 | marvell,pcie-lane = <0>; | 75 | marvell,pcie-lane = <0>; |
76 | clocks = <&gateclk 8>; | 76 | clocks = <&gateclk 8>; |
@@ -88,7 +88,7 @@ | |||
88 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | 88 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
89 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | 89 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
90 | interrupt-map-mask = <0 0 0 0>; | 90 | interrupt-map-mask = <0 0 0 0>; |
91 | interrupt-map = <0 0 0 0 &gic 0 33 0x4>; | 91 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; |
92 | marvell,pcie-port = <1>; | 92 | marvell,pcie-port = <1>; |
93 | marvell,pcie-lane = <0>; | 93 | marvell,pcie-lane = <0>; |
94 | clocks = <&gateclk 5>; | 94 | clocks = <&gateclk 5>; |
@@ -106,7 +106,7 @@ | |||
106 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | 106 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 |
107 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | 107 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; |
108 | interrupt-map-mask = <0 0 0 0>; | 108 | interrupt-map-mask = <0 0 0 0>; |
109 | interrupt-map = <0 0 0 0 &gic 0 70 0x4>; | 109 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; |
110 | marvell,pcie-port = <2>; | 110 | marvell,pcie-port = <2>; |
111 | marvell,pcie-lane = <0>; | 111 | marvell,pcie-lane = <0>; |
112 | clocks = <&gateclk 6>; | 112 | clocks = <&gateclk 6>; |
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index b22f5f1bd337..055bc2f1c051 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi | |||
@@ -81,7 +81,7 @@ | |||
81 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | 81 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
82 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | 82 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
83 | interrupt-map-mask = <0 0 0 0>; | 83 | interrupt-map-mask = <0 0 0 0>; |
84 | interrupt-map = <0 0 0 0 &gic 0 29 0x4>; | 84 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>; |
85 | marvell,pcie-port = <0>; | 85 | marvell,pcie-port = <0>; |
86 | marvell,pcie-lane = <0>; | 86 | marvell,pcie-lane = <0>; |
87 | clocks = <&gateclk 8>; | 87 | clocks = <&gateclk 8>; |
@@ -99,7 +99,7 @@ | |||
99 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | 99 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
100 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | 100 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
101 | interrupt-map-mask = <0 0 0 0>; | 101 | interrupt-map-mask = <0 0 0 0>; |
102 | interrupt-map = <0 0 0 0 &gic 0 33 0x4>; | 102 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>; |
103 | marvell,pcie-port = <1>; | 103 | marvell,pcie-port = <1>; |
104 | marvell,pcie-lane = <0>; | 104 | marvell,pcie-lane = <0>; |
105 | clocks = <&gateclk 5>; | 105 | clocks = <&gateclk 5>; |
@@ -117,7 +117,7 @@ | |||
117 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | 117 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 |
118 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | 118 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; |
119 | interrupt-map-mask = <0 0 0 0>; | 119 | interrupt-map-mask = <0 0 0 0>; |
120 | interrupt-map = <0 0 0 0 &gic 0 70 0x4>; | 120 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>; |
121 | marvell,pcie-port = <2>; | 121 | marvell,pcie-port = <2>; |
122 | marvell,pcie-lane = <0>; | 122 | marvell,pcie-lane = <0>; |
123 | clocks = <&gateclk 6>; | 123 | clocks = <&gateclk 6>; |
@@ -138,7 +138,7 @@ | |||
138 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | 138 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 |
139 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | 139 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; |
140 | interrupt-map-mask = <0 0 0 0>; | 140 | interrupt-map-mask = <0 0 0 0>; |
141 | interrupt-map = <0 0 0 0 &gic 0 71 0x4>; | 141 | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 0x4>; |
142 | marvell,pcie-port = <3>; | 142 | marvell,pcie-port = <3>; |
143 | marvell,pcie-lane = <0>; | 143 | marvell,pcie-lane = <0>; |
144 | clocks = <&gateclk 7>; | 144 | clocks = <&gateclk 7>; |
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 5a10248f4bb9..502d21ae7b61 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi | |||
@@ -13,6 +13,7 @@ | |||
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include "skeleton.dtsi" | 15 | #include "skeleton.dtsi" |
16 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
16 | 17 | ||
17 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | 18 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
18 | 19 | ||
@@ -109,7 +110,7 @@ | |||
109 | timer@c600 { | 110 | timer@c600 { |
110 | compatible = "arm,cortex-a9-twd-timer"; | 111 | compatible = "arm,cortex-a9-twd-timer"; |
111 | reg = <0xc600 0x20>; | 112 | reg = <0xc600 0x20>; |
112 | interrupts = <1 13 0x301>; | 113 | interrupts = <GIC_PPI 13 0x301>; |
113 | clocks = <&coreclk 2>; | 114 | clocks = <&coreclk 2>; |
114 | }; | 115 | }; |
115 | 116 | ||
@@ -128,7 +129,7 @@ | |||
128 | #address-cells = <1>; | 129 | #address-cells = <1>; |
129 | #size-cells = <0>; | 130 | #size-cells = <0>; |
130 | cell-index = <0>; | 131 | cell-index = <0>; |
131 | interrupts = <0 1 0x4>; | 132 | interrupts = <GIC_SPI 1 0x4>; |
132 | clocks = <&coreclk 0>; | 133 | clocks = <&coreclk 0>; |
133 | status = "disabled"; | 134 | status = "disabled"; |
134 | }; | 135 | }; |
@@ -139,7 +140,7 @@ | |||
139 | #address-cells = <1>; | 140 | #address-cells = <1>; |
140 | #size-cells = <0>; | 141 | #size-cells = <0>; |
141 | cell-index = <1>; | 142 | cell-index = <1>; |
142 | interrupts = <0 63 0x4>; | 143 | interrupts = <GIC_SPI 63 0x4>; |
143 | clocks = <&coreclk 0>; | 144 | clocks = <&coreclk 0>; |
144 | status = "disabled"; | 145 | status = "disabled"; |
145 | }; | 146 | }; |
@@ -149,7 +150,7 @@ | |||
149 | reg = <0x11000 0x20>; | 150 | reg = <0x11000 0x20>; |
150 | #address-cells = <1>; | 151 | #address-cells = <1>; |
151 | #size-cells = <0>; | 152 | #size-cells = <0>; |
152 | interrupts = <0 2 0x4>; | 153 | interrupts = <GIC_SPI 2 0x4>; |
153 | timeout-ms = <1000>; | 154 | timeout-ms = <1000>; |
154 | clocks = <&coreclk 0>; | 155 | clocks = <&coreclk 0>; |
155 | status = "disabled"; | 156 | status = "disabled"; |
@@ -160,7 +161,7 @@ | |||
160 | reg = <0x11100 0x20>; | 161 | reg = <0x11100 0x20>; |
161 | #address-cells = <1>; | 162 | #address-cells = <1>; |
162 | #size-cells = <0>; | 163 | #size-cells = <0>; |
163 | interrupts = <0 3 0x4>; | 164 | interrupts = <GIC_SPI 3 0x4>; |
164 | timeout-ms = <1000>; | 165 | timeout-ms = <1000>; |
165 | clocks = <&coreclk 0>; | 166 | clocks = <&coreclk 0>; |
166 | status = "disabled"; | 167 | status = "disabled"; |
@@ -170,7 +171,7 @@ | |||
170 | compatible = "snps,dw-apb-uart"; | 171 | compatible = "snps,dw-apb-uart"; |
171 | reg = <0x12000 0x100>; | 172 | reg = <0x12000 0x100>; |
172 | reg-shift = <2>; | 173 | reg-shift = <2>; |
173 | interrupts = <0 12 4>; | 174 | interrupts = <GIC_SPI 12 4>; |
174 | reg-io-width = <1>; | 175 | reg-io-width = <1>; |
175 | status = "disabled"; | 176 | status = "disabled"; |
176 | }; | 177 | }; |
@@ -179,7 +180,7 @@ | |||
179 | compatible = "snps,dw-apb-uart"; | 180 | compatible = "snps,dw-apb-uart"; |
180 | reg = <0x12100 0x100>; | 181 | reg = <0x12100 0x100>; |
181 | reg-shift = <2>; | 182 | reg-shift = <2>; |
182 | interrupts = <0 13 4>; | 183 | interrupts = <GIC_SPI 13 4>; |
183 | reg-io-width = <1>; | 184 | reg-io-width = <1>; |
184 | status = "disabled"; | 185 | status = "disabled"; |
185 | }; | 186 | }; |
@@ -197,8 +198,8 @@ | |||
197 | #gpio-cells = <2>; | 198 | #gpio-cells = <2>; |
198 | interrupt-controller; | 199 | interrupt-controller; |
199 | #interrupt-cells = <2>; | 200 | #interrupt-cells = <2>; |
200 | interrupts = <0 53 0x4>, <0 54 0x4>, | 201 | interrupts = <GIC_SPI 53 0x4>, <GIC_SPI 54 0x4>, |
201 | <0 55 0x4>, <0 56 0x4>; | 202 | <GIC_SPI 55 0x4>, <GIC_SPI 56 0x4>; |
202 | }; | 203 | }; |
203 | 204 | ||
204 | gpio1: gpio@18140 { | 205 | gpio1: gpio@18140 { |
@@ -209,8 +210,8 @@ | |||
209 | #gpio-cells = <2>; | 210 | #gpio-cells = <2>; |
210 | interrupt-controller; | 211 | interrupt-controller; |
211 | #interrupt-cells = <2>; | 212 | #interrupt-cells = <2>; |
212 | interrupts = <0 58 0x4>, <0 59 0x4>, | 213 | interrupts = <GIC_SPI 58 0x4>, <GIC_SPI 59 0x4>, |
213 | <0 60 0x4>, <0 61 0x4>; | 214 | <GIC_SPI 60 0x4>, <GIC_SPI 61 0x4>; |
214 | }; | 215 | }; |
215 | 216 | ||
216 | system-controller@18200 { | 217 | system-controller@18200 { |
@@ -244,17 +245,17 @@ | |||
244 | #size-cells = <1>; | 245 | #size-cells = <1>; |
245 | interrupt-controller; | 246 | interrupt-controller; |
246 | msi-controller; | 247 | msi-controller; |
247 | interrupts = <1 15 0x4>; | 248 | interrupts = <GIC_PPI 15 0x4>; |
248 | }; | 249 | }; |
249 | 250 | ||
250 | timer@20300 { | 251 | timer@20300 { |
251 | compatible = "marvell,armada-380-timer", | 252 | compatible = "marvell,armada-380-timer", |
252 | "marvell,armada-xp-timer"; | 253 | "marvell,armada-xp-timer"; |
253 | reg = <0x20300 0x30>, <0x21040 0x30>; | 254 | reg = <0x20300 0x30>, <0x21040 0x30>; |
254 | interrupts-extended = <&gic 0 8 4>, | 255 | interrupts-extended = <&gic GIC_SPI 8 4>, |
255 | <&gic 0 9 4>, | 256 | <&gic GIC_SPI 9 4>, |
256 | <&gic 0 10 4>, | 257 | <&gic GIC_SPI 10 4>, |
257 | <&gic 0 11 4>, | 258 | <&gic GIC_SPI 11 4>, |
258 | <&mpic 5>, | 259 | <&mpic 5>, |
259 | <&mpic 6>; | 260 | <&mpic 6>; |
260 | clocks = <&coreclk 2>, <&refclk>; | 261 | clocks = <&coreclk 2>, <&refclk>; |
@@ -285,12 +286,12 @@ | |||
285 | status = "okay"; | 286 | status = "okay"; |
286 | 287 | ||
287 | xor00 { | 288 | xor00 { |
288 | interrupts = <0 22 0x4>; | 289 | interrupts = <GIC_SPI 22 0x4>; |
289 | dmacap,memcpy; | 290 | dmacap,memcpy; |
290 | dmacap,xor; | 291 | dmacap,xor; |
291 | }; | 292 | }; |
292 | xor01 { | 293 | xor01 { |
293 | interrupts = <0 23 0x4>; | 294 | interrupts = <GIC_SPI 23 0x4>; |
294 | dmacap,memcpy; | 295 | dmacap,memcpy; |
295 | dmacap,xor; | 296 | dmacap,xor; |
296 | dmacap,memset; | 297 | dmacap,memset; |
@@ -305,12 +306,12 @@ | |||
305 | status = "okay"; | 306 | status = "okay"; |
306 | 307 | ||
307 | xor10 { | 308 | xor10 { |
308 | interrupts = <0 65 0x4>; | 309 | interrupts = <GIC_SPI 65 0x4>; |
309 | dmacap,memcpy; | 310 | dmacap,memcpy; |
310 | dmacap,xor; | 311 | dmacap,xor; |
311 | }; | 312 | }; |
312 | xor11 { | 313 | xor11 { |
313 | interrupts = <0 66 0x4>; | 314 | interrupts = <GIC_SPI 66 0x4>; |
314 | dmacap,memcpy; | 315 | dmacap,memcpy; |
315 | dmacap,xor; | 316 | dmacap,xor; |
316 | dmacap,memset; | 317 | dmacap,memset; |