m68knommu: move ColdFire PIT timer base addresses

The PIT hardware timer module used in some ColdFire CPU's is not always
addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and
5208 have fixed peripheral addresses. So lets not define the register
addresses of the PIT relative to an IPSBAR definition. Move the base
address definitions into the per-part headers. This is a lot more consistent
since all the other peripheral base addresses are defined in the per-part
header files already.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

6 files changed, 32 insertions, 20 deletions

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..afc21ad78f43 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -134,6 +134,12 @@
 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
 
 /*
+ *  PIT timer module.
+ */
+#define MCFPIT_BASE1            0xFC080000      /* Base address of TIMER1 */
+#define MCFPIT_BASE2            0xFC084000      /* Base address of TIMER2 */
+
+/*
  *  UART module.
  */
 #define MCFUART_BASE1           0x60000         /* Base address of UART1 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 9701ed34d234..6be94f6831ae 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -119,9 +119,16 @@
 #define MCFGPIO_PCLRR_ETPU      (MCF_IPSBAR + 0x10003C)
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
 #define MCFEPORT_EPDDR          (MCF_IPSBAR + 0x130002)
 #define MCFEPORT_EPDR           (MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR          (MCF_IPSBAR + 0x130005)
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 3712f611bd5e..cb7df04ad0c4 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -232,15 +232,20 @@
 #endif
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
 #define MCFEPORT_EPDDR          (MCF_IPSBAR + 0x130002)
 #define MCFEPORT_EPDR           (MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR          (MCF_IPSBAR + 0x130005)
 
-
-
 /*
  *      GPIO pins setups to enable the UARTs.
  */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a918545f6a5a..014098a7de89 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -164,6 +164,14 @@
 #define MCFGPIO_PUAPAR          (MCF_IPSBAR + 0x0010005C)
 
 /*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x00150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x00160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x00170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x00180000)
+
+/*
  *      Edge Port registers
  */
 #define MCFEPORT_EPPAR          (MCF_IPSBAR + 0x00130000)
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
 #define mcfpit_h
 /****************************************************************************/
 
-
-/*
- *      Get address specific defines for the 5270/5271, 5280/5282, and 5208.
- */
-#if defined(CONFIG_M520x)
-#define MCFPIT_BASE1            0x00080000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00084000      /* Base address of TIMER2 */
-#else
-#define MCFPIT_BASE1            0x00150000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00160000      /* Base address of TIMER2 */
-#define MCFPIT_BASE3            0x00170000      /* Base address of TIMER3 */
-#define MCFPIT_BASE4            0x00180000      /* Base address of TIMER4 */
-#endif
-
 /*
- *      Define the PIT timer register set addresses.
+ *      Define the PIT timer register address offsets.
  */
 #define MCFPIT_PCSR             0x0             /* PIT control register */
 #define MCFPIT_PMR              0x2             /* PIT modulus register */
diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c
index aebea19abd78..c2b980926bec 100644
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -31,7 +31,7 @@
  *      By default use timer1 as the system clock timer.
  */
 #define FREQ    ((MCF_CLK / 2) / 64)
-#define TA(a)   (MCF_IPSBAR + MCFPIT_BASE1 + (a))
+#define TA(a)   (MCFPIT_BASE1 + (a))
 #define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
 
 static u32 pit_cnt;