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authorAlex Deucher <alexander.deucher@amd.com>2014-06-25 19:32:36 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:24 -0400
commitf2c6b0f452c3804496f55655fda28c2809e1a58b (patch)
treefcff3a4927d30bbbcbe084874c1a9a9008ba1f12
parent629bd33c75196ca89625148614e9e34b42f4f460 (diff)
drm/radeon/cik: Add support for new ucode format (v5)
This adds CIK support for the new ucode format. v2: add size validation, integrate debug info v3: add support for MEC2 on KV v4: fix typos v4: update to latest format Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/ci_smc.c39
-rw-r--r--drivers/gpu/drm/radeon/cik.c689
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c57
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
4 files changed, 596 insertions, 190 deletions
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c
index 8debc9d47362..b630edc2fd0c 100644
--- a/drivers/gpu/drm/radeon/ci_smc.c
+++ b/drivers/gpu/drm/radeon/ci_smc.c
@@ -213,24 +213,37 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
213 if (!rdev->smc_fw) 213 if (!rdev->smc_fw)
214 return -EINVAL; 214 return -EINVAL;
215 215
216 switch (rdev->family) { 216 if (rdev->new_fw) {
217 case CHIP_BONAIRE: 217 const struct smc_firmware_header_v1_0 *hdr =
218 ucode_start_address = BONAIRE_SMC_UCODE_START; 218 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data;
219 ucode_size = BONAIRE_SMC_UCODE_SIZE; 219
220 break; 220 radeon_ucode_print_smc_hdr(&hdr->header);
221 case CHIP_HAWAII: 221
222 ucode_start_address = HAWAII_SMC_UCODE_START; 222 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
223 ucode_size = HAWAII_SMC_UCODE_SIZE; 223 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
224 break; 224 src = (const u8 *)
225 default: 225 (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
226 DRM_ERROR("unknown asic in smc ucode loader\n"); 226 } else {
227 BUG(); 227 switch (rdev->family) {
228 case CHIP_BONAIRE:
229 ucode_start_address = BONAIRE_SMC_UCODE_START;
230 ucode_size = BONAIRE_SMC_UCODE_SIZE;
231 break;
232 case CHIP_HAWAII:
233 ucode_start_address = HAWAII_SMC_UCODE_START;
234 ucode_size = HAWAII_SMC_UCODE_SIZE;
235 break;
236 default:
237 DRM_ERROR("unknown asic in smc ucode loader\n");
238 BUG();
239 }
240
241 src = (const u8 *)rdev->smc_fw->data;
228 } 242 }
229 243
230 if (ucode_size & 3) 244 if (ucode_size & 3)
231 return -EINVAL; 245 return -EINVAL;
232 246
233 src = (const u8 *)rdev->smc_fw->data;
234 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 247 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
235 WREG32(SMC_IND_INDEX_0, ucode_start_address); 248 WREG32(SMC_IND_INDEX_0, ucode_start_address);
236 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); 249 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index c0ea66192fe0..f1e049b1ab00 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -42,6 +42,16 @@ MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
42MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); 42MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
43MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); 43MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
44MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); 44MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
45
46MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
47MODULE_FIRMWARE("radeon/bonaire_me.bin");
48MODULE_FIRMWARE("radeon/bonaire_ce.bin");
49MODULE_FIRMWARE("radeon/bonaire_mec.bin");
50MODULE_FIRMWARE("radeon/bonaire_mc.bin");
51MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
52MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
53MODULE_FIRMWARE("radeon/bonaire_smc.bin");
54
45MODULE_FIRMWARE("radeon/HAWAII_pfp.bin"); 55MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
46MODULE_FIRMWARE("radeon/HAWAII_me.bin"); 56MODULE_FIRMWARE("radeon/HAWAII_me.bin");
47MODULE_FIRMWARE("radeon/HAWAII_ce.bin"); 57MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
@@ -51,18 +61,45 @@ MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
51MODULE_FIRMWARE("radeon/HAWAII_rlc.bin"); 61MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
52MODULE_FIRMWARE("radeon/HAWAII_sdma.bin"); 62MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
53MODULE_FIRMWARE("radeon/HAWAII_smc.bin"); 63MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
64
65MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
66MODULE_FIRMWARE("radeon/hawaii_me.bin");
67MODULE_FIRMWARE("radeon/hawaii_ce.bin");
68MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69MODULE_FIRMWARE("radeon/hawaii_mc.bin");
70MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
71MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
72MODULE_FIRMWARE("radeon/hawaii_smc.bin");
73
54MODULE_FIRMWARE("radeon/KAVERI_pfp.bin"); 74MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
55MODULE_FIRMWARE("radeon/KAVERI_me.bin"); 75MODULE_FIRMWARE("radeon/KAVERI_me.bin");
56MODULE_FIRMWARE("radeon/KAVERI_ce.bin"); 76MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
57MODULE_FIRMWARE("radeon/KAVERI_mec.bin"); 77MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
58MODULE_FIRMWARE("radeon/KAVERI_rlc.bin"); 78MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
59MODULE_FIRMWARE("radeon/KAVERI_sdma.bin"); 79MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
80
81MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
82MODULE_FIRMWARE("radeon/kaveri_me.bin");
83MODULE_FIRMWARE("radeon/kaveri_ce.bin");
84MODULE_FIRMWARE("radeon/kaveri_mec.bin");
85MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
86MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
87MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
88
60MODULE_FIRMWARE("radeon/KABINI_pfp.bin"); 89MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
61MODULE_FIRMWARE("radeon/KABINI_me.bin"); 90MODULE_FIRMWARE("radeon/KABINI_me.bin");
62MODULE_FIRMWARE("radeon/KABINI_ce.bin"); 91MODULE_FIRMWARE("radeon/KABINI_ce.bin");
63MODULE_FIRMWARE("radeon/KABINI_mec.bin"); 92MODULE_FIRMWARE("radeon/KABINI_mec.bin");
64MODULE_FIRMWARE("radeon/KABINI_rlc.bin"); 93MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
65MODULE_FIRMWARE("radeon/KABINI_sdma.bin"); 94MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
95
96MODULE_FIRMWARE("radeon/kabini_pfp.bin");
97MODULE_FIRMWARE("radeon/kabini_me.bin");
98MODULE_FIRMWARE("radeon/kabini_ce.bin");
99MODULE_FIRMWARE("radeon/kabini_mec.bin");
100MODULE_FIRMWARE("radeon/kabini_rlc.bin");
101MODULE_FIRMWARE("radeon/kabini_sdma.bin");
102
66MODULE_FIRMWARE("radeon/MULLINS_pfp.bin"); 103MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
67MODULE_FIRMWARE("radeon/MULLINS_me.bin"); 104MODULE_FIRMWARE("radeon/MULLINS_me.bin");
68MODULE_FIRMWARE("radeon/MULLINS_ce.bin"); 105MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
@@ -70,6 +107,13 @@ MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
70MODULE_FIRMWARE("radeon/MULLINS_rlc.bin"); 107MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
71MODULE_FIRMWARE("radeon/MULLINS_sdma.bin"); 108MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
72 109
110MODULE_FIRMWARE("radeon/mullins_pfp.bin");
111MODULE_FIRMWARE("radeon/mullins_me.bin");
112MODULE_FIRMWARE("radeon/mullins_ce.bin");
113MODULE_FIRMWARE("radeon/mullins_mec.bin");
114MODULE_FIRMWARE("radeon/mullins_rlc.bin");
115MODULE_FIRMWARE("radeon/mullins_sdma.bin");
116
73extern int r600_ih_ring_alloc(struct radeon_device *rdev); 117extern int r600_ih_ring_alloc(struct radeon_device *rdev);
74extern void r600_ih_ring_fini(struct radeon_device *rdev); 118extern void r600_ih_ring_fini(struct radeon_device *rdev);
75extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 119extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
@@ -1760,27 +1804,44 @@ static void cik_srbm_select(struct radeon_device *rdev,
1760 */ 1804 */
1761int ci_mc_load_microcode(struct radeon_device *rdev) 1805int ci_mc_load_microcode(struct radeon_device *rdev)
1762{ 1806{
1763 const __be32 *fw_data; 1807 const __be32 *fw_data = NULL;
1808 const __le32 *new_fw_data = NULL;
1764 u32 running, blackout = 0; 1809 u32 running, blackout = 0;
1765 u32 *io_mc_regs; 1810 u32 *io_mc_regs = NULL;
1811 const __le32 *new_io_mc_regs = NULL;
1766 int i, regs_size, ucode_size; 1812 int i, regs_size, ucode_size;
1767 1813
1768 if (!rdev->mc_fw) 1814 if (!rdev->mc_fw)
1769 return -EINVAL; 1815 return -EINVAL;
1770 1816
1771 ucode_size = rdev->mc_fw->size / 4; 1817 if (rdev->new_fw) {
1818 const struct mc_firmware_header_v1_0 *hdr =
1819 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1772 1820
1773 switch (rdev->family) { 1821 radeon_ucode_print_mc_hdr(&hdr->header);
1774 case CHIP_BONAIRE: 1822
1775 io_mc_regs = (u32 *)&bonaire_io_mc_regs; 1823 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1776 regs_size = BONAIRE_IO_MC_REGS_SIZE; 1824 new_io_mc_regs = (const __le32 *)
1777 break; 1825 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1778 case CHIP_HAWAII: 1826 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1779 io_mc_regs = (u32 *)&hawaii_io_mc_regs; 1827 new_fw_data = (const __le32 *)
1780 regs_size = HAWAII_IO_MC_REGS_SIZE; 1828 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1781 break; 1829 } else {
1782 default: 1830 ucode_size = rdev->mc_fw->size / 4;
1783 return -EINVAL; 1831
1832 switch (rdev->family) {
1833 case CHIP_BONAIRE:
1834 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1835 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1836 break;
1837 case CHIP_HAWAII:
1838 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1839 regs_size = HAWAII_IO_MC_REGS_SIZE;
1840 break;
1841 default:
1842 return -EINVAL;
1843 }
1844 fw_data = (const __be32 *)rdev->mc_fw->data;
1784 } 1845 }
1785 1846
1786 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 1847 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
@@ -1797,13 +1858,21 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
1797 1858
1798 /* load mc io regs */ 1859 /* load mc io regs */
1799 for (i = 0; i < regs_size; i++) { 1860 for (i = 0; i < regs_size; i++) {
1800 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 1861 if (rdev->new_fw) {
1801 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 1862 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1863 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1864 } else {
1865 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1866 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1867 }
1802 } 1868 }
1803 /* load the MC ucode */ 1869 /* load the MC ucode */
1804 fw_data = (const __be32 *)rdev->mc_fw->data; 1870 for (i = 0; i < ucode_size; i++) {
1805 for (i = 0; i < ucode_size; i++) 1871 if (rdev->new_fw)
1806 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 1872 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1873 else
1874 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1875 }
1807 1876
1808 /* put the engine back into the active state */ 1877 /* put the engine back into the active state */
1809 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 1878 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
@@ -1841,17 +1910,21 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
1841static int cik_init_microcode(struct radeon_device *rdev) 1910static int cik_init_microcode(struct radeon_device *rdev)
1842{ 1911{
1843 const char *chip_name; 1912 const char *chip_name;
1913 const char *new_chip_name;
1844 size_t pfp_req_size, me_req_size, ce_req_size, 1914 size_t pfp_req_size, me_req_size, ce_req_size,
1845 mec_req_size, rlc_req_size, mc_req_size = 0, 1915 mec_req_size, rlc_req_size, mc_req_size = 0,
1846 sdma_req_size, smc_req_size = 0, mc2_req_size = 0; 1916 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1847 char fw_name[30]; 1917 char fw_name[30];
1918 int new_fw = 0;
1848 int err; 1919 int err;
1920 int num_fw;
1849 1921
1850 DRM_DEBUG("\n"); 1922 DRM_DEBUG("\n");
1851 1923
1852 switch (rdev->family) { 1924 switch (rdev->family) {
1853 case CHIP_BONAIRE: 1925 case CHIP_BONAIRE:
1854 chip_name = "BONAIRE"; 1926 chip_name = "BONAIRE";
1927 new_chip_name = "bonaire";
1855 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1928 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1856 me_req_size = CIK_ME_UCODE_SIZE * 4; 1929 me_req_size = CIK_ME_UCODE_SIZE * 4;
1857 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1930 ce_req_size = CIK_CE_UCODE_SIZE * 4;
@@ -1861,9 +1934,11 @@ static int cik_init_microcode(struct radeon_device *rdev)
1861 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4; 1934 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
1862 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1935 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1863 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4); 1936 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
1937 num_fw = 8;
1864 break; 1938 break;
1865 case CHIP_HAWAII: 1939 case CHIP_HAWAII:
1866 chip_name = "HAWAII"; 1940 chip_name = "HAWAII";
1941 new_chip_name = "hawaii";
1867 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1942 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1868 me_req_size = CIK_ME_UCODE_SIZE * 4; 1943 me_req_size = CIK_ME_UCODE_SIZE * 4;
1869 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1944 ce_req_size = CIK_CE_UCODE_SIZE * 4;
@@ -1873,142 +1948,285 @@ static int cik_init_microcode(struct radeon_device *rdev)
1873 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4; 1948 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
1874 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1949 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1875 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4); 1950 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
1951 num_fw = 8;
1876 break; 1952 break;
1877 case CHIP_KAVERI: 1953 case CHIP_KAVERI:
1878 chip_name = "KAVERI"; 1954 chip_name = "KAVERI";
1955 new_chip_name = "kaveri";
1879 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1956 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1880 me_req_size = CIK_ME_UCODE_SIZE * 4; 1957 me_req_size = CIK_ME_UCODE_SIZE * 4;
1881 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1958 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1882 mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1959 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1883 rlc_req_size = KV_RLC_UCODE_SIZE * 4; 1960 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
1884 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1961 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1962 num_fw = 7;
1885 break; 1963 break;
1886 case CHIP_KABINI: 1964 case CHIP_KABINI:
1887 chip_name = "KABINI"; 1965 chip_name = "KABINI";
1966 new_chip_name = "kabini";
1888 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1967 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1889 me_req_size = CIK_ME_UCODE_SIZE * 4; 1968 me_req_size = CIK_ME_UCODE_SIZE * 4;
1890 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1969 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1891 mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1970 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1892 rlc_req_size = KB_RLC_UCODE_SIZE * 4; 1971 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
1893 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1972 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1973 num_fw = 6;
1894 break; 1974 break;
1895 case CHIP_MULLINS: 1975 case CHIP_MULLINS:
1896 chip_name = "MULLINS"; 1976 chip_name = "MULLINS";
1977 new_chip_name = "mullins";
1897 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1978 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1898 me_req_size = CIK_ME_UCODE_SIZE * 4; 1979 me_req_size = CIK_ME_UCODE_SIZE * 4;
1899 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1980 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1900 mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1981 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1901 rlc_req_size = ML_RLC_UCODE_SIZE * 4; 1982 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
1902 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1983 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1984 num_fw = 6;
1903 break; 1985 break;
1904 default: BUG(); 1986 default: BUG();
1905 } 1987 }
1906 1988
1907 DRM_INFO("Loading %s Microcode\n", chip_name); 1989 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1908 1990
1909 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 1991 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
1910 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 1992 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1911 if (err) 1993 if (err) {
1912 goto out; 1994 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1913 if (rdev->pfp_fw->size != pfp_req_size) { 1995 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1914 printk(KERN_ERR 1996 if (err)
1915 "cik_cp: Bogus length %zu in firmware \"%s\"\n", 1997 goto out;
1916 rdev->pfp_fw->size, fw_name); 1998 if (rdev->pfp_fw->size != pfp_req_size) {
1917 err = -EINVAL; 1999 printk(KERN_ERR
1918 goto out; 2000 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2001 rdev->pfp_fw->size, fw_name);
2002 err = -EINVAL;
2003 goto out;
2004 }
2005 } else {
2006 err = radeon_ucode_validate(rdev->pfp_fw);
2007 if (err) {
2008 printk(KERN_ERR
2009 "cik_fw: validation failed for firmware \"%s\"\n",
2010 fw_name);
2011 goto out;
2012 } else {
2013 new_fw++;
2014 }
1919 } 2015 }
1920 2016
1921 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2017 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
1922 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2018 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1923 if (err) 2019 if (err) {
1924 goto out; 2020 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1925 if (rdev->me_fw->size != me_req_size) { 2021 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1926 printk(KERN_ERR 2022 if (err)
1927 "cik_cp: Bogus length %zu in firmware \"%s\"\n", 2023 goto out;
1928 rdev->me_fw->size, fw_name); 2024 if (rdev->me_fw->size != me_req_size) {
1929 err = -EINVAL; 2025 printk(KERN_ERR
2026 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2027 rdev->me_fw->size, fw_name);
2028 err = -EINVAL;
2029 }
2030 } else {
2031 err = radeon_ucode_validate(rdev->me_fw);
2032 if (err) {
2033 printk(KERN_ERR
2034 "cik_fw: validation failed for firmware \"%s\"\n",
2035 fw_name);
2036 goto out;
2037 } else {
2038 new_fw++;
2039 }
1930 } 2040 }
1931 2041
1932 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 2042 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
1933 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); 2043 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1934 if (err) 2044 if (err) {
1935 goto out; 2045 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1936 if (rdev->ce_fw->size != ce_req_size) { 2046 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1937 printk(KERN_ERR 2047 if (err)
1938 "cik_cp: Bogus length %zu in firmware \"%s\"\n", 2048 goto out;
1939 rdev->ce_fw->size, fw_name); 2049 if (rdev->ce_fw->size != ce_req_size) {
1940 err = -EINVAL; 2050 printk(KERN_ERR
2051 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2052 rdev->ce_fw->size, fw_name);
2053 err = -EINVAL;
2054 }
2055 } else {
2056 err = radeon_ucode_validate(rdev->ce_fw);
2057 if (err) {
2058 printk(KERN_ERR
2059 "cik_fw: validation failed for firmware \"%s\"\n",
2060 fw_name);
2061 goto out;
2062 } else {
2063 new_fw++;
2064 }
1941 } 2065 }
1942 2066
1943 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); 2067 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
1944 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev); 2068 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
1945 if (err) 2069 if (err) {
1946 goto out; 2070 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
1947 if (rdev->mec_fw->size != mec_req_size) { 2071 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
1948 printk(KERN_ERR 2072 if (err)
1949 "cik_cp: Bogus length %zu in firmware \"%s\"\n", 2073 goto out;
1950 rdev->mec_fw->size, fw_name); 2074 if (rdev->mec_fw->size != mec_req_size) {
1951 err = -EINVAL; 2075 printk(KERN_ERR
2076 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2077 rdev->mec_fw->size, fw_name);
2078 err = -EINVAL;
2079 }
2080 } else {
2081 err = radeon_ucode_validate(rdev->mec_fw);
2082 if (err) {
2083 printk(KERN_ERR
2084 "cik_fw: validation failed for firmware \"%s\"\n",
2085 fw_name);
2086 goto out;
2087 } else {
2088 new_fw++;
2089 }
1952 } 2090 }
1953 2091
1954 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 2092 if (rdev->family == CHIP_KAVERI) {
2093 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
2094 err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
2095 if (err) {
2096 goto out;
2097 } else {
2098 err = radeon_ucode_validate(rdev->mec2_fw);
2099 if (err) {
2100 goto out;
2101 } else {
2102 new_fw++;
2103 }
2104 }
2105 }
2106
2107 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
1955 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2108 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1956 if (err) 2109 if (err) {
1957 goto out; 2110 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1958 if (rdev->rlc_fw->size != rlc_req_size) { 2111 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1959 printk(KERN_ERR 2112 if (err)
1960 "cik_rlc: Bogus length %zu in firmware \"%s\"\n", 2113 goto out;
1961 rdev->rlc_fw->size, fw_name); 2114 if (rdev->rlc_fw->size != rlc_req_size) {
1962 err = -EINVAL; 2115 printk(KERN_ERR
2116 "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2117 rdev->rlc_fw->size, fw_name);
2118 err = -EINVAL;
2119 }
2120 } else {
2121 err = radeon_ucode_validate(rdev->rlc_fw);
2122 if (err) {
2123 printk(KERN_ERR
2124 "cik_fw: validation failed for firmware \"%s\"\n",
2125 fw_name);
2126 goto out;
2127 } else {
2128 new_fw++;
2129 }
1963 } 2130 }
1964 2131
1965 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); 2132 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
1966 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev); 2133 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
1967 if (err) 2134 if (err) {
1968 goto out; 2135 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
1969 if (rdev->sdma_fw->size != sdma_req_size) { 2136 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
1970 printk(KERN_ERR 2137 if (err)
1971 "cik_sdma: Bogus length %zu in firmware \"%s\"\n", 2138 goto out;
1972 rdev->sdma_fw->size, fw_name); 2139 if (rdev->sdma_fw->size != sdma_req_size) {
1973 err = -EINVAL; 2140 printk(KERN_ERR
2141 "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2142 rdev->sdma_fw->size, fw_name);
2143 err = -EINVAL;
2144 }
2145 } else {
2146 err = radeon_ucode_validate(rdev->sdma_fw);
2147 if (err) {
2148 printk(KERN_ERR
2149 "cik_fw: validation failed for firmware \"%s\"\n",
2150 fw_name);
2151 goto out;
2152 } else {
2153 new_fw++;
2154 }
1974 } 2155 }
1975 2156
1976 /* No SMC, MC ucode on APUs */ 2157 /* No SMC, MC ucode on APUs */
1977 if (!(rdev->flags & RADEON_IS_IGP)) { 2158 if (!(rdev->flags & RADEON_IS_IGP)) {
1978 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name); 2159 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
1979 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 2160 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1980 if (err) { 2161 if (err) {
1981 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 2162 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1982 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 2163 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1983 if (err) 2164 if (err) {
2165 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
2166 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2167 if (err)
2168 goto out;
2169 }
2170 if ((rdev->mc_fw->size != mc_req_size) &&
2171 (rdev->mc_fw->size != mc2_req_size)){
2172 printk(KERN_ERR
2173 "cik_mc: Bogus length %zu in firmware \"%s\"\n",
2174 rdev->mc_fw->size, fw_name);
2175 err = -EINVAL;
2176 }
2177 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
2178 } else {
2179 err = radeon_ucode_validate(rdev->mc_fw);
2180 if (err) {
2181 printk(KERN_ERR
2182 "cik_fw: validation failed for firmware \"%s\"\n",
2183 fw_name);
1984 goto out; 2184 goto out;
2185 } else {
2186 new_fw++;
2187 }
1985 } 2188 }
1986 if ((rdev->mc_fw->size != mc_req_size) &&
1987 (rdev->mc_fw->size != mc2_req_size)){
1988 printk(KERN_ERR
1989 "cik_mc: Bogus length %zu in firmware \"%s\"\n",
1990 rdev->mc_fw->size, fw_name);
1991 err = -EINVAL;
1992 }
1993 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1994 2189
1995 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 2190 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
1996 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2191 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1997 if (err) { 2192 if (err) {
1998 printk(KERN_ERR 2193 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1999 "smc: error loading firmware \"%s\"\n", 2194 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2000 fw_name); 2195 if (err) {
2001 release_firmware(rdev->smc_fw); 2196 printk(KERN_ERR
2002 rdev->smc_fw = NULL; 2197 "smc: error loading firmware \"%s\"\n",
2003 err = 0; 2198 fw_name);
2004 } else if (rdev->smc_fw->size != smc_req_size) { 2199 release_firmware(rdev->smc_fw);
2005 printk(KERN_ERR 2200 rdev->smc_fw = NULL;
2006 "cik_smc: Bogus length %zu in firmware \"%s\"\n", 2201 err = 0;
2007 rdev->smc_fw->size, fw_name); 2202 } else if (rdev->smc_fw->size != smc_req_size) {
2008 err = -EINVAL; 2203 printk(KERN_ERR
2204 "cik_smc: Bogus length %zu in firmware \"%s\"\n",
2205 rdev->smc_fw->size, fw_name);
2206 err = -EINVAL;
2207 }
2208 } else {
2209 err = radeon_ucode_validate(rdev->smc_fw);
2210 if (err) {
2211 printk(KERN_ERR
2212 "cik_fw: validation failed for firmware \"%s\"\n",
2213 fw_name);
2214 goto out;
2215 } else {
2216 new_fw++;
2217 }
2009 } 2218 }
2010 } 2219 }
2011 2220
2221 if (new_fw == 0) {
2222 rdev->new_fw = false;
2223 } else if (new_fw < num_fw) {
2224 printk(KERN_ERR "ci_fw: mixing new and old firmware!\n");
2225 err = -EINVAL;
2226 } else {
2227 rdev->new_fw = true;
2228 }
2229
2012out: 2230out:
2013 if (err) { 2231 if (err) {
2014 if (err != -EINVAL) 2232 if (err != -EINVAL)
@@ -2021,8 +2239,14 @@ out:
2021 rdev->me_fw = NULL; 2239 rdev->me_fw = NULL;
2022 release_firmware(rdev->ce_fw); 2240 release_firmware(rdev->ce_fw);
2023 rdev->ce_fw = NULL; 2241 rdev->ce_fw = NULL;
2242 release_firmware(rdev->mec_fw);
2243 rdev->mec_fw = NULL;
2244 release_firmware(rdev->mec2_fw);
2245 rdev->mec2_fw = NULL;
2024 release_firmware(rdev->rlc_fw); 2246 release_firmware(rdev->rlc_fw);
2025 rdev->rlc_fw = NULL; 2247 rdev->rlc_fw = NULL;
2248 release_firmware(rdev->sdma_fw);
2249 rdev->sdma_fw = NULL;
2026 release_firmware(rdev->mc_fw); 2250 release_firmware(rdev->mc_fw);
2027 rdev->mc_fw = NULL; 2251 rdev->mc_fw = NULL;
2028 release_firmware(rdev->smc_fw); 2252 release_firmware(rdev->smc_fw);
@@ -3969,7 +4193,6 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3969 */ 4193 */
3970static int cik_cp_gfx_load_microcode(struct radeon_device *rdev) 4194static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3971{ 4195{
3972 const __be32 *fw_data;
3973 int i; 4196 int i;
3974 4197
3975 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw) 4198 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
@@ -3977,26 +4200,70 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3977 4200
3978 cik_cp_gfx_enable(rdev, false); 4201 cik_cp_gfx_enable(rdev, false);
3979 4202
3980 /* PFP */ 4203 if (rdev->new_fw) {
3981 fw_data = (const __be32 *)rdev->pfp_fw->data; 4204 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3982 WREG32(CP_PFP_UCODE_ADDR, 0); 4205 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3983 for (i = 0; i < CIK_PFP_UCODE_SIZE; i++) 4206 const struct gfx_firmware_header_v1_0 *ce_hdr =
3984 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 4207 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3985 WREG32(CP_PFP_UCODE_ADDR, 0); 4208 const struct gfx_firmware_header_v1_0 *me_hdr =
3986 4209 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3987 /* CE */ 4210 const __le32 *fw_data;
3988 fw_data = (const __be32 *)rdev->ce_fw->data; 4211 u32 fw_size;
3989 WREG32(CP_CE_UCODE_ADDR, 0); 4212
3990 for (i = 0; i < CIK_CE_UCODE_SIZE; i++) 4213 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3991 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); 4214 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3992 WREG32(CP_CE_UCODE_ADDR, 0); 4215 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3993 4216
3994 /* ME */ 4217 /* PFP */
3995 fw_data = (const __be32 *)rdev->me_fw->data; 4218 fw_data = (const __le32 *)
3996 WREG32(CP_ME_RAM_WADDR, 0); 4219 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3997 for (i = 0; i < CIK_ME_UCODE_SIZE; i++) 4220 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3998 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 4221 WREG32(CP_PFP_UCODE_ADDR, 0);
3999 WREG32(CP_ME_RAM_WADDR, 0); 4222 for (i = 0; i < fw_size; i++)
4223 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4224 WREG32(CP_PFP_UCODE_ADDR, 0);
4225
4226 /* CE */
4227 fw_data = (const __le32 *)
4228 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
4229 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
4230 WREG32(CP_CE_UCODE_ADDR, 0);
4231 for (i = 0; i < fw_size; i++)
4232 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4233 WREG32(CP_CE_UCODE_ADDR, 0);
4234
4235 /* ME */
4236 fw_data = (const __be32 *)
4237 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
4238 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
4239 WREG32(CP_ME_RAM_WADDR, 0);
4240 for (i = 0; i < fw_size; i++)
4241 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4242 WREG32(CP_ME_RAM_WADDR, 0);
4243 } else {
4244 const __be32 *fw_data;
4245
4246 /* PFP */
4247 fw_data = (const __be32 *)rdev->pfp_fw->data;
4248 WREG32(CP_PFP_UCODE_ADDR, 0);
4249 for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
4250 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
4251 WREG32(CP_PFP_UCODE_ADDR, 0);
4252
4253 /* CE */
4254 fw_data = (const __be32 *)rdev->ce_fw->data;
4255 WREG32(CP_CE_UCODE_ADDR, 0);
4256 for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
4257 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
4258 WREG32(CP_CE_UCODE_ADDR, 0);
4259
4260 /* ME */
4261 fw_data = (const __be32 *)rdev->me_fw->data;
4262 WREG32(CP_ME_RAM_WADDR, 0);
4263 for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
4264 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
4265 WREG32(CP_ME_RAM_WADDR, 0);
4266 }
4000 4267
4001 WREG32(CP_PFP_UCODE_ADDR, 0); 4268 WREG32(CP_PFP_UCODE_ADDR, 0);
4002 WREG32(CP_CE_UCODE_ADDR, 0); 4269 WREG32(CP_CE_UCODE_ADDR, 0);
@@ -4261,7 +4528,6 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4261 */ 4528 */
4262static int cik_cp_compute_load_microcode(struct radeon_device *rdev) 4529static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4263{ 4530{
4264 const __be32 *fw_data;
4265 int i; 4531 int i;
4266 4532
4267 if (!rdev->mec_fw) 4533 if (!rdev->mec_fw)
@@ -4269,20 +4535,55 @@ static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4269 4535
4270 cik_cp_compute_enable(rdev, false); 4536 cik_cp_compute_enable(rdev, false);
4271 4537
4272 /* MEC1 */ 4538 if (rdev->new_fw) {
4273 fw_data = (const __be32 *)rdev->mec_fw->data; 4539 const struct gfx_firmware_header_v1_0 *mec_hdr =
4274 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); 4540 (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
4275 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++) 4541 const __le32 *fw_data;
4276 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); 4542 u32 fw_size;
4277 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); 4543
4544 radeon_ucode_print_gfx_hdr(&mec_hdr->header);
4545
4546 /* MEC1 */
4547 fw_data = (const __le32 *)
4548 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4549 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4550 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4551 for (i = 0; i < fw_size; i++)
4552 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4553 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4278 4554
4279 if (rdev->family == CHIP_KAVERI) {
4280 /* MEC2 */ 4555 /* MEC2 */
4556 if (rdev->family == CHIP_KAVERI) {
4557 const struct gfx_firmware_header_v1_0 *mec2_hdr =
4558 (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
4559
4560 fw_data = (const __le32 *)
4561 (rdev->mec2_fw->data +
4562 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4563 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4564 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4565 for (i = 0; i < fw_size; i++)
4566 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
4567 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4568 }
4569 } else {
4570 const __be32 *fw_data;
4571
4572 /* MEC1 */
4281 fw_data = (const __be32 *)rdev->mec_fw->data; 4573 fw_data = (const __be32 *)rdev->mec_fw->data;
4282 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); 4574 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4283 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++) 4575 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4284 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); 4576 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4285 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); 4577 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4578
4579 if (rdev->family == CHIP_KAVERI) {
4580 /* MEC2 */
4581 fw_data = (const __be32 *)rdev->mec_fw->data;
4582 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4583 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4584 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4585 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4586 }
4286 } 4587 }
4287 4588
4288 return 0; 4589 return 0;
@@ -5865,28 +6166,10 @@ static void cik_rlc_start(struct radeon_device *rdev)
5865static int cik_rlc_resume(struct radeon_device *rdev) 6166static int cik_rlc_resume(struct radeon_device *rdev)
5866{ 6167{
5867 u32 i, size, tmp; 6168 u32 i, size, tmp;
5868 const __be32 *fw_data;
5869 6169
5870 if (!rdev->rlc_fw) 6170 if (!rdev->rlc_fw)
5871 return -EINVAL; 6171 return -EINVAL;
5872 6172
5873 switch (rdev->family) {
5874 case CHIP_BONAIRE:
5875 case CHIP_HAWAII:
5876 default:
5877 size = BONAIRE_RLC_UCODE_SIZE;
5878 break;
5879 case CHIP_KAVERI:
5880 size = KV_RLC_UCODE_SIZE;
5881 break;
5882 case CHIP_KABINI:
5883 size = KB_RLC_UCODE_SIZE;
5884 break;
5885 case CHIP_MULLINS:
5886 size = ML_RLC_UCODE_SIZE;
5887 break;
5888 }
5889
5890 cik_rlc_stop(rdev); 6173 cik_rlc_stop(rdev);
5891 6174
5892 /* disable CG */ 6175 /* disable CG */
@@ -5910,11 +6193,45 @@ static int cik_rlc_resume(struct radeon_device *rdev)
5910 WREG32(RLC_MC_CNTL, 0); 6193 WREG32(RLC_MC_CNTL, 0);
5911 WREG32(RLC_UCODE_CNTL, 0); 6194 WREG32(RLC_UCODE_CNTL, 0);
5912 6195
5913 fw_data = (const __be32 *)rdev->rlc_fw->data; 6196 if (rdev->new_fw) {
6197 const struct rlc_firmware_header_v1_0 *hdr =
6198 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
6199 const __le32 *fw_data = (const __le32 *)
6200 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6201
6202 radeon_ucode_print_rlc_hdr(&hdr->header);
6203
6204 size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
6205 WREG32(RLC_GPM_UCODE_ADDR, 0);
6206 for (i = 0; i < size; i++)
6207 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
5914 WREG32(RLC_GPM_UCODE_ADDR, 0); 6208 WREG32(RLC_GPM_UCODE_ADDR, 0);
5915 for (i = 0; i < size; i++) 6209 } else {
5916 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); 6210 const __be32 *fw_data;
5917 WREG32(RLC_GPM_UCODE_ADDR, 0); 6211
6212 switch (rdev->family) {
6213 case CHIP_BONAIRE:
6214 case CHIP_HAWAII:
6215 default:
6216 size = BONAIRE_RLC_UCODE_SIZE;
6217 break;
6218 case CHIP_KAVERI:
6219 size = KV_RLC_UCODE_SIZE;
6220 break;
6221 case CHIP_KABINI:
6222 size = KB_RLC_UCODE_SIZE;
6223 break;
6224 case CHIP_MULLINS:
6225 size = ML_RLC_UCODE_SIZE;
6226 break;
6227 }
6228
6229 fw_data = (const __be32 *)rdev->rlc_fw->data;
6230 WREG32(RLC_GPM_UCODE_ADDR, 0);
6231 for (i = 0; i < size; i++)
6232 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
6233 WREG32(RLC_GPM_UCODE_ADDR, 0);
6234 }
5918 6235
5919 /* XXX - find out what chips support lbpw */ 6236 /* XXX - find out what chips support lbpw */
5920 cik_enable_lbpw(rdev, false); 6237 cik_enable_lbpw(rdev, false);
@@ -6348,11 +6665,10 @@ static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6348 6665
6349void cik_init_cp_pg_table(struct radeon_device *rdev) 6666void cik_init_cp_pg_table(struct radeon_device *rdev)
6350{ 6667{
6351 const __be32 *fw_data;
6352 volatile u32 *dst_ptr; 6668 volatile u32 *dst_ptr;
6353 int me, i, max_me = 4; 6669 int me, i, max_me = 4;
6354 u32 bo_offset = 0; 6670 u32 bo_offset = 0;
6355 u32 table_offset; 6671 u32 table_offset, table_size;
6356 6672
6357 if (rdev->family == CHIP_KAVERI) 6673 if (rdev->family == CHIP_KAVERI)
6358 max_me = 5; 6674 max_me = 5;
@@ -6363,24 +6679,71 @@ void cik_init_cp_pg_table(struct radeon_device *rdev)
6363 /* write the cp table buffer */ 6679 /* write the cp table buffer */
6364 dst_ptr = rdev->rlc.cp_table_ptr; 6680 dst_ptr = rdev->rlc.cp_table_ptr;
6365 for (me = 0; me < max_me; me++) { 6681 for (me = 0; me < max_me; me++) {
6366 if (me == 0) { 6682 if (rdev->new_fw) {
6367 fw_data = (const __be32 *)rdev->ce_fw->data; 6683 const __le32 *fw_data;
6368 table_offset = CP_ME_TABLE_OFFSET; 6684 const struct gfx_firmware_header_v1_0 *hdr;
6369 } else if (me == 1) { 6685
6370 fw_data = (const __be32 *)rdev->pfp_fw->data; 6686 if (me == 0) {
6371 table_offset = CP_ME_TABLE_OFFSET; 6687 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
6372 } else if (me == 2) { 6688 fw_data = (const __le32 *)
6373 fw_data = (const __be32 *)rdev->me_fw->data; 6689 (rdev->ce_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6374 table_offset = CP_ME_TABLE_OFFSET; 6690 table_offset = le32_to_cpu(hdr->jt_offset);
6691 table_size = le32_to_cpu(hdr->jt_size);
6692 } else if (me == 1) {
6693 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
6694 fw_data = (const __le32 *)
6695 (rdev->pfp_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6696 table_offset = le32_to_cpu(hdr->jt_offset);
6697 table_size = le32_to_cpu(hdr->jt_size);
6698 } else if (me == 2) {
6699 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
6700 fw_data = (const __le32 *)
6701 (rdev->me_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6702 table_offset = le32_to_cpu(hdr->jt_offset);
6703 table_size = le32_to_cpu(hdr->jt_size);
6704 } else if (me == 3) {
6705 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
6706 fw_data = (const __le32 *)
6707 (rdev->mec_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6708 table_offset = le32_to_cpu(hdr->jt_offset);
6709 table_size = le32_to_cpu(hdr->jt_size);
6710 } else {
6711 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
6712 fw_data = (const __le32 *)
6713 (rdev->mec2_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6714 table_offset = le32_to_cpu(hdr->jt_offset);
6715 table_size = le32_to_cpu(hdr->jt_size);
6716 }
6717
6718 for (i = 0; i < table_size; i ++) {
6719 dst_ptr[bo_offset + i] =
6720 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
6721 }
6722 bo_offset += table_size;
6375 } else { 6723 } else {
6376 fw_data = (const __be32 *)rdev->mec_fw->data; 6724 const __be32 *fw_data;
6377 table_offset = CP_MEC_TABLE_OFFSET; 6725 table_size = CP_ME_TABLE_SIZE;
6378 } 6726
6727 if (me == 0) {
6728 fw_data = (const __be32 *)rdev->ce_fw->data;
6729 table_offset = CP_ME_TABLE_OFFSET;
6730 } else if (me == 1) {
6731 fw_data = (const __be32 *)rdev->pfp_fw->data;
6732 table_offset = CP_ME_TABLE_OFFSET;
6733 } else if (me == 2) {
6734 fw_data = (const __be32 *)rdev->me_fw->data;
6735 table_offset = CP_ME_TABLE_OFFSET;
6736 } else {
6737 fw_data = (const __be32 *)rdev->mec_fw->data;
6738 table_offset = CP_MEC_TABLE_OFFSET;
6739 }
6379 6740
6380 for (i = 0; i < CP_ME_TABLE_SIZE; i ++) { 6741 for (i = 0; i < table_size; i ++) {
6381 dst_ptr[bo_offset + i] = cpu_to_le32(be32_to_cpu(fw_data[table_offset + i])); 6742 dst_ptr[bo_offset + i] =
6743 cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
6744 }
6745 bo_offset += table_size;
6382 } 6746 }
6383 bo_offset += CP_ME_TABLE_SIZE;
6384 } 6747 }
6385} 6748}
6386 6749
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 8e9d0f1d858e..60aa1cb39f2f 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -24,6 +24,7 @@
24#include <linux/firmware.h> 24#include <linux/firmware.h>
25#include <drm/drmP.h> 25#include <drm/drmP.h>
26#include "radeon.h" 26#include "radeon.h"
27#include "radeon_ucode.h"
27#include "radeon_asic.h" 28#include "radeon_asic.h"
28#include "radeon_trace.h" 29#include "radeon_trace.h"
29#include "cikd.h" 30#include "cikd.h"
@@ -419,7 +420,6 @@ static int cik_sdma_rlc_resume(struct radeon_device *rdev)
419 */ 420 */
420static int cik_sdma_load_microcode(struct radeon_device *rdev) 421static int cik_sdma_load_microcode(struct radeon_device *rdev)
421{ 422{
422 const __be32 *fw_data;
423 int i; 423 int i;
424 424
425 if (!rdev->sdma_fw) 425 if (!rdev->sdma_fw)
@@ -428,19 +428,48 @@ static int cik_sdma_load_microcode(struct radeon_device *rdev)
428 /* halt the MEs */ 428 /* halt the MEs */
429 cik_sdma_enable(rdev, false); 429 cik_sdma_enable(rdev, false);
430 430
431 /* sdma0 */ 431 if (rdev->new_fw) {
432 fw_data = (const __be32 *)rdev->sdma_fw->data; 432 const struct sdma_firmware_header_v1_0 *hdr =
433 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 433 (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
434 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 434 const __le32 *fw_data;
435 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 435 u32 fw_size;
436 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 436
437 437 radeon_ucode_print_sdma_hdr(&hdr->header);
438 /* sdma1 */ 438
439 fw_data = (const __be32 *)rdev->sdma_fw->data; 439 /* sdma0 */
440 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 440 fw_data = (const __le32 *)
441 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 441 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
442 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 442 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
443 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 443 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
444 for (i = 0; i < fw_size; i++)
445 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
446 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
447
448 /* sdma1 */
449 fw_data = (const __le32 *)
450 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
451 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
452 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
453 for (i = 0; i < fw_size; i++)
454 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
455 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
456 } else {
457 const __be32 *fw_data;
458
459 /* sdma0 */
460 fw_data = (const __be32 *)rdev->sdma_fw->data;
461 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
462 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
463 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
464 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
465
466 /* sdma1 */
467 fw_data = (const __be32 *)rdev->sdma_fw->data;
468 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
469 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
470 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
471 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
472 }
444 473
445 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 474 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
446 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 475 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1848d4a0561..7561b1332152 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2302,6 +2302,7 @@ struct radeon_device {
2302 const struct firmware *mc_fw; /* NI MC firmware */ 2302 const struct firmware *mc_fw; /* NI MC firmware */
2303 const struct firmware *ce_fw; /* SI CE firmware */ 2303 const struct firmware *ce_fw; /* SI CE firmware */
2304 const struct firmware *mec_fw; /* CIK MEC firmware */ 2304 const struct firmware *mec_fw; /* CIK MEC firmware */
2305 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2305 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2306 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2306 const struct firmware *smc_fw; /* SMC firmware */ 2307 const struct firmware *smc_fw; /* SMC firmware */
2307 const struct firmware *uvd_fw; /* UVD firmware */ 2308 const struct firmware *uvd_fw; /* UVD firmware */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 02:27:15 -0400