aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>2012-11-30 05:56:04 -0500
committerJeff Garzik <jgarzik@redhat.com>2012-12-03 04:57:51 -0500
commitf295be25a0e7baeda1e338aeb84e16b727b78c7e (patch)
tree9944ba2845a0670442138f92ad25dced4bad502b
parentde90cd71f68e947d3bd6c3f2ef5731ead010a768 (diff)
ata_piix: re-order code and remove prototypes
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat
-rw-r--r--drivers/ata/ata_piix.c419
1 files changed, 198 insertions, 221 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index bec35f491cb9..acffcf0b3ad3 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -164,28 +164,6 @@ struct piix_host_priv {
164 void __iomem *sidpr; 164 void __iomem *sidpr;
165}; 165};
166 166
167static int piix_init_one(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
169static void piix_remove_one(struct pci_dev *pdev);
170static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
171static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
172static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
173static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
174static int ich_pata_cable_detect(struct ata_port *ap);
175static u8 piix_vmw_bmdma_status(struct ata_port *ap);
176static int piix_sidpr_scr_read(struct ata_link *link,
177 unsigned int reg, u32 *val);
178static int piix_sidpr_scr_write(struct ata_link *link,
179 unsigned int reg, u32 val);
180static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
181 unsigned hints);
182static bool piix_irq_check(struct ata_port *ap);
183static int piix_port_start(struct ata_port *ap);
184#ifdef CONFIG_PM
185static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
186static int piix_pci_device_resume(struct pci_dev *pdev);
187#endif
188
189static unsigned int in_module_init = 1; 167static unsigned int in_module_init = 1;
190 168
191static const struct pci_device_id piix_pci_tbl[] = { 169static const struct pci_device_id piix_pci_tbl[] = {
@@ -342,64 +320,6 @@ static const struct pci_device_id piix_pci_tbl[] = {
342 { } /* terminate list */ 320 { } /* terminate list */
343}; 321};
344 322
345static struct pci_driver piix_pci_driver = {
346 .name = DRV_NAME,
347 .id_table = piix_pci_tbl,
348 .probe = piix_init_one,
349 .remove = piix_remove_one,
350#ifdef CONFIG_PM
351 .suspend = piix_pci_device_suspend,
352 .resume = piix_pci_device_resume,
353#endif
354};
355
356static struct scsi_host_template piix_sht = {
357 ATA_BMDMA_SHT(DRV_NAME),
358};
359
360static struct ata_port_operations piix_sata_ops = {
361 .inherits = &ata_bmdma32_port_ops,
362 .sff_irq_check = piix_irq_check,
363 .port_start = piix_port_start,
364};
365
366static struct ata_port_operations piix_pata_ops = {
367 .inherits = &piix_sata_ops,
368 .cable_detect = ata_cable_40wire,
369 .set_piomode = piix_set_piomode,
370 .set_dmamode = piix_set_dmamode,
371 .prereset = piix_pata_prereset,
372};
373
374static struct ata_port_operations piix_vmw_ops = {
375 .inherits = &piix_pata_ops,
376 .bmdma_status = piix_vmw_bmdma_status,
377};
378
379static struct ata_port_operations ich_pata_ops = {
380 .inherits = &piix_pata_ops,
381 .cable_detect = ich_pata_cable_detect,
382 .set_dmamode = ich_set_dmamode,
383};
384
385static struct device_attribute *piix_sidpr_shost_attrs[] = {
386 &dev_attr_link_power_management_policy,
387 NULL
388};
389
390static struct scsi_host_template piix_sidpr_sht = {
391 ATA_BMDMA_SHT(DRV_NAME),
392 .shost_attrs = piix_sidpr_shost_attrs,
393};
394
395static struct ata_port_operations piix_sidpr_sata_ops = {
396 .inherits = &piix_sata_ops,
397 .hardreset = sata_std_hardreset,
398 .scr_read = piix_sidpr_scr_read,
399 .scr_write = piix_sidpr_scr_write,
400 .set_lpm = piix_sidpr_set_lpm,
401};
402
403static const struct piix_map_db ich5_map_db = { 323static const struct piix_map_db ich5_map_db = {
404 .mask = 0x7, 324 .mask = 0x7,
405 .port_enable = 0x3, 325 .port_enable = 0x3,
@@ -504,147 +424,6 @@ static const struct piix_map_db *piix_map_db_table[] = {
504 [ich8_sata_snb] = &ich8_map_db, 424 [ich8_sata_snb] = &ich8_map_db,
505}; 425};
506 426
507static struct ata_port_info piix_port_info[] = {
508 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
509 {
510 .flags = PIIX_PATA_FLAGS,
511 .pio_mask = ATA_PIO4,
512 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
513 .port_ops = &piix_pata_ops,
514 },
515
516 [piix_pata_33] = /* PIIX4 at 33MHz */
517 {
518 .flags = PIIX_PATA_FLAGS,
519 .pio_mask = ATA_PIO4,
520 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
521 .udma_mask = ATA_UDMA2,
522 .port_ops = &piix_pata_ops,
523 },
524
525 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
526 {
527 .flags = PIIX_PATA_FLAGS,
528 .pio_mask = ATA_PIO4,
529 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
530 .udma_mask = ATA_UDMA2,
531 .port_ops = &ich_pata_ops,
532 },
533
534 [ich_pata_66] = /* ICH controllers up to 66MHz */
535 {
536 .flags = PIIX_PATA_FLAGS,
537 .pio_mask = ATA_PIO4,
538 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
539 .udma_mask = ATA_UDMA4,
540 .port_ops = &ich_pata_ops,
541 },
542
543 [ich_pata_100] =
544 {
545 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
546 .pio_mask = ATA_PIO4,
547 .mwdma_mask = ATA_MWDMA12_ONLY,
548 .udma_mask = ATA_UDMA5,
549 .port_ops = &ich_pata_ops,
550 },
551
552 [ich_pata_100_nomwdma1] =
553 {
554 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
555 .pio_mask = ATA_PIO4,
556 .mwdma_mask = ATA_MWDMA2_ONLY,
557 .udma_mask = ATA_UDMA5,
558 .port_ops = &ich_pata_ops,
559 },
560
561 [ich5_sata] =
562 {
563 .flags = PIIX_SATA_FLAGS,
564 .pio_mask = ATA_PIO4,
565 .mwdma_mask = ATA_MWDMA2,
566 .udma_mask = ATA_UDMA6,
567 .port_ops = &piix_sata_ops,
568 },
569
570 [ich6_sata] =
571 {
572 .flags = PIIX_SATA_FLAGS,
573 .pio_mask = ATA_PIO4,
574 .mwdma_mask = ATA_MWDMA2,
575 .udma_mask = ATA_UDMA6,
576 .port_ops = &piix_sata_ops,
577 },
578
579 [ich6m_sata] =
580 {
581 .flags = PIIX_SATA_FLAGS,
582 .pio_mask = ATA_PIO4,
583 .mwdma_mask = ATA_MWDMA2,
584 .udma_mask = ATA_UDMA6,
585 .port_ops = &piix_sata_ops,
586 },
587
588 [ich8_sata] =
589 {
590 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
591 .pio_mask = ATA_PIO4,
592 .mwdma_mask = ATA_MWDMA2,
593 .udma_mask = ATA_UDMA6,
594 .port_ops = &piix_sata_ops,
595 },
596
597 [ich8_2port_sata] =
598 {
599 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
600 .pio_mask = ATA_PIO4,
601 .mwdma_mask = ATA_MWDMA2,
602 .udma_mask = ATA_UDMA6,
603 .port_ops = &piix_sata_ops,
604 },
605
606 [tolapai_sata] =
607 {
608 .flags = PIIX_SATA_FLAGS,
609 .pio_mask = ATA_PIO4,
610 .mwdma_mask = ATA_MWDMA2,
611 .udma_mask = ATA_UDMA6,
612 .port_ops = &piix_sata_ops,
613 },
614
615 [ich8m_apple_sata] =
616 {
617 .flags = PIIX_SATA_FLAGS,
618 .pio_mask = ATA_PIO4,
619 .mwdma_mask = ATA_MWDMA2,
620 .udma_mask = ATA_UDMA6,
621 .port_ops = &piix_sata_ops,
622 },
623
624 [piix_pata_vmw] =
625 {
626 .flags = PIIX_PATA_FLAGS,
627 .pio_mask = ATA_PIO4,
628 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
629 .udma_mask = ATA_UDMA2,
630 .port_ops = &piix_vmw_ops,
631 },
632
633 /*
634 * some Sandybridge chipsets have broken 32 mode up to now,
635 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
636 */
637 [ich8_sata_snb] =
638 {
639 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
640 .pio_mask = ATA_PIO4,
641 .mwdma_mask = ATA_MWDMA2,
642 .udma_mask = ATA_UDMA6,
643 .port_ops = &piix_sata_ops,
644 },
645
646};
647
648static struct pci_bits piix_enable_bits[] = { 427static struct pci_bits piix_enable_bits[] = {
649 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 428 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
650 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 429 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
@@ -1261,6 +1040,193 @@ static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1261 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1040 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1262} 1041}
1263 1042
1043static struct scsi_host_template piix_sht = {
1044 ATA_BMDMA_SHT(DRV_NAME),
1045};
1046
1047static struct ata_port_operations piix_sata_ops = {
1048 .inherits = &ata_bmdma32_port_ops,
1049 .sff_irq_check = piix_irq_check,
1050 .port_start = piix_port_start,
1051};
1052
1053static struct ata_port_operations piix_pata_ops = {
1054 .inherits = &piix_sata_ops,
1055 .cable_detect = ata_cable_40wire,
1056 .set_piomode = piix_set_piomode,
1057 .set_dmamode = piix_set_dmamode,
1058 .prereset = piix_pata_prereset,
1059};
1060
1061static struct ata_port_operations piix_vmw_ops = {
1062 .inherits = &piix_pata_ops,
1063 .bmdma_status = piix_vmw_bmdma_status,
1064};
1065
1066static struct ata_port_operations ich_pata_ops = {
1067 .inherits = &piix_pata_ops,
1068 .cable_detect = ich_pata_cable_detect,
1069 .set_dmamode = ich_set_dmamode,
1070};
1071
1072static struct device_attribute *piix_sidpr_shost_attrs[] = {
1073 &dev_attr_link_power_management_policy,
1074 NULL
1075};
1076
1077static struct scsi_host_template piix_sidpr_sht = {
1078 ATA_BMDMA_SHT(DRV_NAME),
1079 .shost_attrs = piix_sidpr_shost_attrs,
1080};
1081
1082static struct ata_port_operations piix_sidpr_sata_ops = {
1083 .inherits = &piix_sata_ops,
1084 .hardreset = sata_std_hardreset,
1085 .scr_read = piix_sidpr_scr_read,
1086 .scr_write = piix_sidpr_scr_write,
1087 .set_lpm = piix_sidpr_set_lpm,
1088};
1089
1090static struct ata_port_info piix_port_info[] = {
1091 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1092 {
1093 .flags = PIIX_PATA_FLAGS,
1094 .pio_mask = ATA_PIO4,
1095 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1096 .port_ops = &piix_pata_ops,
1097 },
1098
1099 [piix_pata_33] = /* PIIX4 at 33MHz */
1100 {
1101 .flags = PIIX_PATA_FLAGS,
1102 .pio_mask = ATA_PIO4,
1103 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1104 .udma_mask = ATA_UDMA2,
1105 .port_ops = &piix_pata_ops,
1106 },
1107
1108 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1109 {
1110 .flags = PIIX_PATA_FLAGS,
1111 .pio_mask = ATA_PIO4,
1112 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1113 .udma_mask = ATA_UDMA2,
1114 .port_ops = &ich_pata_ops,
1115 },
1116
1117 [ich_pata_66] = /* ICH controllers up to 66MHz */
1118 {
1119 .flags = PIIX_PATA_FLAGS,
1120 .pio_mask = ATA_PIO4,
1121 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1122 .udma_mask = ATA_UDMA4,
1123 .port_ops = &ich_pata_ops,
1124 },
1125
1126 [ich_pata_100] =
1127 {
1128 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1129 .pio_mask = ATA_PIO4,
1130 .mwdma_mask = ATA_MWDMA12_ONLY,
1131 .udma_mask = ATA_UDMA5,
1132 .port_ops = &ich_pata_ops,
1133 },
1134
1135 [ich_pata_100_nomwdma1] =
1136 {
1137 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1138 .pio_mask = ATA_PIO4,
1139 .mwdma_mask = ATA_MWDMA2_ONLY,
1140 .udma_mask = ATA_UDMA5,
1141 .port_ops = &ich_pata_ops,
1142 },
1143
1144 [ich5_sata] =
1145 {
1146 .flags = PIIX_SATA_FLAGS,
1147 .pio_mask = ATA_PIO4,
1148 .mwdma_mask = ATA_MWDMA2,
1149 .udma_mask = ATA_UDMA6,
1150 .port_ops = &piix_sata_ops,
1151 },
1152
1153 [ich6_sata] =
1154 {
1155 .flags = PIIX_SATA_FLAGS,
1156 .pio_mask = ATA_PIO4,
1157 .mwdma_mask = ATA_MWDMA2,
1158 .udma_mask = ATA_UDMA6,
1159 .port_ops = &piix_sata_ops,
1160 },
1161
1162 [ich6m_sata] =
1163 {
1164 .flags = PIIX_SATA_FLAGS,
1165 .pio_mask = ATA_PIO4,
1166 .mwdma_mask = ATA_MWDMA2,
1167 .udma_mask = ATA_UDMA6,
1168 .port_ops = &piix_sata_ops,
1169 },
1170
1171 [ich8_sata] =
1172 {
1173 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1174 .pio_mask = ATA_PIO4,
1175 .mwdma_mask = ATA_MWDMA2,
1176 .udma_mask = ATA_UDMA6,
1177 .port_ops = &piix_sata_ops,
1178 },
1179
1180 [ich8_2port_sata] =
1181 {
1182 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1183 .pio_mask = ATA_PIO4,
1184 .mwdma_mask = ATA_MWDMA2,
1185 .udma_mask = ATA_UDMA6,
1186 .port_ops = &piix_sata_ops,
1187 },
1188
1189 [tolapai_sata] =
1190 {
1191 .flags = PIIX_SATA_FLAGS,
1192 .pio_mask = ATA_PIO4,
1193 .mwdma_mask = ATA_MWDMA2,
1194 .udma_mask = ATA_UDMA6,
1195 .port_ops = &piix_sata_ops,
1196 },
1197
1198 [ich8m_apple_sata] =
1199 {
1200 .flags = PIIX_SATA_FLAGS,
1201 .pio_mask = ATA_PIO4,
1202 .mwdma_mask = ATA_MWDMA2,
1203 .udma_mask = ATA_UDMA6,
1204 .port_ops = &piix_sata_ops,
1205 },
1206
1207 [piix_pata_vmw] =
1208 {
1209 .flags = PIIX_PATA_FLAGS,
1210 .pio_mask = ATA_PIO4,
1211 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1212 .udma_mask = ATA_UDMA2,
1213 .port_ops = &piix_vmw_ops,
1214 },
1215
1216 /*
1217 * some Sandybridge chipsets have broken 32 mode up to now,
1218 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1219 */
1220 [ich8_sata_snb] =
1221 {
1222 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1223 .pio_mask = ATA_PIO4,
1224 .mwdma_mask = ATA_MWDMA2,
1225 .udma_mask = ATA_UDMA6,
1226 .port_ops = &piix_sata_ops,
1227 },
1228};
1229
1264#define AHCI_PCI_BAR 5 1230#define AHCI_PCI_BAR 5
1265#define AHCI_GLOBAL_CTL 0x04 1231#define AHCI_GLOBAL_CTL 0x04
1266#define AHCI_ENABLE (1 << 31) 1232#define AHCI_ENABLE (1 << 31)
@@ -1746,6 +1712,17 @@ static void piix_remove_one(struct pci_dev *pdev)
1746 ata_pci_remove_one(pdev); 1712 ata_pci_remove_one(pdev);
1747} 1713}
1748 1714
1715static struct pci_driver piix_pci_driver = {
1716 .name = DRV_NAME,
1717 .id_table = piix_pci_tbl,
1718 .probe = piix_init_one,
1719 .remove = piix_remove_one,
1720#ifdef CONFIG_PM
1721 .suspend = piix_pci_device_suspend,
1722 .resume = piix_pci_device_resume,
1723#endif
1724};
1725
1749static int __init piix_init(void) 1726static int __init piix_init(void)
1750{ 1727{
1751 int rc; 1728 int rc;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 17:33:58 -0400