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authorThierry Reding <treding@nvidia.com>2013-09-30 09:14:41 -0400
committerThierry Reding <treding@nvidia.com>2013-10-31 04:55:42 -0400
commitf27db9615ad6c0bad6047d0592cfc627b9997f8a (patch)
treedfcdcad1056a02b91f5246d1a7ad8376e9da4163
parent5407f31bd37d1289dfd0a2a23a45c5ff2aec8e58 (diff)
drm/tegra: hdmi: Rename tegra{2,3} to tegra{20,30}
Everything related to Tegra uses Tegra20 and Tegra30 instead of Tegra2 and Tegra3, respectively. Rename the TMDS arrays in the HDMI driver for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 3a00cb078041..ed7c58fa595c 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -144,7 +144,7 @@ struct tmds_config {
144 u32 drive_current; 144 u32 drive_current;
145}; 145};
146 146
147static const struct tmds_config tegra2_tmds_config[] = { 147static const struct tmds_config tegra20_tmds_config[] = {
148 { /* slow pixel clock modes */ 148 { /* slow pixel clock modes */
149 .pclk = 27000000, 149 .pclk = 27000000,
150 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 150 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
@@ -177,7 +177,7 @@ static const struct tmds_config tegra2_tmds_config[] = {
177 }, 177 },
178}; 178};
179 179
180static const struct tmds_config tegra3_tmds_config[] = { 180static const struct tmds_config tegra30_tmds_config[] = {
181 { /* 480p modes */ 181 { /* 480p modes */
182 .pclk = 27000000, 182 .pclk = 27000000,
183 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 183 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
@@ -704,11 +704,11 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
704 704
705 /* TMDS CONFIG */ 705 /* TMDS CONFIG */
706 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { 706 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
707 num_tmds = ARRAY_SIZE(tegra3_tmds_config); 707 num_tmds = ARRAY_SIZE(tegra30_tmds_config);
708 tmds = tegra3_tmds_config; 708 tmds = tegra30_tmds_config;
709 } else { 709 } else {
710 num_tmds = ARRAY_SIZE(tegra2_tmds_config); 710 num_tmds = ARRAY_SIZE(tegra20_tmds_config);
711 tmds = tegra2_tmds_config; 711 tmds = tegra20_tmds_config;
712 } 712 }
713 713
714 for (i = 0; i < num_tmds; i++) { 714 for (i = 0; i < num_tmds; i++) {