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authorArnd Bergmann <arnd@arndb.de>2013-06-19 20:10:42 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-19 20:10:42 -0400
commitf25a4d68f8ca83132dcfb8607d55fc71b12956c0 (patch)
tree8da8920f3158b73701d824bf8f90e400715bad2f
parentd5a51af940efec07c969bdb5fe478bb518116404 (diff)
parent3bfbc6cd9b41f937a134ba65a4a1eefba062b9a8 (diff)
Merge tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
This is a dependency for imx/dt Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt13
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/imx6sl-clock.txt10
-rw-r--r--Documentation/devicetree/bindings/clock/vf610-clock.txt26
-rw-r--r--arch/arm/Kconfig.debug13
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig10
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/mach-imx/Kconfig63
-rw-r--r--arch/arm/mach-imx/Makefile4
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c73
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c48
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c267
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c10
-rw-r--r--arch/arm/mach-imx/clk-vf610.c319
-rw-r--r--arch/arm/mach-imx/clk.c35
-rw-r--r--arch/arm/mach-imx/clk.h4
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/hardware.h1
-rw-r--r--arch/arm/mach-imx/imx25-dt.c2
-rw-r--r--arch/arm/mach-imx/imx27-dt.c2
-rw-r--r--arch/arm/mach-imx/imx31-dt.c2
-rw-r--r--arch/arm/mach-imx/imx51-dt.c2
-rw-r--r--arch/arm/mach-imx/irq-common.c1
-rw-r--r--arch/arm/mach-imx/mach-imx53.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c81
-rw-r--r--arch/arm/mach-imx/mach-imx6sl.c52
-rw-r--r--arch/arm/mach-imx/mach-pca100.c4
-rw-r--r--arch/arm/mach-imx/mach-vf610.c48
-rw-r--r--arch/arm/mach-imx/mm-imx1.c2
-rw-r--r--arch/arm/mach-imx/mm-imx21.c2
-rw-r--r--arch/arm/mach-imx/mm-imx25.c2
-rw-r--r--arch/arm/mach-imx/mm-imx27.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c4
-rw-r--r--arch/arm/mach-imx/mm-imx5.c3
-rw-r--r--arch/arm/mach-imx/system.c47
-rw-r--r--arch/arm/mach-imx/ulpi.c118
-rw-r--r--arch/arm/mach-imx/ulpi.h11
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h148
-rw-r--r--include/dt-bindings/clock/vf610-clock.h163
39 files changed, 1374 insertions, 234 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index d71b4b2c077d..f46f5625d8ad 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -184,6 +184,19 @@ clocks and IDs.
184 cko2 170 184 cko2 170
185 srtc_gate 171 185 srtc_gate 171
186 pata_gate 172 186 pata_gate 172
187 sata_gate 173
188 spdif_xtal_sel 174
189 spdif0_sel 175
190 spdif1_sel 176
191 spdif0_pred 177
192 spdif0_podf 178
193 spdif1_pred 179
194 spdif1_podf 180
195 spdif0_com_sel 181
196 spdif1_com_sel 182
197 spdif0_gate 183
198 spdif1_gate 184
199 spdif_ipg_gate 185
187 200
188Examples (for mx53): 201Examples (for mx53):
189 202
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6deb6fd1c7cd..a0e104f0527e 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -208,6 +208,7 @@ clocks and IDs.
208 pll4_post_div 193 208 pll4_post_div 193
209 pll5_post_div 194 209 pll5_post_div 194
210 pll5_video_div 195 210 pll5_video_div 195
211 eim_slow 196
211 212
212Examples: 213Examples:
213 214
diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
new file mode 100644
index 000000000000..15e40bdf147d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
@@ -0,0 +1,10 @@
1* Clock bindings for Freescale i.MX6 SoloLite
2
3Required properties:
4- compatible: Should be "fsl,imx6sl-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
10for the full list of i.MX6 SoloLite clock IDs.
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
new file mode 100644
index 000000000000..c80863d344ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -0,0 +1,26 @@
1* Clock bindings for Freescale Vybrid VF610 SOC
2
3Required properties:
4- compatible: Should be "fsl,vf610-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
10for the full list of VF610 clock IDs.
11
12Examples:
13
14clks: ccm@4006b000 {
15 compatible = "fsl,vf610-ccm";
16 reg = <0x4006b000 0x1000>;
17 #clock-cells = <1>;
18};
19
20uart1: serial@40028000 {
21 compatible = "fsl,vf610-uart";
22 reg = <0x40028000 0x1000>;
23 interrupts = <0 62 0x04>;
24 clocks = <&clks VF610_CLK_UART1>;
25 clock-names = "ipg";
26};
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908d5cda..29f7623553c1 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -251,6 +251,13 @@ choice
251 Say Y here if you want kernel low-level debugging support 251 Say Y here if you want kernel low-level debugging support
252 on i.MX6Q/DL. 252 on i.MX6Q/DL.
253 253
254 config DEBUG_IMX6SL_UART
255 bool "i.MX6SL Debug UART"
256 depends on SOC_IMX6SL
257 help
258 Say Y here if you want kernel low-level debugging support
259 on i.MX6SL.
260
254 config DEBUG_MMP_UART2 261 config DEBUG_MMP_UART2
255 bool "Kernel low-level debugging message via MMP UART2" 262 bool "Kernel low-level debugging message via MMP UART2"
256 depends on ARCH_MMP 263 depends on ARCH_MMP
@@ -532,7 +539,8 @@ config DEBUG_IMX_UART_PORT
532 DEBUG_IMX35_UART || \ 539 DEBUG_IMX35_UART || \
533 DEBUG_IMX51_UART || \ 540 DEBUG_IMX51_UART || \
534 DEBUG_IMX53_UART || \ 541 DEBUG_IMX53_UART || \
535 DEBUG_IMX6Q_UART 542 DEBUG_IMX6Q_UART || \
543 DEBUG_IMX6SL_UART
536 default 1 544 default 1
537 depends on ARCH_MXC 545 depends on ARCH_MXC
538 help 546 help
@@ -631,7 +639,8 @@ config DEBUG_LL_INCLUDE
631 DEBUG_IMX35_UART || \ 639 DEBUG_IMX35_UART || \
632 DEBUG_IMX51_UART || \ 640 DEBUG_IMX51_UART || \
633 DEBUG_IMX53_UART ||\ 641 DEBUG_IMX53_UART ||\
634 DEBUG_IMX6Q_UART 642 DEBUG_IMX6Q_UART || \
643 DEBUG_IMX6SL_UART
635 default "debug/mvebu.S" if DEBUG_MVEBU_UART 644 default "debug/mvebu.S" if DEBUG_MVEBU_UART
636 default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART 645 default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
637 default "debug/nomadik.S" if DEBUG_NOMADIK_UART 646 default "debug/nomadik.S" if DEBUG_NOMADIK_UART
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f248b5..06686e7303a9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y
37CONFIG_MACH_EUKREA_CPUIMX51SD=y 37CONFIG_MACH_EUKREA_CPUIMX51SD=y
38CONFIG_SOC_IMX53=y 38CONFIG_SOC_IMX53=y
39CONFIG_SOC_IMX6Q=y 39CONFIG_SOC_IMX6Q=y
40CONFIG_SOC_IMX6SL=y
41CONFIG_SOC_VF610=y
40CONFIG_MXC_PWM=y 42CONFIG_MXC_PWM=y
41CONFIG_SMP=y 43CONFIG_SMP=y
42CONFIG_VMSPLIT_2G=y 44CONFIG_VMSPLIT_2G=y
@@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
47CONFIG_VFP=y 49CONFIG_VFP=y
48CONFIG_NEON=y 50CONFIG_NEON=y
49CONFIG_BINFMT_MISC=m 51CONFIG_BINFMT_MISC=m
52CONFIG_PM_RUNTIME=y
50CONFIG_PM_DEBUG=y 53CONFIG_PM_DEBUG=y
51CONFIG_PM_TEST_SUSPEND=y 54CONFIG_PM_TEST_SUSPEND=y
52CONFIG_NET=y 55CONFIG_NET=y
@@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
170CONFIG_LCD_CLASS_DEVICE=y 173CONFIG_LCD_CLASS_DEVICE=y
171CONFIG_LCD_L4F00242T03=y 174CONFIG_LCD_L4F00242T03=y
172CONFIG_BACKLIGHT_CLASS_DEVICE=y 175CONFIG_BACKLIGHT_CLASS_DEVICE=y
176CONFIG_BACKLIGHT_PWM=y
173CONFIG_FRAMEBUFFER_CONSOLE=y 177CONFIG_FRAMEBUFFER_CONSOLE=y
174CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 178CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
175CONFIG_FONTS=y 179CONFIG_FONTS=y
@@ -182,6 +186,7 @@ CONFIG_SND_SOC=y
182CONFIG_SND_IMX_SOC=y 186CONFIG_SND_IMX_SOC=y
183CONFIG_SND_SOC_PHYCORE_AC97=y 187CONFIG_SND_SOC_PHYCORE_AC97=y
184CONFIG_SND_SOC_EUKREA_TLV320=y 188CONFIG_SND_SOC_EUKREA_TLV320=y
189CONFIG_SND_SOC_IMX_WM8962=y
185CONFIG_SND_SOC_IMX_SGTL5000=y 190CONFIG_SND_SOC_IMX_SGTL5000=y
186CONFIG_SND_SOC_IMX_MC13783=y 191CONFIG_SND_SOC_IMX_MC13783=y
187CONFIG_USB=y 192CONFIG_USB=y
@@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y
208CONFIG_MXS_DMA=y 213CONFIG_MXS_DMA=y
209CONFIG_STAGING=y 214CONFIG_STAGING=y
210CONFIG_DRM_IMX=y 215CONFIG_DRM_IMX=y
216CONFIG_DRM_IMX_TVE=y
217CONFIG_DRM_IMX_FB_HELPER=y
218CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
211CONFIG_DRM_IMX_IPUV3_CORE=y 219CONFIG_DRM_IMX_IPUV3_CORE=y
212CONFIG_DRM_IMX_IPUV3=y 220CONFIG_DRM_IMX_IPUV3=y
213CONFIG_COMMON_CLK_DEBUG=y 221CONFIG_COMMON_CLK_DEBUG=y
214# CONFIG_IOMMU_SUPPORT is not set 222# CONFIG_IOMMU_SUPPORT is not set
223CONFIG_PWM=y
224CONFIG_PWM_IMX=y
215CONFIG_EXT2_FS=y 225CONFIG_EXT2_FS=y
216CONFIG_EXT2_FS_XATTR=y 226CONFIG_EXT2_FS_XATTR=y
217CONFIG_EXT2_FS_POSIX_ACL=y 227CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67 67
68#define IMX6SL_UART1_BASE_ADDR 0x02020000
69#define IMX6SL_UART2_BASE_ADDR 0x02024000
70#define IMX6SL_UART3_BASE_ADDR 0x02034000
71#define IMX6SL_UART4_BASE_ADDR 0x02038000
72#define IMX6SL_UART5_BASE_ADDR 0x02018000
73#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
74#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
75
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 76#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69 77
70#ifdef CONFIG_DEBUG_IMX1_UART 78#ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 91#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART) 92#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
94#elif defined(CONFIG_DEBUG_IMX6SL_UART)
95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
86#endif 96#endif
87 97
88#endif /* __DEBUG_IMX_UART_H */ 98#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328464f3..f25cf888f3d4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -56,9 +56,6 @@ config MXC_USE_EPIT
56 uses the same clocks as the GPT. Anyway, on some systems the GPT 56 uses the same clocks as the GPT. Anyway, on some systems the GPT
57 may be in use for other purposes. 57 may be in use for other purposes.
58 58
59config MXC_ULPI
60 bool
61
62config ARCH_HAS_RNGA 59config ARCH_HAS_RNGA
63 bool 60 bool
64 61
@@ -233,7 +230,7 @@ config MACH_EUKREA_CPUIMX25SD
233 select IMX_HAVE_PLATFORM_MXC_EHCI 230 select IMX_HAVE_PLATFORM_MXC_EHCI
234 select IMX_HAVE_PLATFORM_MXC_NAND 231 select IMX_HAVE_PLATFORM_MXC_NAND
235 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 232 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
236 select MXC_ULPI if USB_ULPI 233 select USB_ULPI_VIEWPORT if USB_ULPI
237 select SOC_IMX25 234 select SOC_IMX25
238 235
239choice 236choice
@@ -284,7 +281,7 @@ config MACH_PCM038
284 select IMX_HAVE_PLATFORM_MXC_NAND 281 select IMX_HAVE_PLATFORM_MXC_NAND
285 select IMX_HAVE_PLATFORM_MXC_W1 282 select IMX_HAVE_PLATFORM_MXC_W1
286 select IMX_HAVE_PLATFORM_SPI_IMX 283 select IMX_HAVE_PLATFORM_SPI_IMX
287 select MXC_ULPI if USB_ULPI 284 select USB_ULPI_VIEWPORT if USB_ULPI
288 select SOC_IMX27 285 select SOC_IMX27
289 help 286 help
290 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 287 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -314,7 +311,7 @@ config MACH_CPUIMX27
314 select IMX_HAVE_PLATFORM_MXC_EHCI 311 select IMX_HAVE_PLATFORM_MXC_EHCI
315 select IMX_HAVE_PLATFORM_MXC_NAND 312 select IMX_HAVE_PLATFORM_MXC_NAND
316 select IMX_HAVE_PLATFORM_MXC_W1 313 select IMX_HAVE_PLATFORM_MXC_W1
317 select MXC_ULPI if USB_ULPI 314 select USB_ULPI_VIEWPORT if USB_ULPI
318 select SOC_IMX27 315 select SOC_IMX27
319 help 316 help
320 Include support for Eukrea CPUIMX27 platform. This includes 317 Include support for Eukrea CPUIMX27 platform. This includes
@@ -369,7 +366,7 @@ config MACH_MX27_3DS
369 select IMX_HAVE_PLATFORM_MXC_MMC 366 select IMX_HAVE_PLATFORM_MXC_MMC
370 select IMX_HAVE_PLATFORM_SPI_IMX 367 select IMX_HAVE_PLATFORM_SPI_IMX
371 select MXC_DEBUG_BOARD 368 select MXC_DEBUG_BOARD
372 select MXC_ULPI if USB_ULPI 369 select USB_ULPI_VIEWPORT if USB_ULPI
373 select SOC_IMX27 370 select SOC_IMX27
374 help 371 help
375 Include support for MX27PDK platform. This includes specific 372 Include support for MX27PDK platform. This includes specific
@@ -414,7 +411,7 @@ config MACH_PCA100
414 select IMX_HAVE_PLATFORM_MXC_NAND 411 select IMX_HAVE_PLATFORM_MXC_NAND
415 select IMX_HAVE_PLATFORM_MXC_W1 412 select IMX_HAVE_PLATFORM_MXC_W1
416 select IMX_HAVE_PLATFORM_SPI_IMX 413 select IMX_HAVE_PLATFORM_SPI_IMX
417 select MXC_ULPI if USB_ULPI 414 select USB_ULPI_VIEWPORT if USB_ULPI
418 select SOC_IMX27 415 select SOC_IMX27
419 help 416 help
420 Include support for phyCARD-s (aka pca100) platform. This 417 Include support for phyCARD-s (aka pca100) platform. This
@@ -481,7 +478,7 @@ config MACH_MX31LILLY
481 select IMX_HAVE_PLATFORM_MXC_EHCI 478 select IMX_HAVE_PLATFORM_MXC_EHCI
482 select IMX_HAVE_PLATFORM_MXC_MMC 479 select IMX_HAVE_PLATFORM_MXC_MMC
483 select IMX_HAVE_PLATFORM_SPI_IMX 480 select IMX_HAVE_PLATFORM_SPI_IMX
484 select MXC_ULPI if USB_ULPI 481 select USB_ULPI_VIEWPORT if USB_ULPI
485 select SOC_IMX31 482 select SOC_IMX31
486 help 483 help
487 Include support for mx31 based LILLY1131 modules. This includes 484 Include support for mx31 based LILLY1131 modules. This includes
@@ -497,7 +494,7 @@ config MACH_MX31LITE
497 select IMX_HAVE_PLATFORM_MXC_RTC 494 select IMX_HAVE_PLATFORM_MXC_RTC
498 select IMX_HAVE_PLATFORM_SPI_IMX 495 select IMX_HAVE_PLATFORM_SPI_IMX
499 select LEDS_GPIO_REGISTER 496 select LEDS_GPIO_REGISTER
500 select MXC_ULPI if USB_ULPI 497 select USB_ULPI_VIEWPORT if USB_ULPI
501 select SOC_IMX31 498 select SOC_IMX31
502 help 499 help
503 Include support for MX31 LITEKIT platform. This includes specific 500 Include support for MX31 LITEKIT platform. This includes specific
@@ -514,7 +511,7 @@ config MACH_PCM037
514 select IMX_HAVE_PLATFORM_MXC_MMC 511 select IMX_HAVE_PLATFORM_MXC_MMC
515 select IMX_HAVE_PLATFORM_MXC_NAND 512 select IMX_HAVE_PLATFORM_MXC_NAND
516 select IMX_HAVE_PLATFORM_MXC_W1 513 select IMX_HAVE_PLATFORM_MXC_W1
517 select MXC_ULPI if USB_ULPI 514 select USB_ULPI_VIEWPORT if USB_ULPI
518 select SOC_IMX31 515 select SOC_IMX31
519 help 516 help
520 Include support for Phytec pcm037 platform. This includes 517 Include support for Phytec pcm037 platform. This includes
@@ -544,7 +541,7 @@ config MACH_MX31_3DS
544 select IMX_HAVE_PLATFORM_MXC_NAND 541 select IMX_HAVE_PLATFORM_MXC_NAND
545 select IMX_HAVE_PLATFORM_SPI_IMX 542 select IMX_HAVE_PLATFORM_SPI_IMX
546 select MXC_DEBUG_BOARD 543 select MXC_DEBUG_BOARD
547 select MXC_ULPI if USB_ULPI 544 select USB_ULPI_VIEWPORT if USB_ULPI
548 select SOC_IMX31 545 select SOC_IMX31
549 help 546 help
550 Include support for MX31PDK (3DS) platform. This includes specific 547 Include support for MX31PDK (3DS) platform. This includes specific
@@ -571,7 +568,7 @@ config MACH_MX31MOBOARD
571 select IMX_HAVE_PLATFORM_MXC_MMC 568 select IMX_HAVE_PLATFORM_MXC_MMC
572 select IMX_HAVE_PLATFORM_SPI_IMX 569 select IMX_HAVE_PLATFORM_SPI_IMX
573 select LEDS_GPIO_REGISTER 570 select LEDS_GPIO_REGISTER
574 select MXC_ULPI if USB_ULPI 571 select USB_ULPI_VIEWPORT if USB_ULPI
575 select SOC_IMX31 572 select SOC_IMX31
576 help 573 help
577 Include support for mx31moboard platform. This includes specific 574 Include support for mx31moboard platform. This includes specific
@@ -595,7 +592,7 @@ config MACH_ARMADILLO5X0
595 select IMX_HAVE_PLATFORM_MXC_EHCI 592 select IMX_HAVE_PLATFORM_MXC_EHCI
596 select IMX_HAVE_PLATFORM_MXC_MMC 593 select IMX_HAVE_PLATFORM_MXC_MMC
597 select IMX_HAVE_PLATFORM_MXC_NAND 594 select IMX_HAVE_PLATFORM_MXC_NAND
598 select MXC_ULPI if USB_ULPI 595 select USB_ULPI_VIEWPORT if USB_ULPI
599 select SOC_IMX31 596 select SOC_IMX31
600 help 597 help
601 Include support for Atmark Armadillo-500 platform. This includes 598 Include support for Atmark Armadillo-500 platform. This includes
@@ -639,7 +636,7 @@ config MACH_PCM043
639 select IMX_HAVE_PLATFORM_MXC_EHCI 636 select IMX_HAVE_PLATFORM_MXC_EHCI
640 select IMX_HAVE_PLATFORM_MXC_NAND 637 select IMX_HAVE_PLATFORM_MXC_NAND
641 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 638 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
642 select MXC_ULPI if USB_ULPI 639 select USB_ULPI_VIEWPORT if USB_ULPI
643 select SOC_IMX35 640 select SOC_IMX35
644 help 641 help
645 Include support for Phytec pcm043 platform. This includes 642 Include support for Phytec pcm043 platform. This includes
@@ -673,7 +670,7 @@ config MACH_EUKREA_CPUIMX35SD
673 select IMX_HAVE_PLATFORM_MXC_EHCI 670 select IMX_HAVE_PLATFORM_MXC_EHCI
674 select IMX_HAVE_PLATFORM_MXC_NAND 671 select IMX_HAVE_PLATFORM_MXC_NAND
675 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 672 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
676 select MXC_ULPI if USB_ULPI 673 select USB_ULPI_VIEWPORT if USB_ULPI
677 select SOC_IMX35 674 select SOC_IMX35
678 help 675 help
679 Include support for Eukrea CPUIMX35 platform. This includes 676 Include support for Eukrea CPUIMX35 platform. This includes
@@ -816,6 +813,40 @@ config SOC_IMX6Q
816 help 813 help
817 This enables support for Freescale i.MX6 Quad processor. 814 This enables support for Freescale i.MX6 Quad processor.
818 815
816config SOC_IMX6SL
817 bool "i.MX6 SoloLite support"
818 select ARM_ERRATA_754322
819 select ARM_ERRATA_775420
820 select ARM_GIC
821 select CPU_V7
822 select HAVE_IMX_ANATOP
823 select HAVE_IMX_GPC
824 select HAVE_IMX_MMDC
825 select HAVE_IMX_SRC
826 select PINCTRL
827 select PINCTRL_IMX6SL
828 select PL310_ERRATA_588369 if CACHE_PL310
829 select PL310_ERRATA_727915 if CACHE_PL310
830 select PL310_ERRATA_769419 if CACHE_PL310
831
832 help
833 This enables support for Freescale i.MX6 SoloLite processor.
834
835config SOC_VF610
836 bool "Vybrid Family VF610 support"
837 select CPU_V7
838 select ARM_GIC
839 select CLKSRC_OF
840 select PINCTRL
841 select PINCTRL_VF610
842 select VF_PIT_TIMER
843 select PL310_ERRATA_588369 if CACHE_PL310
844 select PL310_ERRATA_727915 if CACHE_PL310
845 select PL310_ERRATA_769419 if CACHE_PL310
846
847 help
848 This enable support for Freescale Vybrid VF610 processor.
849
819endif 850endif
820 851
821source "arch/arm/mach-imx/devices/Kconfig" 852source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c490ac0..e20f22d58fd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
23obj-$(CONFIG_MXC_TZIC) += tzic.o 23obj-$(CONFIG_MXC_TZIC) += tzic.o
24obj-$(CONFIG_MXC_AVIC) += avic.o 24obj-$(CONFIG_MXC_AVIC) += avic.o
25 25
26obj-$(CONFIG_MXC_ULPI) += ulpi.o
27obj-$(CONFIG_MXC_USE_EPIT) += epit.o 26obj-$(CONFIG_MXC_USE_EPIT) += epit.o
28obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 27obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
29 28
@@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
98obj-$(CONFIG_SMP) += headsmp.o platsmp.o 97obj-$(CONFIG_SMP) += headsmp.o platsmp.o
99obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 98obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
100obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 99obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
100obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
101 101
102ifeq ($(CONFIG_PM),y) 102ifeq ($(CONFIG_PM),y)
103obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o 103obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
@@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
111obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 111obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
112obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 112obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
113 113
114obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
115
114obj-y += devices/ 116obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b6a3c6..04b1bad68350 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
73 "tve_sel", "lp_apm", 73 "tve_sel", "lp_apm",
74 "uart_root", "dummy"/* spdif0_clk_root */, 74 "uart_root", "dummy"/* spdif0_clk_root */,
75 "dummy", "dummy", }; 75 "dummy", "dummy", };
76static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
77static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
78static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
79static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
80static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
81
76 82
77enum imx5_clks { 83enum imx5_clks {
78 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, 84 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
110 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, 116 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
111 cko1_sel, cko1_podf, cko1, 117 cko1_sel, cko1_podf, cko1,
112 cko2_sel, cko2_podf, cko2, 118 cko2_sel, cko2_podf, cko2,
113 srtc_gate, pata_gate, 119 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
120 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
121 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
114 clk_max 122 clk_max
115}; 123};
116 124
@@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
123{ 131{
124 int i; 132 int i;
125 133
134 of_clk_init(NULL);
135
126 clk[dummy] = imx_clk_fixed("dummy", 0); 136 clk[dummy] = imx_clk_fixed("dummy", 0);
127 clk[ckil] = imx_clk_fixed("ckil", rate_ckil); 137 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
128 clk[osc] = imx_clk_fixed("osc", rate_osc); 138 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
129 clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1); 139 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
130 clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2); 140 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
131 141
132 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, 142 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
133 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 143 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
267 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); 277 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
268 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); 278 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
269 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); 279 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
280 clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
281 clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
282 clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
283 clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
284 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
285 clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
286 clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
270 287
271 for (i = 0; i < ARRAY_SIZE(clk); i++) 288 for (i = 0; i < ARRAY_SIZE(clk); i++)
272 if (IS_ERR(clk[i])) 289 if (IS_ERR(clk[i]))
@@ -378,6 +395,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
378 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); 395 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
379 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); 396 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
380 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); 397 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
398 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
399 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
400 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
401 spdif_sel, ARRAY_SIZE(spdif_sel));
402 clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
403 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
404 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
405 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
406 clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
381 407
382 for (i = 0; i < ARRAY_SIZE(clk); i++) 408 for (i = 0; i < ARRAY_SIZE(clk); i++)
383 if (IS_ERR(clk[i])) 409 if (IS_ERR(clk[i]))
@@ -485,6 +511,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
485 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); 511 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
486 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 512 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
487 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 513 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
514 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
488 515
489 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, 516 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
490 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); 517 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -495,6 +522,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
495 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); 522 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
496 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); 523 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
497 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 524 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
525 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
526 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
498 527
499 for (i = 0; i < ARRAY_SIZE(clk); i++) 528 for (i = 0; i < ARRAY_SIZE(clk); i++)
500 if (IS_ERR(clk[i])) 529 if (IS_ERR(clk[i]))
@@ -542,42 +571,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
542 return 0; 571 return 0;
543} 572}
544 573
545#ifdef CONFIG_OF
546static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
547 unsigned long *ckih1, unsigned long *ckih2)
548{
549 struct device_node *np;
550
551 /* retrieve the freqency of fixed clocks from device tree */
552 for_each_compatible_node(np, NULL, "fixed-clock") {
553 u32 rate;
554 if (of_property_read_u32(np, "clock-frequency", &rate))
555 continue;
556
557 if (of_device_is_compatible(np, "fsl,imx-ckil"))
558 *ckil = rate;
559 else if (of_device_is_compatible(np, "fsl,imx-osc"))
560 *osc = rate;
561 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
562 *ckih1 = rate;
563 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
564 *ckih2 = rate;
565 }
566}
567
568int __init mx51_clocks_init_dt(void) 574int __init mx51_clocks_init_dt(void)
569{ 575{
570 unsigned long ckil, osc, ckih1, ckih2; 576 return mx51_clocks_init(0, 0, 0, 0);
571
572 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
573 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
574} 577}
575 578
576int __init mx53_clocks_init_dt(void) 579int __init mx53_clocks_init_dt(void)
577{ 580{
578 unsigned long ckil, osc, ckih1, ckih2; 581 return mx53_clocks_init(0, 0, 0, 0);
579
580 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
581 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
582} 582}
583#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e3148ce852d..4282e99f5ca1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -238,7 +238,7 @@ enum mx6q_clks {
238 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 238 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
239 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 239 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
240 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 240 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
241 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max 241 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
242}; 242};
243 243
244static struct clk *clk[clk_max]; 244static struct clk *clk[clk_max];
@@ -270,27 +270,16 @@ static struct clk_div_table video_div_table[] = {
270 { } 270 { }
271}; 271};
272 272
273int __init mx6q_clocks_init(void) 273static void __init imx6q_clocks_init(struct device_node *ccm_node)
274{ 274{
275 struct device_node *np; 275 struct device_node *np;
276 void __iomem *base; 276 void __iomem *base;
277 int i, irq; 277 int i, irq;
278 278
279 clk[dummy] = imx_clk_fixed("dummy", 0); 279 clk[dummy] = imx_clk_fixed("dummy", 0);
280 280 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
281 /* retrieve the freqency of fixed clocks from device tree */ 281 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
282 for_each_compatible_node(np, NULL, "fixed-clock") { 282 clk[osc] = imx_obtain_fixed_clock("osc", 0);
283 u32 rate;
284 if (of_property_read_u32(np, "clock-frequency", &rate))
285 continue;
286
287 if (of_device_is_compatible(np, "fsl,imx-ckil"))
288 clk[ckil] = imx_clk_fixed("ckil", rate);
289 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
290 clk[ckih] = imx_clk_fixed("ckih", rate);
291 else if (of_device_is_compatible(np, "fsl,imx-osc"))
292 clk[osc] = imx_clk_fixed("osc", rate);
293 }
294 283
295 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 284 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
296 base = of_iomap(np, 0); 285 base = of_iomap(np, 0);
@@ -312,7 +301,6 @@ int __init mx6q_clocks_init(void)
312 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 301 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
313 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 302 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
314 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 303 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
315 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
316 304
317 /* 305 /*
318 * Bit 20 is the reserved and read-only bit, we do this only for: 306 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -360,7 +348,7 @@ int __init mx6q_clocks_init(void)
360 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 348 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
361 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 349 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
362 350
363 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); 351 np = ccm_node;
364 base = of_iomap(np, 0); 352 base = of_iomap(np, 0);
365 WARN_ON(!base); 353 WARN_ON(!base);
366 ccm_base = base; 354 ccm_base = base;
@@ -481,7 +469,14 @@ int __init mx6q_clocks_init(void)
481 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); 469 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
482 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 470 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
483 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 471 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
484 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 472 if (cpu_is_imx6dl())
473 /*
474 * The multiplexer and divider of imx6q clock gpu3d_shader get
475 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
476 */
477 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
478 else
479 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
485 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 480 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
486 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 481 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
487 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); 482 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
@@ -499,7 +494,14 @@ int __init mx6q_clocks_init(void)
499 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 494 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
500 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 495 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
501 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 496 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
502 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 497 if (cpu_is_imx6dl())
498 /*
499 * The multiplexer and divider of the imx6q clock gpu2d get
500 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
501 */
502 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
503 else
504 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
503 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); 505 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
504 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 506 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
505 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 507 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
@@ -528,6 +530,7 @@ int __init mx6q_clocks_init(void)
528 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 530 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
529 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 531 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
530 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 532 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
533 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
531 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 534 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
532 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 535 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
533 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 536 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
@@ -547,6 +550,8 @@ int __init mx6q_clocks_init(void)
547 clk_register_clkdev(clk[ahb], "ahb", NULL); 550 clk_register_clkdev(clk[ahb], "ahb", NULL);
548 clk_register_clkdev(clk[cko1], "cko1", NULL); 551 clk_register_clkdev(clk[cko1], "cko1", NULL);
549 clk_register_clkdev(clk[arm], NULL, "cpu0"); 552 clk_register_clkdev(clk[arm], NULL, "cpu0");
553 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
554 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
550 555
551 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { 556 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
552 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); 557 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
@@ -576,6 +581,5 @@ int __init mx6q_clocks_init(void)
576 WARN_ON(!base); 581 WARN_ON(!base);
577 irq = irq_of_parse_and_map(np, 0); 582 irq = irq_of_parse_and_map(np, 0);
578 mxc_timer_init(base, irq); 583 mxc_timer_init(base, irq);
579
580 return 0;
581} 584}
585CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 000000000000..a307ac22dffe
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/err.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <dt-bindings/clock/imx6sl-clock.h>
17
18#include "clk.h"
19#include "common.h"
20
21static const char const *step_sels[] = { "osc", "pll2_pfd2", };
22static const char const *pll1_sw_sels[] = { "pll1_sys", "step", };
23static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
24static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", };
25static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
26static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
27static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
28static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
33static const char const *perclk_sels[] = { "ipg", "osc", };
34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
39static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
40static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
41static const char const *uart_sels[] = { "pll3_80m", "osc", };
42
43static struct clk_div_table clk_enet_ref_table[] = {
44 { .val = 0, .div = 20, },
45 { .val = 1, .div = 10, },
46 { .val = 2, .div = 5, },
47 { .val = 3, .div = 4, },
48 { }
49};
50
51static struct clk_div_table post_div_table[] = {
52 { .val = 2, .div = 1, },
53 { .val = 1, .div = 2, },
54 { .val = 0, .div = 4, },
55 { }
56};
57
58static struct clk_div_table video_div_table[] = {
59 { .val = 0, .div = 1, },
60 { .val = 1, .div = 2, },
61 { .val = 2, .div = 1, },
62 { .val = 3, .div = 4, },
63 { }
64};
65
66static struct clk *clks[IMX6SL_CLK_CLK_END];
67static struct clk_onecell_data clk_data;
68
69static void __init imx6sl_clocks_init(struct device_node *ccm_node)
70{
71 struct device_node *np;
72 void __iomem *base;
73 int irq;
74 int i;
75
76 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
77 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
78 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
79
80 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
81 base = of_iomap(np, 0);
82 WARN_ON(!base);
83
84 /* type name parent base div_mask */
85 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
86 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
87 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
88 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
89 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
90 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
91 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
92
93 /*
94 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
95 * bit 20. They are used by phy driver to keep the refcount of
96 * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
97 * turned on during boot, and software will not need to control it
98 * anymore after that.
99 */
100 clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
101 clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
102 clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
103 clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
104
105 /* dev name parent_name flags reg shift width div: flags, div_table lock */
106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
108 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
109 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
110
111 /* name parent_name reg idx */
112 clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
113 clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
114 clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
115 clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
116 clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
117 clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
118 clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
119
120 /* name parent_name mult div */
121 clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
122 clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
123 clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
124 clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
125
126 np = ccm_node;
127 base = of_iomap(np, 0);
128 WARN_ON(!base);
129
130 /* name reg shift width parent_names num_parents */
131 clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
132 clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
133 clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
134 clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
135 clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
136 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
137 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
138 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
139 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
140 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
141 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
142 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
143 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
144 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
145 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
146 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
147 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
148 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
149 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
150 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
151 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
152 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
153 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
154 clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
155 clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
156 clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
157 clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
158 clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
159 clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
160
161 /* name reg shift width busy: reg, shift parent_names num_parents */
162 clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
163 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
164
165 /* name parent_name reg shift width */
166 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
167 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
168 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
169 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
170 clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
171 clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
172 clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
173 clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
174 clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
175 clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
176 clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
177 clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
178 clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
179 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
180 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
181 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
182 clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
183 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
184 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
185 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
186 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
187 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
188 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
189 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3);
190 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
191 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
192 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
193 clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
194 clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
195 clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
196 clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
197 clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
198 clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
199
200 /* name parent_name reg shift width busy: reg, shift */
201 clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
202 clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
203 clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
204
205 /* name parent_name reg shift */
206 clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
207 clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
208 clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
209 clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
210 clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
211 clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
212 clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
213 clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20);
214 clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
215 clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
216 clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
217 clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
218 clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
219 clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
220 clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0);
221 clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
222 clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
223 clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
224 clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
225 clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
226 clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
227 clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
228 clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
229 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
230 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
231 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
232 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
233 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
234 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
235 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
236 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
237 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
238 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
239 clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
240 clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
241 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
242 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
243
244 for (i = 0; i < ARRAY_SIZE(clks); i++)
245 if (IS_ERR(clks[i]))
246 pr_err("i.MX6SL clk %d: register failed with %ld\n",
247 i, PTR_ERR(clks[i]));
248
249 clk_data.clks = clks;
250 clk_data.clk_num = ARRAY_SIZE(clks);
251 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
252
253 clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
254 clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
255
256 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
257 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
258 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
259 }
260
261 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
262 base = of_iomap(np, 0);
263 WARN_ON(!base);
264 irq = irq_of_parse_and_map(np, 0);
265 mxc_timer_init(base, irq);
266}
267CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3df9a7a..a9fad5f8d340 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
296 .recalc_rate = clk_pllv3_enet_recalc_rate, 296 .recalc_rate = clk_pllv3_enet_recalc_rate,
297}; 297};
298 298
299static const struct clk_ops clk_pllv3_mlb_ops = {
300 .prepare = clk_pllv3_prepare,
301 .unprepare = clk_pllv3_unprepare,
302 .enable = clk_pllv3_enable,
303 .disable = clk_pllv3_disable,
304};
305
306struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 299struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
307 const char *parent_name, void __iomem *base, 300 const char *parent_name, void __iomem *base,
308 u32 div_mask) 301 u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
330 case IMX_PLLV3_ENET: 323 case IMX_PLLV3_ENET:
331 ops = &clk_pllv3_enet_ops; 324 ops = &clk_pllv3_enet_ops;
332 break; 325 break;
333 case IMX_PLLV3_MLB:
334 ops = &clk_pllv3_mlb_ops;
335 break;
336 default: 326 default:
337 ops = &clk_pllv3_ops; 327 ops = &clk_pllv3_ops;
338 } 328 }
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 000000000000..d617c0b7c809
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,319 @@
1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/of_address.h>
12#include <linux/clk.h>
13#include <dt-bindings/clock/vf610-clock.h>
14
15#include "clk.h"
16
17#define CCM_CCR (ccm_base + 0x00)
18#define CCM_CSR (ccm_base + 0x04)
19#define CCM_CCSR (ccm_base + 0x08)
20#define CCM_CACRR (ccm_base + 0x0c)
21#define CCM_CSCMR1 (ccm_base + 0x10)
22#define CCM_CSCDR1 (ccm_base + 0x14)
23#define CCM_CSCDR2 (ccm_base + 0x18)
24#define CCM_CSCDR3 (ccm_base + 0x1c)
25#define CCM_CSCMR2 (ccm_base + 0x20)
26#define CCM_CSCDR4 (ccm_base + 0x24)
27#define CCM_CLPCR (ccm_base + 0x2c)
28#define CCM_CISR (ccm_base + 0x30)
29#define CCM_CIMR (ccm_base + 0x34)
30#define CCM_CGPR (ccm_base + 0x3c)
31#define CCM_CCGR0 (ccm_base + 0x40)
32#define CCM_CCGR1 (ccm_base + 0x44)
33#define CCM_CCGR2 (ccm_base + 0x48)
34#define CCM_CCGR3 (ccm_base + 0x4c)
35#define CCM_CCGR4 (ccm_base + 0x50)
36#define CCM_CCGR5 (ccm_base + 0x54)
37#define CCM_CCGR6 (ccm_base + 0x58)
38#define CCM_CCGR7 (ccm_base + 0x5c)
39#define CCM_CCGR8 (ccm_base + 0x60)
40#define CCM_CCGR9 (ccm_base + 0x64)
41#define CCM_CCGR10 (ccm_base + 0x68)
42#define CCM_CCGR11 (ccm_base + 0x6c)
43#define CCM_CMEOR0 (ccm_base + 0x70)
44#define CCM_CMEOR1 (ccm_base + 0x74)
45#define CCM_CMEOR2 (ccm_base + 0x78)
46#define CCM_CMEOR3 (ccm_base + 0x7c)
47#define CCM_CMEOR4 (ccm_base + 0x80)
48#define CCM_CMEOR5 (ccm_base + 0x84)
49#define CCM_CPPDSR (ccm_base + 0x88)
50#define CCM_CCOWR (ccm_base + 0x8c)
51#define CCM_CCPGR0 (ccm_base + 0x90)
52#define CCM_CCPGR1 (ccm_base + 0x94)
53#define CCM_CCPGR2 (ccm_base + 0x98)
54#define CCM_CCPGR3 (ccm_base + 0x9c)
55
56#define CCM_CCGRx_CGn(n) ((n) * 2)
57
58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61
62static void __iomem *anatop_base;
63static void __iomem *ccm_base;
64
65/* sources for multiplexer clocks, this is used multiple times */
66static const char const *fast_sels[] = { "firc", "fxosc", };
67static const char const *slow_sels[] = { "sirc_32k", "sxosc", };
68static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
69static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
70static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
71static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
72static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
73static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
74static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
75static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
76static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
77static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
78static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
79static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
80static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
81static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
82/* FTM counter clock source, not module clock */
83static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
84static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
85
86static struct clk_div_table pll4_main_div_table[] = {
87 { .val = 0, .div = 1 },
88 { .val = 1, .div = 2 },
89 { .val = 2, .div = 6 },
90 { .val = 3, .div = 8 },
91 { .val = 4, .div = 10 },
92 { .val = 5, .div = 12 },
93 { .val = 6, .div = 14 },
94 { .val = 7, .div = 16 },
95 { }
96};
97
98static struct clk *clk[VF610_CLK_END];
99static struct clk_onecell_data clk_data;
100
101static void __init vf610_clocks_init(struct device_node *ccm_node)
102{
103 struct device_node *np;
104
105 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
106 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
107 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
108 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
109
110 clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
111 clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
112 clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
113 clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
114
115 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
116
117 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
118 anatop_base = of_iomap(np, 0);
119 BUG_ON(!anatop_base);
120
121 np = ccm_node;
122 ccm_base = of_iomap(np, 0);
123 BUG_ON(!ccm_base);
124
125 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
126 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
127
128 clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
129 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
130 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
131 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
132 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
133
134 clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
135 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
136 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
137 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
138 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
139
140 clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
141 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
142 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
143 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
144 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
145
146 clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
147 /* Enet pll: fixed 50Mhz */
148 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
149 /* pll6: default 960Mhz */
150 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
151 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
152 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
153 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
154 clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
155 clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
156 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
157 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
158
159 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
160 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
161 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
162
163 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
164 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
165
166 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
167 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
168 clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
169 clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
170 clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
171 clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
172
173 clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
174 clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
175 clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
176 clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
177 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
178 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
179
180 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
181 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
182 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
183 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
184 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
185 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
186
187 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
188
189 clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
190 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
191 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
192 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
193
194 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
195 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
196
197 clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
198 clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
199 clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
200 clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
201
202 clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
203
204 clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
205 clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
206 clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
207 clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
208
209 clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
210 clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
211 clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
212 clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
213
214 /*
215 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
216 * selectable clock sources, both use a common enable bit
217 * in CCM_CSCDR1, selecting "dummy" clock as parent of
218 * "ftm0_ext_fix" make it serve only for enable/disable.
219 */
220 clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
221 clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
222 clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
223 clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
224 clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
225 clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
226 clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
227 clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
228 clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
229 clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
230 clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
231 clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
232
233 /* ftm(n)_clk are FTM module operation clock */
234 clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
235 clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
236 clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
237 clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
238
239 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
240 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
241 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
242 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
243 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
244 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
245 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
246 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
247
248 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
249 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
250 clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
251 clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
252
253 clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
254 clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
255 clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
256 clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
257
258 clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
259 clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
260 clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
261 clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
262
263 clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
264 clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
265 clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
266 clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
267
268 clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
269 clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
270 clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
271 clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
272
273 clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
274 clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
275 clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
276 clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
277 clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
278
279 clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
280 clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
281 clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
282
283 clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
284 clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
285 clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
286 clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
287 clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
288
289 clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
290 clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
291 clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
292 clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
293
294 clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
295
296 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
297 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
298
299 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
300 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
301 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
302 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
303
304 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
305 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
306 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
307 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
308
309 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
310 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
311 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
312 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
313
314 /* Add the clocks to provider list */
315 clk_data.clks = clk;
316 clk_data.clk_num = ARRAY_SIZE(clk);
317 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
318}
319CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 37e884ed1cd4..55bc80a00666 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,4 +1,39 @@
1#include <linux/clk.h>
2#include <linux/err.h>
3#include <linux/of.h>
4#include <linux/slab.h>
1#include <linux/spinlock.h> 5#include <linux/spinlock.h>
2#include "clk.h" 6#include "clk.h"
3 7
4DEFINE_SPINLOCK(imx_ccm_lock); 8DEFINE_SPINLOCK(imx_ccm_lock);
9
10static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
11{
12 struct of_phandle_args phandle;
13 struct clk *clk = ERR_PTR(-ENODEV);
14 char *path;
15
16 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
17 if (!path)
18 return ERR_PTR(-ENOMEM);
19
20 phandle.np = of_find_node_by_path(path);
21 kfree(path);
22
23 if (phandle.np) {
24 clk = of_clk_get_from_provider(&phandle);
25 of_node_put(phandle.np);
26 }
27 return clk;
28}
29
30struct clk * __init imx_obtain_fixed_clock(
31 const char *name, unsigned long rate)
32{
33 struct clk *clk;
34
35 clk = imx_obtain_fixed_clock_from_dt(name);
36 if (IS_ERR(clk))
37 clk = imx_clk_fixed(name, rate);
38 return clk;
39}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c66dff..0e4e8bb261b9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
18 IMX_PLLV3_USB, 18 IMX_PLLV3_USB,
19 IMX_PLLV3_AV, 19 IMX_PLLV3_AV,
20 IMX_PLLV3_ENET, 20 IMX_PLLV3_ENET,
21 IMX_PLLV3_MLB,
22}; 21};
23 22
24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 23struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
29 void __iomem *reg, u8 bit_idx, 28 void __iomem *reg, u8 bit_idx,
30 u8 clk_gate_flags, spinlock_t *lock); 29 u8 clk_gate_flags, spinlock_t *lock);
31 30
31struct clk * imx_obtain_fixed_clock(
32 const char *name, unsigned long rate);
33
32static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 34static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
33 void __iomem *reg, u8 shift) 35 void __iomem *reg, u8 shift)
34{ 36{
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f99cee..ee78847abf47 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,12 +68,12 @@ extern int mx27_clocks_init_dt(void);
68extern int mx31_clocks_init_dt(void); 68extern int mx31_clocks_init_dt(void);
69extern int mx51_clocks_init_dt(void); 69extern int mx51_clocks_init_dt(void);
70extern int mx53_clocks_init_dt(void); 70extern int mx53_clocks_init_dt(void);
71extern int mx6q_clocks_init(void);
72extern struct platform_device *mxc_register_gpio(char *name, int id, 71extern struct platform_device *mxc_register_gpio(char *name, int id,
73 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 72 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
74extern void mxc_set_cpu_type(unsigned int type); 73extern void mxc_set_cpu_type(unsigned int type);
75extern void mxc_restart(char, const char *); 74extern void mxc_restart(char, const char *);
76extern void mxc_arch_reset_init(void __iomem *); 75extern void mxc_arch_reset_init(void __iomem *);
76extern void mxc_arch_reset_init_dt(void);
77extern int mx53_revision(void); 77extern int mx53_revision(void);
78extern int imx6q_revision(void); 78extern int imx6q_revision(void);
79extern int mx53_display_revision(void); 79extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f7b591..a3b0b04b45c9 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
20#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
21#define __ASM_ARCH_MXC_HARDWARE_H__ 21#define __ASM_ARCH_MXC_HARDWARE_H__
22 22
23#include <asm/io.h>
23#include <asm/sizes.h> 24#include <asm/sizes.h>
24 25
25#define addr_in_module(addr, mod) \ 26#define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 82348391582a..3e1ec5ffe630 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -19,6 +19,8 @@
19 19
20static void __init imx25_dt_init(void) 20static void __init imx25_dt_init(void)
21{ 21{
22 mxc_arch_reset_init_dt();
23
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23} 25}
24 26
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0a77ff..4e235ecb4021 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,6 +22,8 @@ static void __init imx27_dt_init(void)
22{ 22{
23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
24 24
25 mxc_arch_reset_init_dt();
26
25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 27 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
26 28
27 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611e29ab..818a1cc2fe45 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -20,6 +20,8 @@
20 20
21static void __init imx31_dt_init(void) 21static void __init imx31_dt_init(void)
22{ 22{
23 mxc_arch_reset_init_dt();
24
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
24} 26}
25 27
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc322111..53e43e579dd7 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -23,6 +23,8 @@ static void __init imx51_dt_init(void)
23{ 23{
24 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 24 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
25 25
26 mxc_arch_reset_init_dt();
27
26 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 28 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
27 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
28} 30}
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52dc46b..0a920d184867 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/platform_data/asoc-imx-ssi.h>
21 22
22#include "irq-common.h" 23#include "irq-common.h"
23 24
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c616feed..74e7b94c22e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,6 +21,7 @@
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22 22
23#include "common.h" 23#include "common.h"
24#include "hardware.h"
24#include "mx53.h" 25#include "mx53.h"
25 26
26static void __init imx53_qsb_init(void) 27static void __init imx53_qsb_init(void)
@@ -38,6 +39,8 @@ static void __init imx53_qsb_init(void)
38 39
39static void __init imx53_dt_init(void) 40static void __init imx53_dt_init(void)
40{ 41{
42 mxc_arch_reset_init_dt();
43
41 if (of_machine_is_compatible("fsl,imx53-qsb")) 44 if (of_machine_is_compatible("fsl,imx53-qsb"))
42 imx53_qsb_init(); 45 imx53_qsb_init();
43 46
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd81379a..f5965220a4d8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clk-provider.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clocksource.h> 16#include <linux/clocksource.h>
16#include <linux/cpu.h> 17#include <linux/cpu.h>
@@ -145,6 +146,45 @@ static void __init imx6q_sabrelite_init(void)
145 imx6q_sabrelite_cko1_setup(); 146 imx6q_sabrelite_cko1_setup();
146} 147}
147 148
149static void __init imx6q_sabresd_cko1_setup(void)
150{
151 struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
152 unsigned long rate;
153
154 cko1_sel = clk_get_sys(NULL, "cko1_sel");
155 pll4 = clk_get_sys(NULL, "pll4_audio");
156 pll4_post = clk_get_sys(NULL, "pll4_post_div");
157 cko1 = clk_get_sys(NULL, "cko1");
158 if (IS_ERR(cko1_sel) || IS_ERR(pll4)
159 || IS_ERR(pll4_post) || IS_ERR(cko1)) {
160 pr_err("cko1 setup failed!\n");
161 goto put_clk;
162 }
163 /*
164 * Setting pll4 at 768MHz (24MHz * 32)
165 * So its child clock can get 24MHz easily
166 */
167 clk_set_rate(pll4, 768000000);
168
169 clk_set_parent(cko1_sel, pll4_post);
170 rate = clk_round_rate(cko1, 24000000);
171 clk_set_rate(cko1, rate);
172put_clk:
173 if (!IS_ERR(cko1_sel))
174 clk_put(cko1_sel);
175 if (!IS_ERR(pll4_post))
176 clk_put(pll4_post);
177 if (!IS_ERR(pll4))
178 clk_put(pll4);
179 if (!IS_ERR(cko1))
180 clk_put(cko1);
181}
182
183static void __init imx6q_sabresd_init(void)
184{
185 imx6q_sabresd_cko1_setup();
186}
187
148static void __init imx6q_1588_init(void) 188static void __init imx6q_1588_init(void)
149{ 189{
150 struct regmap *gpr; 190 struct regmap *gpr;
@@ -165,6 +205,9 @@ static void __init imx6q_init_machine(void)
165{ 205{
166 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 206 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
167 imx6q_sabrelite_init(); 207 imx6q_sabrelite_init();
208 else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
209 of_machine_is_compatible("fsl,imx6dl-sabresd"))
210 imx6q_sabresd_init();
168 211
169 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 212 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
170 213
@@ -253,10 +296,44 @@ static void __init imx6q_map_io(void)
253 imx_scu_map_io(); 296 imx_scu_map_io();
254} 297}
255 298
299#ifdef CONFIG_CACHE_L2X0
300static void __init imx6q_init_l2cache(void)
301{
302 void __iomem *l2x0_base;
303 struct device_node *np;
304 unsigned int val;
305
306 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
307 if (!np)
308 goto out;
309
310 l2x0_base = of_iomap(np, 0);
311 if (!l2x0_base) {
312 of_node_put(np);
313 goto out;
314 }
315
316 /* Configure the L2 PREFETCH and POWER registers */
317 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
318 val |= 0x70800000;
319 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
320 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
321 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
322
323 iounmap(l2x0_base);
324 of_node_put(np);
325
326out:
327 l2x0_of_init(0, ~0UL);
328}
329#else
330static inline void imx6q_init_l2cache(void) {}
331#endif
332
256static void __init imx6q_init_irq(void) 333static void __init imx6q_init_irq(void)
257{ 334{
258 imx6q_init_revision(); 335 imx6q_init_revision();
259 l2x0_of_init(0, ~0UL); 336 imx6q_init_l2cache();
260 imx_src_init(); 337 imx_src_init();
261 imx_gpc_init(); 338 imx_gpc_init();
262 irqchip_init(); 339 irqchip_init();
@@ -264,7 +341,7 @@ static void __init imx6q_init_irq(void)
264 341
265static void __init imx6q_timer_init(void) 342static void __init imx6q_timer_init(void)
266{ 343{
267 mx6q_clocks_init(); 344 of_clk_init(NULL);
268 clocksource_of_init(); 345 clocksource_of_init();
269 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", 346 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
270 imx6q_revision()); 347 imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 000000000000..132db2609507
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/irqchip.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <asm/hardware/cache-l2x0.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17
18#include "common.h"
19
20static void __init imx6sl_init_machine(void)
21{
22 mxc_arch_reset_init_dt();
23
24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
25}
26
27static void __init imx6sl_init_irq(void)
28{
29 l2x0_of_init(0, ~0UL);
30 imx_src_init();
31 imx_gpc_init();
32 irqchip_init();
33}
34
35static void __init imx6sl_timer_init(void)
36{
37 of_clk_init(NULL);
38}
39
40static const char *imx6sl_dt_compat[] __initdata = {
41 "fsl,imx6sl",
42 NULL,
43};
44
45DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
46 .map_io = debug_ll_io_init,
47 .init_irq = imx6sl_init_irq,
48 .init_time = imx6sl_timer_init,
49 .init_machine = imx6sl_init_machine,
50 .dt_compat = imx6sl_dt_compat,
51 .restart = mxc_restart,
52MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb1ffdf..19bb6441a7d4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
398 imx27_add_fsl_usb2_udc(&otg_device_pdata); 398 imx27_add_fsl_usb2_udc(&otg_device_pdata);
399 } 399 }
400 400
401 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 401 usbh2_pdata.otg = imx_otg_ulpi_create(
402 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 402 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
403 403
404 if (usbh2_pdata.otg) 404 if (usbh2_pdata.otg)
405 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 405 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 000000000000..816991deb9b8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/of_platform.h>
11#include <linux/clocksource.h>
12#include <linux/irqchip.h>
13#include <linux/clk-provider.h>
14#include <asm/mach/arch.h>
15#include <asm/hardware/cache-l2x0.h>
16
17#include "common.h"
18
19static void __init vf610_init_machine(void)
20{
21 mxc_arch_reset_init_dt();
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23}
24
25static void __init vf610_init_irq(void)
26{
27 l2x0_of_init(0, ~0UL);
28 irqchip_init();
29}
30
31static void __init vf610_init_time(void)
32{
33 of_clk_init(NULL);
34 clocksource_of_init();
35}
36
37static const char *vf610_dt_compat[] __initdata = {
38 "fsl,vf610",
39 NULL,
40};
41
42DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
43 .init_irq = vf610_init_irq,
44 .init_time = vf610_init_time,
45 .init_machine = vf610_init_machine,
46 .dt_compat = vf610_dt_compat,
47 .restart = mxc_restart,
48MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c52d3eb..e065fedb3ad4 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
39void __init imx1_init_early(void) 39void __init imx1_init_early(void)
40{ 40{
41 mxc_set_cpu_type(MXC_CPU_MX1); 41 mxc_set_cpu_type(MXC_CPU_MX1);
42 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
43 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), 42 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
44 MX1_NUM_GPIO_PORT); 43 MX1_NUM_GPIO_PORT);
45} 44}
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
51 50
52void __init imx1_soc_init(void) 51void __init imx1_soc_init(void)
53{ 52{
53 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
54 mxc_device_init(); 54 mxc_device_init();
55 55
56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, 56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec53..2e91ab2ca378 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
66void __init imx21_init_early(void) 66void __init imx21_init_early(void)
67{ 67{
68 mxc_set_cpu_type(MXC_CPU_MX21); 68 mxc_set_cpu_type(MXC_CPU_MX21);
69 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
70 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), 69 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
71 MX21_NUM_GPIO_PORT); 70 MX21_NUM_GPIO_PORT);
72} 71}
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
82 81
83void __init imx21_soc_init(void) 82void __init imx21_soc_init(void)
84{ 83{
84 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
85 mxc_device_init(); 85 mxc_device_init();
86 86
87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7af..e065c117f5a6 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
54{ 54{
55 mxc_set_cpu_type(MXC_CPU_MX25); 55 mxc_set_cpu_type(MXC_CPU_MX25);
56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
57 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
58} 57}
59 58
60void __init mx25_init_irq(void) 59void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
89 88
90void __init imx25_soc_init(void) 89void __init imx25_soc_init(void)
91{ 90{
91 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
92 mxc_device_init(); 92 mxc_device_init();
93 93
94 /* i.mx25 has the i.mx35 type gpio */ 94 /* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5f..7d82a5a5b16b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
66void __init imx27_init_early(void) 66void __init imx27_init_early(void)
67{ 67{
68 mxc_set_cpu_type(MXC_CPU_MX27); 68 mxc_set_cpu_type(MXC_CPU_MX27);
69 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
70 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), 69 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
71 MX27_NUM_GPIO_PORT); 70 MX27_NUM_GPIO_PORT);
72} 71}
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
82 81
83void __init imx27_soc_init(void) 82void __init imx27_soc_init(void)
84{ 83{
84 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
85 mxc_device_init(); 85 mxc_device_init();
86 86
87 /* i.mx27 has the i.mx21 type gpio */ 87 /* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a682174..8f0f60697f55 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
138void __init imx31_init_early(void) 138void __init imx31_init_early(void)
139{ 139{
140 mxc_set_cpu_type(MXC_CPU_MX31); 140 mxc_set_cpu_type(MXC_CPU_MX31);
141 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
142 arch_ioremap_caller = imx3_ioremap_caller; 141 arch_ioremap_caller = imx3_ioremap_caller;
143 arm_pm_idle = imx3_idle; 142 arm_pm_idle = imx3_idle;
144 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 143 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
174 173
175 imx3_init_l2x0(); 174 imx3_init_l2x0();
176 175
176 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
177 mxc_device_init(); 177 mxc_device_init();
178 178
179 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 179 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
216{ 216{
217 mxc_set_cpu_type(MXC_CPU_MX35); 217 mxc_set_cpu_type(MXC_CPU_MX35);
218 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 218 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
219 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
220 arm_pm_idle = imx3_idle; 219 arm_pm_idle = imx3_idle;
221 arch_ioremap_caller = imx3_ioremap_caller; 220 arch_ioremap_caller = imx3_ioremap_caller;
222 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); 221 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
272 271
273 imx3_init_l2x0(); 272 imx3_init_l2x0();
274 273
274 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
275 mxc_device_init(); 275 mxc_device_init();
276 276
277 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 277 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70e5081..cf193d87274a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
83 imx51_ipu_mipi_setup(); 83 imx51_ipu_mipi_setup();
84 mxc_set_cpu_type(MXC_CPU_MX51); 84 mxc_set_cpu_type(MXC_CPU_MX51);
85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
87 imx_src_init(); 86 imx_src_init();
88} 87}
89 88
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
91{ 90{
92 mxc_set_cpu_type(MXC_CPU_MX53); 91 mxc_set_cpu_type(MXC_CPU_MX53);
93 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 92 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
94 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
95 imx_src_init(); 93 imx_src_init();
96} 94}
97 95
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
129 127
130void __init imx51_soc_init(void) 128void __init imx51_soc_init(void)
131{ 129{
130 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
132 mxc_device_init(); 131 mxc_device_init();
133 132
134 /* i.mx51 has the i.mx35 type gpio */ 133 /* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d73bf85..7cdc79a9657c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
24 26
25#include <asm/system_misc.h> 27#include <asm/system_misc.h>
26#include <asm/proc-fns.h> 28#include <asm/proc-fns.h>
@@ -30,6 +32,7 @@
30#include "hardware.h" 32#include "hardware.h"
31 33
32static void __iomem *wdog_base; 34static void __iomem *wdog_base;
35static struct clk *wdog_clk;
33 36
34/* 37/*
35 * Reset the system. It is called by machine_restart(). 38 * Reset the system. It is called by machine_restart().
@@ -38,16 +41,13 @@ void mxc_restart(char mode, const char *cmd)
38{ 41{
39 unsigned int wcr_enable; 42 unsigned int wcr_enable;
40 43
41 if (cpu_is_mx1()) { 44 if (wdog_clk)
42 wcr_enable = (1 << 0); 45 clk_enable(wdog_clk);
43 } else {
44 struct clk *clk;
45 46
46 clk = clk_get_sys("imx2-wdt.0", NULL); 47 if (cpu_is_mx1())
47 if (!IS_ERR(clk)) 48 wcr_enable = (1 << 0);
48 clk_prepare_enable(clk); 49 else
49 wcr_enable = (1 << 2); 50 wcr_enable = (1 << 2);
50 }
51 51
52 /* Assert SRS signal */ 52 /* Assert SRS signal */
53 __raw_writew(wcr_enable, wdog_base); 53 __raw_writew(wcr_enable, wdog_base);
@@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd)
55 /* wait for reset to assert... */ 55 /* wait for reset to assert... */
56 mdelay(500); 56 mdelay(500);
57 57
58 printk(KERN_ERR "Watchdog reset failed to assert reset\n"); 58 pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
59 59
60 /* delay to allow the serial port to show the message */ 60 /* delay to allow the serial port to show the message */
61 mdelay(50); 61 mdelay(50);
@@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd)
64 soft_restart(0); 64 soft_restart(0);
65} 65}
66 66
67void mxc_arch_reset_init(void __iomem *base) 67void __init mxc_arch_reset_init(void __iomem *base)
68{ 68{
69 wdog_base = base; 69 wdog_base = base;
70
71 wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
72 if (IS_ERR(wdog_clk)) {
73 pr_warn("%s: failed to get wdog clock\n", __func__);
74 wdog_clk = NULL;
75 return;
76 }
77
78 clk_prepare(wdog_clk);
79}
80
81void __init mxc_arch_reset_init_dt(void)
82{
83 struct device_node *np;
84
85 np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
86 wdog_base = of_iomap(np, 0);
87 WARN_ON(!wdog_base);
88
89 wdog_clk = of_clk_get(np, 0);
90 if (IS_ERR(wdog_clk)) {
91 pr_warn("%s: failed to get wdog clock\n", __func__);
92 wdog_clk = NULL;
93 return;
94 }
95
96 clk_prepare(wdog_clk);
70} 97}
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10c..000000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
26
27#include "ulpi.h"
28
29/* ULPIVIEW register bits */
30#define ULPIVW_WU (1 << 31) /* Wakeup */
31#define ULPIVW_RUN (1 << 30) /* read/write run */
32#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
33#define ULPIVW_SS (1 << 27) /* SyncState */
34#define ULPIVW_PORT_MASK 0x07 /* Port field */
35#define ULPIVW_PORT_SHIFT 24
36#define ULPIVW_ADDR_MASK 0xff /* data address field */
37#define ULPIVW_ADDR_SHIFT 16
38#define ULPIVW_RDATA_MASK 0xff /* read data field */
39#define ULPIVW_RDATA_SHIFT 8
40#define ULPIVW_WDATA_MASK 0xff /* write data field */
41#define ULPIVW_WDATA_SHIFT 0
42
43static int ulpi_poll(void __iomem *view, u32 bit)
44{
45 int timeout = 10000;
46
47 while (timeout--) {
48 u32 data = __raw_readl(view);
49
50 if (!(data & bit))
51 return 0;
52
53 cpu_relax();
54 };
55
56 printk(KERN_WARNING "timeout polling for ULPI device\n");
57
58 return -ETIMEDOUT;
59}
60
61static int ulpi_read(struct usb_phy *otg, u32 reg)
62{
63 int ret;
64 void __iomem *view = otg->io_priv;
65
66 /* make sure interface is running */
67 if (!(__raw_readl(view) & ULPIVW_SS)) {
68 __raw_writel(ULPIVW_WU, view);
69
70 /* wait for wakeup */
71 ret = ulpi_poll(view, ULPIVW_WU);
72 if (ret)
73 return ret;
74 }
75
76 /* read the register */
77 __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
78
79 /* wait for completion */
80 ret = ulpi_poll(view, ULPIVW_RUN);
81 if (ret)
82 return ret;
83
84 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
85}
86
87static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
88{
89 int ret;
90 void __iomem *view = otg->io_priv;
91
92 /* make sure the interface is running */
93 if (!(__raw_readl(view) & ULPIVW_SS)) {
94 __raw_writel(ULPIVW_WU, view);
95 /* wait for wakeup */
96 ret = ulpi_poll(view, ULPIVW_WU);
97 if (ret)
98 return ret;
99 }
100
101 __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
102 (reg << ULPIVW_ADDR_SHIFT) |
103 ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
104
105 /* wait for completion */
106 return ulpi_poll(view, ULPIVW_RUN);
107}
108
109struct usb_phy_io_ops mxc_ulpi_access_ops = {
110 .read = ulpi_read,
111 .write = ulpi_write,
112};
113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
114
115struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..23f5c0349e80 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
1#ifndef __MACH_ULPI_H 1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H 2#define __MACH_ULPI_H
3 3
4#ifdef CONFIG_USB_ULPI 4#include <linux/usb/ulpi.h>
5struct usb_phy *imx_otg_ulpi_create(unsigned int flags); 5
6#ifdef CONFIG_USB_ULPI_VIEWPORT
7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{
9 return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
10}
6#else 11#else
7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) 12static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{ 13{
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
10} 15}
11#endif 16#endif
12 17
13extern struct usb_phy_io_ops mxc_ulpi_access_ops;
14
15#endif /* __MACH_ULPI_H */ 18#endif /* __MACH_ULPI_H */
16 19
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 000000000000..7fcdf90879f2
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,148 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
11#define __DT_BINDINGS_CLOCK_IMX6SL_H
12
13#define IMX6SL_CLK_DUMMY 0
14#define IMX6SL_CLK_CKIL 1
15#define IMX6SL_CLK_OSC 2
16#define IMX6SL_CLK_PLL1_SYS 3
17#define IMX6SL_CLK_PLL2_BUS 4
18#define IMX6SL_CLK_PLL3_USB_OTG 5
19#define IMX6SL_CLK_PLL4_AUDIO 6
20#define IMX6SL_CLK_PLL5_VIDEO 7
21#define IMX6SL_CLK_PLL6_ENET 8
22#define IMX6SL_CLK_PLL7_USB_HOST 9
23#define IMX6SL_CLK_USBPHY1 10
24#define IMX6SL_CLK_USBPHY2 11
25#define IMX6SL_CLK_USBPHY1_GATE 12
26#define IMX6SL_CLK_USBPHY2_GATE 13
27#define IMX6SL_CLK_PLL4_POST_DIV 14
28#define IMX6SL_CLK_PLL5_POST_DIV 15
29#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
30#define IMX6SL_CLK_ENET_REF 17
31#define IMX6SL_CLK_PLL2_PFD0 18
32#define IMX6SL_CLK_PLL2_PFD1 19
33#define IMX6SL_CLK_PLL2_PFD2 20
34#define IMX6SL_CLK_PLL3_PFD0 21
35#define IMX6SL_CLK_PLL3_PFD1 22
36#define IMX6SL_CLK_PLL3_PFD2 23
37#define IMX6SL_CLK_PLL3_PFD3 24
38#define IMX6SL_CLK_PLL2_198M 25
39#define IMX6SL_CLK_PLL3_120M 26
40#define IMX6SL_CLK_PLL3_80M 27
41#define IMX6SL_CLK_PLL3_60M 28
42#define IMX6SL_CLK_STEP 29
43#define IMX6SL_CLK_PLL1_SW 30
44#define IMX6SL_CLK_OCRAM_ALT_SEL 31
45#define IMX6SL_CLK_OCRAM_SEL 32
46#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
47#define IMX6SL_CLK_PRE_PERIPH_SEL 34
48#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
49#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
50#define IMX6SL_CLK_CSI_SEL 37
51#define IMX6SL_CLK_LCDIF_AXI_SEL 38
52#define IMX6SL_CLK_USDHC1_SEL 39
53#define IMX6SL_CLK_USDHC2_SEL 40
54#define IMX6SL_CLK_USDHC3_SEL 41
55#define IMX6SL_CLK_USDHC4_SEL 42
56#define IMX6SL_CLK_SSI1_SEL 43
57#define IMX6SL_CLK_SSI2_SEL 44
58#define IMX6SL_CLK_SSI3_SEL 45
59#define IMX6SL_CLK_PERCLK_SEL 46
60#define IMX6SL_CLK_PXP_AXI_SEL 47
61#define IMX6SL_CLK_EPDC_AXI_SEL 48
62#define IMX6SL_CLK_GPU2D_OVG_SEL 49
63#define IMX6SL_CLK_GPU2D_SEL 50
64#define IMX6SL_CLK_LCDIF_PIX_SEL 51
65#define IMX6SL_CLK_EPDC_PIX_SEL 52
66#define IMX6SL_CLK_SPDIF0_SEL 53
67#define IMX6SL_CLK_SPDIF1_SEL 54
68#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
69#define IMX6SL_CLK_ECSPI_SEL 56
70#define IMX6SL_CLK_UART_SEL 57
71#define IMX6SL_CLK_PERIPH 58
72#define IMX6SL_CLK_PERIPH2 59
73#define IMX6SL_CLK_OCRAM_PODF 60
74#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
75#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
76#define IMX6SL_CLK_IPG 63
77#define IMX6SL_CLK_CSI_PODF 64
78#define IMX6SL_CLK_LCDIF_AXI_PODF 65
79#define IMX6SL_CLK_USDHC1_PODF 66
80#define IMX6SL_CLK_USDHC2_PODF 67
81#define IMX6SL_CLK_USDHC3_PODF 68
82#define IMX6SL_CLK_USDHC4_PODF 69
83#define IMX6SL_CLK_SSI1_PRED 70
84#define IMX6SL_CLK_SSI1_PODF 71
85#define IMX6SL_CLK_SSI2_PRED 72
86#define IMX6SL_CLK_SSI2_PODF 73
87#define IMX6SL_CLK_SSI3_PRED 74
88#define IMX6SL_CLK_SSI3_PODF 75
89#define IMX6SL_CLK_PERCLK 76
90#define IMX6SL_CLK_PXP_AXI_PODF 77
91#define IMX6SL_CLK_EPDC_AXI_PODF 78
92#define IMX6SL_CLK_GPU2D_OVG_PODF 79
93#define IMX6SL_CLK_GPU2D_PODF 80
94#define IMX6SL_CLK_LCDIF_PIX_PRED 81
95#define IMX6SL_CLK_EPDC_PIX_PRED 82
96#define IMX6SL_CLK_LCDIF_PIX_PODF 83
97#define IMX6SL_CLK_EPDC_PIX_PODF 84
98#define IMX6SL_CLK_SPDIF0_PRED 85
99#define IMX6SL_CLK_SPDIF0_PODF 86
100#define IMX6SL_CLK_SPDIF1_PRED 87
101#define IMX6SL_CLK_SPDIF1_PODF 88
102#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
103#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
104#define IMX6SL_CLK_ECSPI_ROOT 91
105#define IMX6SL_CLK_UART_ROOT 92
106#define IMX6SL_CLK_AHB 93
107#define IMX6SL_CLK_MMDC_ROOT 94
108#define IMX6SL_CLK_ARM 95
109#define IMX6SL_CLK_ECSPI1 96
110#define IMX6SL_CLK_ECSPI2 97
111#define IMX6SL_CLK_ECSPI3 98
112#define IMX6SL_CLK_ECSPI4 99
113#define IMX6SL_CLK_EPIT1 100
114#define IMX6SL_CLK_EPIT2 101
115#define IMX6SL_CLK_EXTERN_AUDIO 102
116#define IMX6SL_CLK_GPT 103
117#define IMX6SL_CLK_GPT_SERIAL 104
118#define IMX6SL_CLK_GPU2D_OVG 105
119#define IMX6SL_CLK_I2C1 106
120#define IMX6SL_CLK_I2C2 107
121#define IMX6SL_CLK_I2C3 108
122#define IMX6SL_CLK_OCOTP 109
123#define IMX6SL_CLK_CSI 110
124#define IMX6SL_CLK_PXP_AXI 111
125#define IMX6SL_CLK_EPDC_AXI 112
126#define IMX6SL_CLK_LCDIF_AXI 113
127#define IMX6SL_CLK_LCDIF_PIX 114
128#define IMX6SL_CLK_EPDC_PIX 115
129#define IMX6SL_CLK_OCRAM 116
130#define IMX6SL_CLK_PWM1 117
131#define IMX6SL_CLK_PWM2 118
132#define IMX6SL_CLK_PWM3 119
133#define IMX6SL_CLK_PWM4 120
134#define IMX6SL_CLK_SDMA 121
135#define IMX6SL_CLK_SPDIF 122
136#define IMX6SL_CLK_SSI1 123
137#define IMX6SL_CLK_SSI2 124
138#define IMX6SL_CLK_SSI3 125
139#define IMX6SL_CLK_UART 126
140#define IMX6SL_CLK_UART_SERIAL 127
141#define IMX6SL_CLK_USBOH3 128
142#define IMX6SL_CLK_USDHC1 129
143#define IMX6SL_CLK_USDHC2 130
144#define IMX6SL_CLK_USDHC3 131
145#define IMX6SL_CLK_USDHC4 132
146#define IMX6SL_CLK_CLK_END 133
147
148#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 000000000000..15e997fa78f2
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_VF610_H
11#define __DT_BINDINGS_CLOCK_VF610_H
12
13#define VF610_CLK_DUMMY 0
14#define VF610_CLK_SIRC_128K 1
15#define VF610_CLK_SIRC_32K 2
16#define VF610_CLK_FIRC 3
17#define VF610_CLK_SXOSC 4
18#define VF610_CLK_FXOSC 5
19#define VF610_CLK_FXOSC_HALF 6
20#define VF610_CLK_SLOW_CLK_SEL 7
21#define VF610_CLK_FASK_CLK_SEL 8
22#define VF610_CLK_AUDIO_EXT 9
23#define VF610_CLK_ENET_EXT 10
24#define VF610_CLK_PLL1_MAIN 11
25#define VF610_CLK_PLL1_PFD1 12
26#define VF610_CLK_PLL1_PFD2 13
27#define VF610_CLK_PLL1_PFD3 14
28#define VF610_CLK_PLL1_PFD4 15
29#define VF610_CLK_PLL2_MAIN 16
30#define VF610_CLK_PLL2_PFD1 17
31#define VF610_CLK_PLL2_PFD2 18
32#define VF610_CLK_PLL2_PFD3 19
33#define VF610_CLK_PLL2_PFD4 20
34#define VF610_CLK_PLL3_MAIN 21
35#define VF610_CLK_PLL3_PFD1 22
36#define VF610_CLK_PLL3_PFD2 23
37#define VF610_CLK_PLL3_PFD3 24
38#define VF610_CLK_PLL3_PFD4 25
39#define VF610_CLK_PLL4_MAIN 26
40#define VF610_CLK_PLL5_MAIN 27
41#define VF610_CLK_PLL6_MAIN 28
42#define VF610_CLK_PLL3_MAIN_DIV 29
43#define VF610_CLK_PLL4_MAIN_DIV 30
44#define VF610_CLK_PLL6_MAIN_DIV 31
45#define VF610_CLK_PLL1_PFD_SEL 32
46#define VF610_CLK_PLL2_PFD_SEL 33
47#define VF610_CLK_SYS_SEL 34
48#define VF610_CLK_DDR_SEL 35
49#define VF610_CLK_SYS_BUS 36
50#define VF610_CLK_PLATFORM_BUS 37
51#define VF610_CLK_IPG_BUS 38
52#define VF610_CLK_UART0 39
53#define VF610_CLK_UART1 40
54#define VF610_CLK_UART2 41
55#define VF610_CLK_UART3 42
56#define VF610_CLK_UART4 43
57#define VF610_CLK_UART5 44
58#define VF610_CLK_PIT 45
59#define VF610_CLK_I2C0 46
60#define VF610_CLK_I2C1 47
61#define VF610_CLK_I2C2 48
62#define VF610_CLK_I2C3 49
63#define VF610_CLK_FTM0_EXT_SEL 50
64#define VF610_CLK_FTM0_FIX_SEL 51
65#define VF610_CLK_FTM0_EXT_FIX_EN 52
66#define VF610_CLK_FTM1_EXT_SEL 53
67#define VF610_CLK_FTM1_FIX_SEL 54
68#define VF610_CLK_FTM1_EXT_FIX_EN 55
69#define VF610_CLK_FTM2_EXT_SEL 56
70#define VF610_CLK_FTM2_FIX_SEL 57
71#define VF610_CLK_FTM2_EXT_FIX_EN 58
72#define VF610_CLK_FTM3_EXT_SEL 59
73#define VF610_CLK_FTM3_FIX_SEL 60
74#define VF610_CLK_FTM3_EXT_FIX_EN 61
75#define VF610_CLK_FTM0 62
76#define VF610_CLK_FTM1 63
77#define VF610_CLK_FTM2 64
78#define VF610_CLK_FTM3 65
79#define VF610_CLK_ENET_50M 66
80#define VF610_CLK_ENET_25M 67
81#define VF610_CLK_ENET_SEL 68
82#define VF610_CLK_ENET 69
83#define VF610_CLK_ENET_TS_SEL 70
84#define VF610_CLK_ENET_TS 71
85#define VF610_CLK_DSPI0 72
86#define VF610_CLK_DSPI1 73
87#define VF610_CLK_DSPI2 74
88#define VF610_CLK_DSPI3 75
89#define VF610_CLK_WDT 76
90#define VF610_CLK_ESDHC0_SEL 77
91#define VF610_CLK_ESDHC0_EN 78
92#define VF610_CLK_ESDHC0_DIV 79
93#define VF610_CLK_ESDHC0 80
94#define VF610_CLK_ESDHC1_SEL 81
95#define VF610_CLK_ESDHC1_EN 82
96#define VF610_CLK_ESDHC1_DIV 83
97#define VF610_CLK_ESDHC1 84
98#define VF610_CLK_DCU0_SEL 85
99#define VF610_CLK_DCU0_EN 86
100#define VF610_CLK_DCU0_DIV 87
101#define VF610_CLK_DCU0 88
102#define VF610_CLK_DCU1_SEL 89
103#define VF610_CLK_DCU1_EN 90
104#define VF610_CLK_DCU1_DIV 91
105#define VF610_CLK_DCU1 92
106#define VF610_CLK_ESAI_SEL 93
107#define VF610_CLK_ESAI_EN 94
108#define VF610_CLK_ESAI_DIV 95
109#define VF610_CLK_ESAI 96
110#define VF610_CLK_SAI0_SEL 97
111#define VF610_CLK_SAI0_EN 98
112#define VF610_CLK_SAI0_DIV 99
113#define VF610_CLK_SAI0 100
114#define VF610_CLK_SAI1_SEL 101
115#define VF610_CLK_SAI1_EN 102
116#define VF610_CLK_SAI1_DIV 103
117#define VF610_CLK_SAI1 104
118#define VF610_CLK_SAI2_SEL 105
119#define VF610_CLK_SAI2_EN 106
120#define VF610_CLK_SAI2_DIV 107
121#define VF610_CLK_SAI2 108
122#define VF610_CLK_SAI3_SEL 109
123#define VF610_CLK_SAI3_EN 110
124#define VF610_CLK_SAI3_DIV 111
125#define VF610_CLK_SAI3 112
126#define VF610_CLK_USBC0 113
127#define VF610_CLK_USBC1 114
128#define VF610_CLK_QSPI0_SEL 115
129#define VF610_CLK_QSPI0_EN 116
130#define VF610_CLK_QSPI0_X4_DIV 117
131#define VF610_CLK_QSPI0_X2_DIV 118
132#define VF610_CLK_QSPI0_X1_DIV 119
133#define VF610_CLK_QSPI1_SEL 120
134#define VF610_CLK_QSPI1_EN 121
135#define VF610_CLK_QSPI1_X4_DIV 122
136#define VF610_CLK_QSPI1_X2_DIV 123
137#define VF610_CLK_QSPI1_X1_DIV 124
138#define VF610_CLK_QSPI0 125
139#define VF610_CLK_QSPI1 126
140#define VF610_CLK_NFC_SEL 127
141#define VF610_CLK_NFC_EN 128
142#define VF610_CLK_NFC_PRE_DIV 129
143#define VF610_CLK_NFC_FRAC_DIV 130
144#define VF610_CLK_NFC_INV 131
145#define VF610_CLK_NFC 132
146#define VF610_CLK_VADC_SEL 133
147#define VF610_CLK_VADC_EN 134
148#define VF610_CLK_VADC_DIV 135
149#define VF610_CLK_VADC_DIV_HALF 136
150#define VF610_CLK_VADC 137
151#define VF610_CLK_ADC0 138
152#define VF610_CLK_ADC1 139
153#define VF610_CLK_DAC0 140
154#define VF610_CLK_DAC1 141
155#define VF610_CLK_FLEXCAN0 142
156#define VF610_CLK_FLEXCAN1 143
157#define VF610_CLK_ASRC 144
158#define VF610_CLK_GPU_SEL 145
159#define VF610_CLK_GPU_EN 146
160#define VF610_CLK_GPU2D 147
161#define VF610_CLK_END 148
162
163#endif /* __DT_BINDINGS_CLOCK_VF610_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 12:21:34 -0400