diff options
author | Heiko Stübner <heiko@sntech.de> | 2014-08-20 15:09:24 -0400 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2014-08-27 17:43:01 -0400 |
commit | f23a6179d45e9d144bf2eb2bd82b2f1270f85fcf (patch) | |
tree | 5bb93d909d3d5c2df6deb9054d96e300f7cd4e3b | |
parent | 4721ab855d1a1d3e472ff38d1cae06e23e0520cf (diff) |
ARM: dts: rockchip: add saradc nodes
Add the core device nodes for the SARADC found on both the Cortex-A9 series
(rk3066 and rk3188) as well as the newer rk3288.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 10 | ||||
-rw-r--r-- | arch/arm/boot/dts/rk3xxx.dtsi | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 7342b2453d6f..9eda0973795f 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi | |||
@@ -98,6 +98,16 @@ | |||
98 | status = "disabled"; | 98 | status = "disabled"; |
99 | }; | 99 | }; |
100 | 100 | ||
101 | saradc: saradc@ff100000 { | ||
102 | compatible = "rockchip,saradc"; | ||
103 | reg = <0xff100000 0x100>; | ||
104 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | ||
105 | #io-channel-cells = <1>; | ||
106 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | ||
107 | clock-names = "saradc", "apb_pclk"; | ||
108 | status = "disabled"; | ||
109 | }; | ||
110 | |||
101 | i2c1: i2c@ff140000 { | 111 | i2c1: i2c@ff140000 { |
102 | compatible = "rockchip,rk3288-i2c"; | 112 | compatible = "rockchip,rk3288-i2c"; |
103 | reg = <0xff140000 0x1000>; | 113 | reg = <0xff140000 0x1000>; |
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 8caf85d83901..cce4a07d6e04 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi | |||
@@ -264,4 +264,14 @@ | |||
264 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | 264 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; |
265 | status = "disabled"; | 265 | status = "disabled"; |
266 | }; | 266 | }; |
267 | |||
268 | saradc: saradc@2006c000 { | ||
269 | compatible = "rockchip,saradc"; | ||
270 | reg = <0x2006c000 0x100>; | ||
271 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | ||
272 | #io-channel-cells = <1>; | ||
273 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | ||
274 | clock-names = "saradc", "apb_pclk"; | ||
275 | status = "disabled"; | ||
276 | }; | ||
267 | }; | 277 | }; |