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authorDevin Heitmueller <dheitmueller@kernellabs.com>2009-10-04 23:34:04 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-07-27 16:52:30 -0400
commitf1c78d340fc21adb01f89f9bee15c58b533bffd7 (patch)
treea3f6798f1469e08eb42aebb094260ad0a712a090
parent799ed11afe7694858584d1ed4e9ae2f9e48142ec (diff)
[media] dib0700: fixup PLL config for PCTV 340e
Based on a reference trace under Windows, reverse engineer the PLL config. Note that the xtal is not yet setup, and the timf cannot be determined yet because my reference trace doesn't actually achieve a signal lock. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Cc: Patrick Boettcher <pboettcher@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c42
1 files changed, 41 insertions, 1 deletions
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index aaf1eabf175f..790fca63248a 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -2735,13 +2735,53 @@ static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
2735 .perform_agc_softsplit = 0x00, 2735 .perform_agc_softsplit = 0x00,
2736}; 2736};
2737 2737
2738/* validation:
2739 reg 900 (0x0384) = 0x0e60
2740 reg 903 (0x0387) = 0x0027
2741 reg 18 (0x0012) = 0x0321
2742 reg 19 (0x0013) = 0x1620
2743 reg 21 (0x0015) = 0x0265
2744 reg 22 (0x0016) = 0x6cbd
2745 reg 23 (0x0017) = 0x0138
2746 reg 24 (0x0018) = 0x1381
2747 reg 72 (0x0048) = 0xd257
2748 internal = 52500
2749 sampling = never seems to be used?
2750 pll_prediv = 1
2751 pll_ratio = 7
2752 pll_range = 3
2753 pll_reset = 1
2754 pll_bypass = 0
2755 enable_refdiv = 0
2756 bypclk_div = 0
2757 IO_CLK_en_core = 1
2758 ADClkSrc = 1
2759 modulo = 0
2760 sad_cfg: = 0xd257
2761 refsel = (3 << 14)
2762 sel = (1 << 12)
2763 freq_15k = (599 << 0)
2764 ifreq = 40201405
2765 timf = ? (need lock to compute)
2766 xtal_hz = ? (val dependent on exact tuning freq)
2767 */
2768static struct dibx000_bandwidth_config stk7700p_xc4000_pll_config = {
2769 52500, 30000, // internal, sampling
2770 1, 7, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
2771 0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo
2772 (3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k
2773 40201405, // ifreq
2774 20452225, // timf
2775 30000000, // xtal
2776};
2777
2738/* FIXME: none of these inputs are validated yet */ 2778/* FIXME: none of these inputs are validated yet */
2739static struct dib7000p_config pctv_340e_config = { 2779static struct dib7000p_config pctv_340e_config = {
2740 .output_mpeg2_in_188_bytes = 1, // validated L3317: 0x00eb=0x0066 2780 .output_mpeg2_in_188_bytes = 1, // validated L3317: 0x00eb=0x0066
2741 2781
2742 .agc_config_count = 1, 2782 .agc_config_count = 1,
2743 .agc = &stk7700p_7000p_xc4000_agc_config, 2783 .agc = &stk7700p_7000p_xc4000_agc_config,
2744 .bw = &stk7700p_pll_config, 2784 .bw = &stk7700p_xc4000_pll_config,
2745 2785
2746 .gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS, 2786 .gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,
2747 .gpio_val = DIB7000M_GPIO_DEFAULT_VALUES, 2787 .gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,