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authorAnton Blanchard <anton@samba.org>2006-02-13 02:11:13 -0500
committerPaul Mackerras <paulus@samba.org>2006-02-23 19:36:33 -0500
commitf1870f772c5e884862b4dd8f1ec2147247dda0ef (patch)
tree652414b8090a4b24e03aba76ddd37d83b762b88b
parentcb2c9b2741346eb23b177187a51ff5abf08295bd (diff)
[PATCH] powerpc64: remove broken/bitrotted HMT support
HMT support is currently broken and needs to be reworked to play nicely with the SMT scheduler. Remove the bit rotten bits for the time being. I also updated an incorrect comment, we enter __secondary_hold with the physical cpu id in r3. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/kernel/head_64.S97
-rw-r--r--arch/powerpc/kernel/prom_init.c38
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig7
3 files changed, 4 insertions, 138 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index bb845eed0e98..11f2cd5af7dc 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -139,7 +139,7 @@ _GLOBAL(__secondary_hold)
139 ori r24,r24,MSR_RI 139 ori r24,r24,MSR_RI
140 mtmsrd r24 /* RI on */ 140 mtmsrd r24 /* RI on */
141 141
142 /* Grab our linux cpu number */ 142 /* Grab our physical cpu number */
143 mr r24,r3 143 mr r24,r3
144 144
145 /* Tell the master cpu we're here */ 145 /* Tell the master cpu we're here */
@@ -153,11 +153,7 @@ _GLOBAL(__secondary_hold)
153 cmpdi 0,r4,1 153 cmpdi 0,r4,1
154 bne 100b 154 bne 100b
155 155
156#ifdef CONFIG_HMT 156#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
157 SET_REG_IMMEDIATE(r4, .hmt_init)
158 mtctr r4
159 bctr
160#elif defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
161 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init) 157 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
162 mtctr r4 158 mtctr r4
163 mr r3,r24 159 mr r3,r24
@@ -1808,22 +1804,6 @@ _STATIC(start_here_multiplatform)
1808 ori r6,r6,MSR_RI 1804 ori r6,r6,MSR_RI
1809 mtmsrd r6 /* RI on */ 1805 mtmsrd r6 /* RI on */
1810 1806
1811#ifdef CONFIG_HMT
1812 /* Start up the second thread on cpu 0 */
1813 mfspr r3,SPRN_PVR
1814 srwi r3,r3,16
1815 cmpwi r3,0x34 /* Pulsar */
1816 beq 90f
1817 cmpwi r3,0x36 /* Icestar */
1818 beq 90f
1819 cmpwi r3,0x37 /* SStar */
1820 beq 90f
1821 b 91f /* HMT not supported */
182290: li r3,0
1823 bl .hmt_start_secondary
182491:
1825#endif
1826
1827 /* The following gets the stack and TOC set up with the regs */ 1807 /* The following gets the stack and TOC set up with the regs */
1828 /* pointing to the real addr of the kernel stack. This is */ 1808 /* pointing to the real addr of the kernel stack. This is */
1829 /* all done to support the C function call below which sets */ 1809 /* all done to support the C function call below which sets */
@@ -1937,77 +1917,8 @@ _STATIC(start_here_common)
1937 1917
1938 bl .start_kernel 1918 bl .start_kernel
1939 1919
1940_GLOBAL(hmt_init) 1920 /* Not reached */
1941#ifdef CONFIG_HMT 1921 BUG_OPCODE
1942 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1943 mfspr r7,SPRN_PVR
1944 srwi r7,r7,16
1945 cmpwi r7,0x34 /* Pulsar */
1946 beq 90f
1947 cmpwi r7,0x36 /* Icestar */
1948 beq 91f
1949 cmpwi r7,0x37 /* SStar */
1950 beq 91f
1951 b 101f
195290: mfspr r6,SPRN_PIR
1953 andi. r6,r6,0x1f
1954 b 92f
195591: mfspr r6,SPRN_PIR
1956 andi. r6,r6,0x3ff
195792: sldi r4,r24,3
1958 stwx r6,r5,r4
1959 bl .hmt_start_secondary
1960 b 101f
1961
1962__hmt_secondary_hold:
1963 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1964 clrldi r5,r5,4
1965 li r7,0
1966 mfspr r6,SPRN_PIR
1967 mfspr r8,SPRN_PVR
1968 srwi r8,r8,16
1969 cmpwi r8,0x34
1970 bne 93f
1971 andi. r6,r6,0x1f
1972 b 103f
197393: andi. r6,r6,0x3f
1974
1975103: lwzx r8,r5,r7
1976 cmpw r8,r6
1977 beq 104f
1978 addi r7,r7,8
1979 b 103b
1980
1981104: addi r7,r7,4
1982 lwzx r9,r5,r7
1983 mr r24,r9
1984101:
1985#endif
1986 mr r3,r24
1987 b .pSeries_secondary_smp_init
1988
1989#ifdef CONFIG_HMT
1990_GLOBAL(hmt_start_secondary)
1991 LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold)
1992 clrldi r4,r4,4
1993 mtspr SPRN_NIADORM, r4
1994 mfspr r4, SPRN_MSRDORM
1995 li r5, -65
1996 and r4, r4, r5
1997 mtspr SPRN_MSRDORM, r4
1998 lis r4,0xffef
1999 ori r4,r4,0x7403
2000 mtspr SPRN_TSC, r4
2001 li r4,0x1f4
2002 mtspr SPRN_TST, r4
2003 mfspr r4, SPRN_HID0
2004 ori r4, r4, 0x1
2005 mtspr SPRN_HID0, r4
2006 mfspr r4, SPRN_CTRLF
2007 oris r4, r4, 0x40
2008 mtspr SPRN_CTRLT, r4
2009 blr
2010#endif
2011 1922
2012/* 1923/*
2013 * We put a few things here that have to be page-aligned. 1924 * We put a few things here that have to be page-aligned.
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index ec7153f4d47c..d34fe537400e 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -205,14 +205,6 @@ static cell_t __initdata regbuf[1024];
205 205
206#define MAX_CPU_THREADS 2 206#define MAX_CPU_THREADS 2
207 207
208/* TO GO */
209#ifdef CONFIG_HMT
210struct {
211 unsigned int pir;
212 unsigned int threadid;
213} hmt_thread_data[NR_CPUS];
214#endif /* CONFIG_HMT */
215
216/* 208/*
217 * Error results ... some OF calls will return "-1" on error, some 209 * Error results ... some OF calls will return "-1" on error, some
218 * will return 0, some will return either. To simplify, here are 210 * will return 0, some will return either. To simplify, here are
@@ -1319,10 +1311,6 @@ static void __init prom_hold_cpus(void)
1319 */ 1311 */
1320 *spinloop = 0; 1312 *spinloop = 0;
1321 1313
1322#ifdef CONFIG_HMT
1323 for (i = 0; i < NR_CPUS; i++)
1324 RELOC(hmt_thread_data)[i].pir = 0xdeadbeef;
1325#endif
1326 /* look for cpus */ 1314 /* look for cpus */
1327 for (node = 0; prom_next_node(&node); ) { 1315 for (node = 0; prom_next_node(&node); ) {
1328 type[0] = 0; 1316 type[0] = 0;
@@ -1389,32 +1377,6 @@ static void __init prom_hold_cpus(void)
1389 /* Reserve cpu #s for secondary threads. They start later. */ 1377 /* Reserve cpu #s for secondary threads. They start later. */
1390 cpuid += cpu_threads; 1378 cpuid += cpu_threads;
1391 } 1379 }
1392#ifdef CONFIG_HMT
1393 /* Only enable HMT on processors that provide support. */
1394 if (__is_processor(PV_PULSAR) ||
1395 __is_processor(PV_ICESTAR) ||
1396 __is_processor(PV_SSTAR)) {
1397 prom_printf(" starting secondary threads\n");
1398
1399 for (i = 0; i < NR_CPUS; i += 2) {
1400 if (!cpu_online(i))
1401 continue;
1402
1403 if (i == 0) {
1404 unsigned long pir = mfspr(SPRN_PIR);
1405 if (__is_processor(PV_PULSAR)) {
1406 RELOC(hmt_thread_data)[i].pir =
1407 pir & 0x1f;
1408 } else {
1409 RELOC(hmt_thread_data)[i].pir =
1410 pir & 0x3ff;
1411 }
1412 }
1413 }
1414 } else {
1415 prom_printf("Processor is not HMT capable\n");
1416 }
1417#endif
1418 1380
1419 if (cpuid > NR_CPUS) 1381 if (cpuid > NR_CPUS)
1420 prom_printf("WARNING: maximum CPUs (" __stringify(NR_CPUS) 1382 prom_printf("WARNING: maximum CPUs (" __stringify(NR_CPUS)
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index e3fc3407bb1f..4e5c8f8d869d 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -9,13 +9,6 @@ config PPC_SPLPAR
9 processors, that is, which share physical processors between 9 processors, that is, which share physical processors between
10 two or more partitions. 10 two or more partitions.
11 11
12config HMT
13 bool "Hardware multithreading"
14 depends on SMP && PPC_PSERIES && BROKEN
15 help
16 This option enables hardware multithreading on RS64 cpus.
17 pSeries systems p620 and p660 have such a cpu type.
18
19config EEH 12config EEH
20 bool "PCI Extended Error Handling (EEH)" if EMBEDDED 13 bool "PCI Extended Error Handling (EEH)" if EMBEDDED
21 depends on PPC_PSERIES 14 depends on PPC_PSERIES