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authorDave Airlie <airlied@redhat.com>2013-04-16 18:48:23 -0400
committerDave Airlie <airlied@redhat.com>2013-04-16 18:48:23 -0400
commitf18353eee7570412adca210b4968ecf2783754ba (patch)
treef42a655004a9ed7047bfca6bce694ea7a395f0e6
parent62c8ba7c58e4163f975c5f8b5a3dd5f306a2deda (diff)
parent466476dfdcafbb4286ffa232a3a792731b9dc852 (diff)
Merge branch 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: This is the initial 3.10 pull request for radeon. The big changes here are UVD support and proper tiling support for SI. The rest is bug fixes. I hope to have another pull request later in the week with some new things we've been working on internally. * 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux: (28 commits) drm/radeon: Always flush the VM drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN drm/radeon: cleanup properly if mmio mapping fails drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS drm/radeon: add si tile mode array query v3 drm/radeon: add ring working query drm/radeon: handle broken disabled rb mask gracefully drm/radeon: add pcie set/get lanes callbacks for newer asics drm/radeon: update r600 set/get pcie lane config drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT drm/radeon: remove unused blit remnants from si.c drm/radeon: add UVD tiling addr config v2 drm/radeon: init UVD clocks to sane defaults drm/radeon: add set_uvd_clocks callback for r7xx v3 drm/radeon: add set_uvd_clocks callback for SI drm/radeon: add set_uvd_clocks callback for evergreen drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4) drm/radeon: add radeon_atom_get_clock_dividers helper drm/radeon: add pm callback for setting uvd clocks drm/radeon: UVD bringup v8 ...
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c298
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h47
-rw-r--r--drivers/gpu/drm/radeon/ni.c127
-rw-r--r--drivers/gpu/drm/radeon/nid.h21
-rw-r--r--drivers/gpu/drm/radeon/r600.c388
-rw-r--r--drivers/gpu/drm/radeon/r600d.h61
-rw-r--r--drivers/gpu/drm/radeon/radeon.h61
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c82
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c107
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c79
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c187
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c72
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c666
-rw-r--r--drivers/gpu/drm/radeon/rs690.c23
-rw-r--r--drivers/gpu/drm/radeon/rs690d.h3
-rw-r--r--drivers/gpu/drm/radeon/rv515.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c327
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h43
-rw-r--r--drivers/gpu/drm/radeon/si.c260
-rw-r--r--drivers/gpu/drm/radeon/sid.h40
-rw-r--r--include/uapi/drm/radeon_drm.h26
32 files changed, 2737 insertions, 332 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index bf172522ea68..86c5e3611892 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ 77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ 78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
79 si_blit_shaders.o radeon_prime.o 79 si_blit_shaders.o radeon_prime.o radeon_uvd.o
80 80
81radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 81radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
82radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 82radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 21a892c6ab9c..6d6fdb3ba0d0 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -557,6 +557,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
557 /* use frac fb div on APUs */ 557 /* use frac fb div on APUs */
558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 /* use frac fb div on RS780/RS880 */
561 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
562 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 563 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
561 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 564 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
562 } else { 565 } else {
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 305a657bf215..124c19365392 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -84,6 +84,217 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
84 } 84 }
85} 85}
86 86
87static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
88 u32 cntl_reg, u32 status_reg)
89{
90 int r, i;
91 struct atom_clock_dividers dividers;
92
93 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
94 clock, false, &dividers);
95 if (r)
96 return r;
97
98 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
99
100 for (i = 0; i < 100; i++) {
101 if (RREG32(status_reg) & DCLK_STATUS)
102 break;
103 mdelay(10);
104 }
105 if (i == 100)
106 return -ETIMEDOUT;
107
108 return 0;
109}
110
111int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
112{
113 int r = 0;
114 u32 cg_scratch = RREG32(CG_SCRATCH1);
115
116 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
117 if (r)
118 goto done;
119 cg_scratch &= 0xffff0000;
120 cg_scratch |= vclk / 100; /* Mhz */
121
122 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
123 if (r)
124 goto done;
125 cg_scratch &= 0x0000ffff;
126 cg_scratch |= (dclk / 100) << 16; /* Mhz */
127
128done:
129 WREG32(CG_SCRATCH1, cg_scratch);
130
131 return r;
132}
133
134static int evergreen_uvd_calc_post_div(unsigned target_freq,
135 unsigned vco_freq,
136 unsigned *div)
137{
138 /* target larger than vco frequency ? */
139 if (vco_freq < target_freq)
140 return -1; /* forget it */
141
142 /* Fclk = Fvco / PDIV */
143 *div = vco_freq / target_freq;
144
145 /* we alway need a frequency less than or equal the target */
146 if ((vco_freq / *div) > target_freq)
147 *div += 1;
148
149 /* dividers above 5 must be even */
150 if (*div > 5 && *div % 2)
151 *div += 1;
152
153 /* out of range ? */
154 if (*div >= 128)
155 return -1; /* forget it */
156
157 return vco_freq / *div;
158}
159
160static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
161{
162 unsigned i;
163
164 /* assert UPLL_CTLREQ */
165 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
166
167 /* wait for CTLACK and CTLACK2 to get asserted */
168 for (i = 0; i < 100; ++i) {
169 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
170 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
171 break;
172 mdelay(10);
173 }
174 if (i == 100)
175 return -ETIMEDOUT;
176
177 /* deassert UPLL_CTLREQ */
178 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
179
180 return 0;
181}
182
183int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
184{
185 /* start off with something large */
186 int optimal_diff_score = 0x7FFFFFF;
187 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
188 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
189 unsigned vco_freq;
190 int r;
191
192 /* loop through vco from low to high */
193 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
194 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
195 int calc_clk, diff_score, diff_vclk, diff_dclk;
196 unsigned vclk_div, dclk_div;
197
198 /* fb div out of range ? */
199 if (fb_div > 0x03FFFFFF)
200 break; /* it can oly get worse */
201
202 /* calc vclk with current vco freq. */
203 calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
204 if (calc_clk == -1)
205 break; /* vco is too big, it has to stop. */
206 diff_vclk = vclk - calc_clk;
207
208 /* calc dclk with current vco freq. */
209 calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
210 if (calc_clk == -1)
211 break; /* vco is too big, it has to stop. */
212 diff_dclk = dclk - calc_clk;
213
214 /* determine if this vco setting is better than current optimal settings */
215 diff_score = abs(diff_vclk) + abs(diff_dclk);
216 if (diff_score < optimal_diff_score) {
217 optimal_fb_div = fb_div;
218 optimal_vclk_div = vclk_div;
219 optimal_dclk_div = dclk_div;
220 optimal_vco_freq = vco_freq;
221 optimal_diff_score = diff_score;
222 if (optimal_diff_score == 0)
223 break; /* it can't get better than this */
224 }
225 }
226
227 /* set VCO_MODE to 1 */
228 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
229
230 /* toggle UPLL_SLEEP to 1 then back to 0 */
231 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
232 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
233
234 /* deassert UPLL_RESET */
235 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
236
237 mdelay(1);
238
239 /* bypass vclk and dclk with bclk */
240 WREG32_P(CG_UPLL_FUNC_CNTL_2,
241 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
242 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
243
244 /* put PLL in bypass mode */
245 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
246
247 r = evergreen_uvd_send_upll_ctlreq(rdev);
248 if (r)
249 return r;
250
251 /* assert UPLL_RESET again */
252 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
253
254 /* disable spread spectrum. */
255 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
256
257 /* set feedback divider */
258 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
259
260 /* set ref divider to 0 */
261 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
262
263 if (optimal_vco_freq < 187500)
264 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
265 else
266 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
267
268 /* set PDIV_A and PDIV_B */
269 WREG32_P(CG_UPLL_FUNC_CNTL_2,
270 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
271 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
272
273 /* give the PLL some time to settle */
274 mdelay(15);
275
276 /* deassert PLL_RESET */
277 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
278
279 mdelay(15);
280
281 /* switch from bypass mode to normal mode */
282 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
283
284 r = evergreen_uvd_send_upll_ctlreq(rdev);
285 if (r)
286 return r;
287
288 /* switch VCLK and DCLK selection */
289 WREG32_P(CG_UPLL_FUNC_CNTL_2,
290 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
291 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
292
293 mdelay(100);
294
295 return 0;
296}
297
87void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 298void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88{ 299{
89 u16 ctl, v; 300 u16 ctl, v;
@@ -608,6 +819,16 @@ void evergreen_hpd_init(struct radeon_device *rdev)
608 819
609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 820 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
610 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 821 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
822
823 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
824 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
825 /* don't try to enable hpd on eDP or LVDS avoid breaking the
826 * aux dp channel on imac and help (but not completely fix)
827 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
828 * also avoid interrupt storms during dpms.
829 */
830 continue;
831 }
611 switch (radeon_connector->hpd.hpd) { 832 switch (radeon_connector->hpd.hpd) {
612 case RADEON_HPD_1: 833 case RADEON_HPD_1:
613 WREG32(DC_HPD1_CONTROL, tmp); 834 WREG32(DC_HPD1_CONTROL, tmp);
@@ -2050,6 +2271,14 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2050 } 2271 }
2051 /* enabled rb are just the one not disabled :) */ 2272 /* enabled rb are just the one not disabled :) */
2052 disabled_rb_mask = tmp; 2273 disabled_rb_mask = tmp;
2274 tmp = 0;
2275 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
2276 tmp |= (1 << i);
2277 /* if all the backends are disabled, fix it up here */
2278 if ((disabled_rb_mask & tmp) == tmp) {
2279 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
2280 disabled_rb_mask &= ~(1 << i);
2281 }
2053 2282
2054 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2283 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2055 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2284 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
@@ -2058,6 +2287,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2058 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2287 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2059 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2288 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2060 WREG32(DMA_TILING_CONFIG, gb_addr_config); 2289 WREG32(DMA_TILING_CONFIG, gb_addr_config);
2290 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
2291 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2292 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2061 2293
2062 if ((rdev->config.evergreen.max_backends == 1) && 2294 if ((rdev->config.evergreen.max_backends == 1) &&
2063 (rdev->flags & RADEON_IS_IGP)) { 2295 (rdev->flags & RADEON_IS_IGP)) {
@@ -3360,6 +3592,9 @@ restart_ih:
3360 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 3592 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3361 break; 3593 break;
3362 } 3594 }
3595 case 124: /* UVD */
3596 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
3597 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
3363 break; 3598 break;
3364 case 146: 3599 case 146:
3365 case 147: 3600 case 147:
@@ -3571,7 +3806,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
3571 3806
3572static int evergreen_startup(struct radeon_device *rdev) 3807static int evergreen_startup(struct radeon_device *rdev)
3573{ 3808{
3574 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3809 struct radeon_ring *ring;
3575 int r; 3810 int r;
3576 3811
3577 /* enable pcie gen2 link */ 3812 /* enable pcie gen2 link */
@@ -3638,6 +3873,17 @@ static int evergreen_startup(struct radeon_device *rdev)
3638 return r; 3873 return r;
3639 } 3874 }
3640 3875
3876 r = rv770_uvd_resume(rdev);
3877 if (!r) {
3878 r = radeon_fence_driver_start_ring(rdev,
3879 R600_RING_TYPE_UVD_INDEX);
3880 if (r)
3881 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
3882 }
3883
3884 if (r)
3885 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3886
3641 /* Enable IRQ */ 3887 /* Enable IRQ */
3642 r = r600_irq_init(rdev); 3888 r = r600_irq_init(rdev);
3643 if (r) { 3889 if (r) {
@@ -3647,6 +3893,7 @@ static int evergreen_startup(struct radeon_device *rdev)
3647 } 3893 }
3648 evergreen_irq_set(rdev); 3894 evergreen_irq_set(rdev);
3649 3895
3896 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3650 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3897 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3651 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3898 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3652 0, 0xfffff, RADEON_CP_PACKET2); 3899 0, 0xfffff, RADEON_CP_PACKET2);
@@ -3670,6 +3917,19 @@ static int evergreen_startup(struct radeon_device *rdev)
3670 if (r) 3917 if (r)
3671 return r; 3918 return r;
3672 3919
3920 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3921 if (ring->ring_size) {
3922 r = radeon_ring_init(rdev, ring, ring->ring_size,
3923 R600_WB_UVD_RPTR_OFFSET,
3924 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
3925 0, 0xfffff, RADEON_CP_PACKET2);
3926 if (!r)
3927 r = r600_uvd_init(rdev);
3928
3929 if (r)
3930 DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
3931 }
3932
3673 r = radeon_ib_pool_init(rdev); 3933 r = radeon_ib_pool_init(rdev);
3674 if (r) { 3934 if (r) {
3675 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3935 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -3716,8 +3976,10 @@ int evergreen_resume(struct radeon_device *rdev)
3716int evergreen_suspend(struct radeon_device *rdev) 3976int evergreen_suspend(struct radeon_device *rdev)
3717{ 3977{
3718 r600_audio_fini(rdev); 3978 r600_audio_fini(rdev);
3979 radeon_uvd_suspend(rdev);
3719 r700_cp_stop(rdev); 3980 r700_cp_stop(rdev);
3720 r600_dma_stop(rdev); 3981 r600_dma_stop(rdev);
3982 r600_uvd_rbc_stop(rdev);
3721 evergreen_irq_suspend(rdev); 3983 evergreen_irq_suspend(rdev);
3722 radeon_wb_disable(rdev); 3984 radeon_wb_disable(rdev);
3723 evergreen_pcie_gart_disable(rdev); 3985 evergreen_pcie_gart_disable(rdev);
@@ -3797,6 +4059,13 @@ int evergreen_init(struct radeon_device *rdev)
3797 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 4059 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3798 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 4060 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3799 4061
4062 r = radeon_uvd_init(rdev);
4063 if (!r) {
4064 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4065 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
4066 4096);
4067 }
4068
3800 rdev->ih.ring_obj = NULL; 4069 rdev->ih.ring_obj = NULL;
3801 r600_ih_ring_init(rdev, 64 * 1024); 4070 r600_ih_ring_init(rdev, 64 * 1024);
3802 4071
@@ -3843,6 +4112,7 @@ void evergreen_fini(struct radeon_device *rdev)
3843 radeon_ib_pool_fini(rdev); 4112 radeon_ib_pool_fini(rdev);
3844 radeon_irq_kms_fini(rdev); 4113 radeon_irq_kms_fini(rdev);
3845 evergreen_pcie_gart_fini(rdev); 4114 evergreen_pcie_gart_fini(rdev);
4115 radeon_uvd_fini(rdev);
3846 r600_vram_scratch_fini(rdev); 4116 r600_vram_scratch_fini(rdev);
3847 radeon_gem_fini(rdev); 4117 radeon_gem_fini(rdev);
3848 radeon_fence_driver_fini(rdev); 4118 radeon_fence_driver_fini(rdev);
@@ -3878,7 +4148,7 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3878 if (!(mask & DRM_PCIE_SPEED_50)) 4148 if (!(mask & DRM_PCIE_SPEED_50))
3879 return; 4149 return;
3880 4150
3881 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4151 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3882 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4152 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3883 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4153 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3884 return; 4154 return;
@@ -3889,33 +4159,33 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3889 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 4159 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3890 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4160 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3891 4161
3892 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4162 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
3893 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4163 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3894 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4164 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3895 4165
3896 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4166 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3897 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4167 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3898 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4168 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3899 4169
3900 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4170 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3901 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 4171 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3902 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4172 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3903 4173
3904 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4174 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3905 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 4175 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3906 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4176 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3907 4177
3908 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4178 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3909 speed_cntl |= LC_GEN2_EN_STRAP; 4179 speed_cntl |= LC_GEN2_EN_STRAP;
3910 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4180 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3911 4181
3912 } else { 4182 } else {
3913 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4183 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
3914 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4184 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3915 if (1) 4185 if (1)
3916 link_width_cntl |= LC_UPCONFIGURE_DIS; 4186 link_width_cntl |= LC_UPCONFIGURE_DIS;
3917 else 4187 else
3918 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4188 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3919 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4189 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3920 } 4190 }
3921} 4191}
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 982d25ad9af3..eabf92af84e5 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -53,6 +53,43 @@
53#define RCU_IND_INDEX 0x100 53#define RCU_IND_INDEX 0x100
54#define RCU_IND_DATA 0x104 54#define RCU_IND_DATA 0x104
55 55
56/* discrete uvd clocks */
57#define CG_UPLL_FUNC_CNTL 0x718
58# define UPLL_RESET_MASK 0x00000001
59# define UPLL_SLEEP_MASK 0x00000002
60# define UPLL_BYPASS_EN_MASK 0x00000004
61# define UPLL_CTLREQ_MASK 0x00000008
62# define UPLL_REF_DIV_MASK 0x001F0000
63# define UPLL_VCO_MODE_MASK 0x00000200
64# define UPLL_CTLACK_MASK 0x40000000
65# define UPLL_CTLACK2_MASK 0x80000000
66#define CG_UPLL_FUNC_CNTL_2 0x71c
67# define UPLL_PDIV_A(x) ((x) << 0)
68# define UPLL_PDIV_A_MASK 0x0000007F
69# define UPLL_PDIV_B(x) ((x) << 8)
70# define UPLL_PDIV_B_MASK 0x00007F00
71# define VCLK_SRC_SEL(x) ((x) << 20)
72# define VCLK_SRC_SEL_MASK 0x01F00000
73# define DCLK_SRC_SEL(x) ((x) << 25)
74# define DCLK_SRC_SEL_MASK 0x3E000000
75#define CG_UPLL_FUNC_CNTL_3 0x720
76# define UPLL_FB_DIV(x) ((x) << 0)
77# define UPLL_FB_DIV_MASK 0x01FFFFFF
78#define CG_UPLL_FUNC_CNTL_4 0x854
79# define UPLL_SPARE_ISPARE9 0x00020000
80#define CG_UPLL_SPREAD_SPECTRUM 0x79c
81# define SSEN_MASK 0x00000001
82
83/* fusion uvd clocks */
84#define CG_DCLK_CNTL 0x610
85# define DCLK_DIVIDER_MASK 0x7f
86# define DCLK_DIR_CNTL_EN (1 << 8)
87#define CG_DCLK_STATUS 0x614
88# define DCLK_STATUS (1 << 0)
89#define CG_VCLK_CNTL 0x618
90#define CG_VCLK_STATUS 0x61c
91#define CG_SCRATCH1 0x820
92
56#define GRBM_GFX_INDEX 0x802C 93#define GRBM_GFX_INDEX 0x802C
57#define INSTANCE_INDEX(x) ((x) << 0) 94#define INSTANCE_INDEX(x) ((x) << 0)
58#define SE_INDEX(x) ((x) << 16) 95#define SE_INDEX(x) ((x) << 16)
@@ -992,6 +1029,16 @@
992# define TARGET_LINK_SPEED_MASK (0xf << 0) 1029# define TARGET_LINK_SPEED_MASK (0xf << 0)
993# define SELECTABLE_DEEMPHASIS (1 << 6) 1030# define SELECTABLE_DEEMPHASIS (1 << 6)
994 1031
1032
1033/*
1034 * UVD
1035 */
1036#define UVD_UDEC_ADDR_CONFIG 0xef4c
1037#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1038#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1039#define UVD_RBC_RB_RPTR 0xf690
1040#define UVD_RBC_RB_WPTR 0xf694
1041
995/* 1042/*
996 * PM4 1043 * PM4
997 */ 1044 */
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 27769e724b6d..fd03f318cc1c 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -615,15 +615,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
615 } 615 }
616 /* enabled rb are just the one not disabled :) */ 616 /* enabled rb are just the one not disabled :) */
617 disabled_rb_mask = tmp; 617 disabled_rb_mask = tmp;
618 tmp = 0;
619 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
620 tmp |= (1 << i);
621 /* if all the backends are disabled, fix it up here */
622 if ((disabled_rb_mask & tmp) == tmp) {
623 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
624 disabled_rb_mask &= ~(1 << i);
625 }
618 626
619 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 627 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
620 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 628 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
621 629
622 WREG32(GB_ADDR_CONFIG, gb_addr_config); 630 WREG32(GB_ADDR_CONFIG, gb_addr_config);
623 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 631 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
632 if (ASIC_IS_DCE6(rdev))
633 WREG32(DMIF_ADDR_CALC, gb_addr_config);
624 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 634 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
625 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 635 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
626 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 636 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
637 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
638 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
639 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
627 640
628 if ((rdev->config.cayman.max_backends_per_se == 1) && 641 if ((rdev->config.cayman.max_backends_per_se == 1) &&
629 (rdev->flags & RADEON_IS_IGP)) { 642 (rdev->flags & RADEON_IS_IGP)) {
@@ -931,6 +944,23 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
931 radeon_ring_write(ring, 10); /* poll interval */ 944 radeon_ring_write(ring, 10); /* poll interval */
932} 945}
933 946
947void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
948 struct radeon_ring *ring,
949 struct radeon_semaphore *semaphore,
950 bool emit_wait)
951{
952 uint64_t addr = semaphore->gpu_addr;
953
954 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
955 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
956
957 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
958 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
959
960 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
961 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
962}
963
934static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 964static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
935{ 965{
936 if (enable) 966 if (enable)
@@ -1682,6 +1712,16 @@ static int cayman_startup(struct radeon_device *rdev)
1682 return r; 1712 return r;
1683 } 1713 }
1684 1714
1715 r = rv770_uvd_resume(rdev);
1716 if (!r) {
1717 r = radeon_fence_driver_start_ring(rdev,
1718 R600_RING_TYPE_UVD_INDEX);
1719 if (r)
1720 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1721 }
1722 if (r)
1723 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1724
1685 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 1725 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1686 if (r) { 1726 if (r) {
1687 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1727 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
@@ -1748,6 +1788,18 @@ static int cayman_startup(struct radeon_device *rdev)
1748 if (r) 1788 if (r)
1749 return r; 1789 return r;
1750 1790
1791 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1792 if (ring->ring_size) {
1793 r = radeon_ring_init(rdev, ring, ring->ring_size,
1794 R600_WB_UVD_RPTR_OFFSET,
1795 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1796 0, 0xfffff, RADEON_CP_PACKET2);
1797 if (!r)
1798 r = r600_uvd_init(rdev);
1799 if (r)
1800 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1801 }
1802
1751 r = radeon_ib_pool_init(rdev); 1803 r = radeon_ib_pool_init(rdev);
1752 if (r) { 1804 if (r) {
1753 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1805 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -1794,6 +1846,8 @@ int cayman_suspend(struct radeon_device *rdev)
1794 radeon_vm_manager_fini(rdev); 1846 radeon_vm_manager_fini(rdev);
1795 cayman_cp_enable(rdev, false); 1847 cayman_cp_enable(rdev, false);
1796 cayman_dma_stop(rdev); 1848 cayman_dma_stop(rdev);
1849 r600_uvd_rbc_stop(rdev);
1850 radeon_uvd_suspend(rdev);
1797 evergreen_irq_suspend(rdev); 1851 evergreen_irq_suspend(rdev);
1798 radeon_wb_disable(rdev); 1852 radeon_wb_disable(rdev);
1799 cayman_pcie_gart_disable(rdev); 1853 cayman_pcie_gart_disable(rdev);
@@ -1868,6 +1922,13 @@ int cayman_init(struct radeon_device *rdev)
1868 ring->ring_obj = NULL; 1922 ring->ring_obj = NULL;
1869 r600_ring_init(rdev, ring, 64 * 1024); 1923 r600_ring_init(rdev, ring, 64 * 1024);
1870 1924
1925 r = radeon_uvd_init(rdev);
1926 if (!r) {
1927 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1928 ring->ring_obj = NULL;
1929 r600_ring_init(rdev, ring, 4096);
1930 }
1931
1871 rdev->ih.ring_obj = NULL; 1932 rdev->ih.ring_obj = NULL;
1872 r600_ih_ring_init(rdev, 64 * 1024); 1933 r600_ih_ring_init(rdev, 64 * 1024);
1873 1934
@@ -1919,6 +1980,7 @@ void cayman_fini(struct radeon_device *rdev)
1919 radeon_vm_manager_fini(rdev); 1980 radeon_vm_manager_fini(rdev);
1920 radeon_ib_pool_fini(rdev); 1981 radeon_ib_pool_fini(rdev);
1921 radeon_irq_kms_fini(rdev); 1982 radeon_irq_kms_fini(rdev);
1983 radeon_uvd_fini(rdev);
1922 cayman_pcie_gart_fini(rdev); 1984 cayman_pcie_gart_fini(rdev);
1923 r600_vram_scratch_fini(rdev); 1985 r600_vram_scratch_fini(rdev);
1924 radeon_gem_fini(rdev); 1986 radeon_gem_fini(rdev);
@@ -2017,28 +2079,57 @@ void cayman_vm_set_page(struct radeon_device *rdev,
2017 } 2079 }
2018 } 2080 }
2019 } else { 2081 } else {
2020 while (count) { 2082 if ((flags & RADEON_VM_PAGE_SYSTEM) ||
2021 ndw = count * 2; 2083 (count == 1)) {
2022 if (ndw > 0xFFFFE) 2084 while (count) {
2023 ndw = 0xFFFFE; 2085 ndw = count * 2;
2086 if (ndw > 0xFFFFE)
2087 ndw = 0xFFFFE;
2088
2089 /* for non-physically contiguous pages (system) */
2090 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2091 ib->ptr[ib->length_dw++] = pe;
2092 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2093 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2094 if (flags & RADEON_VM_PAGE_SYSTEM) {
2095 value = radeon_vm_map_gart(rdev, addr);
2096 value &= 0xFFFFFFFFFFFFF000ULL;
2097 } else if (flags & RADEON_VM_PAGE_VALID) {
2098 value = addr;
2099 } else {
2100 value = 0;
2101 }
2102 addr += incr;
2103 value |= r600_flags;
2104 ib->ptr[ib->length_dw++] = value;
2105 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2106 }
2107 }
2108 while (ib->length_dw & 0x7)
2109 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2110 } else {
2111 while (count) {
2112 ndw = count * 2;
2113 if (ndw > 0xFFFFE)
2114 ndw = 0xFFFFE;
2024 2115
2025 /* for non-physically contiguous pages (system) */ 2116 if (flags & RADEON_VM_PAGE_VALID)
2026 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2027 ib->ptr[ib->length_dw++] = pe;
2028 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2029 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2030 if (flags & RADEON_VM_PAGE_SYSTEM) {
2031 value = radeon_vm_map_gart(rdev, addr);
2032 value &= 0xFFFFFFFFFFFFF000ULL;
2033 } else if (flags & RADEON_VM_PAGE_VALID) {
2034 value = addr; 2117 value = addr;
2035 } else { 2118 else
2036 value = 0; 2119 value = 0;
2037 } 2120 /* for physically contiguous pages (vram) */
2038 addr += incr; 2121 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
2039 value |= r600_flags; 2122 ib->ptr[ib->length_dw++] = pe; /* dst addr */
2040 ib->ptr[ib->length_dw++] = value; 2123 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2124 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
2125 ib->ptr[ib->length_dw++] = 0;
2126 ib->ptr[ib->length_dw++] = value; /* value */
2041 ib->ptr[ib->length_dw++] = upper_32_bits(value); 2127 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2128 ib->ptr[ib->length_dw++] = incr; /* increment size */
2129 ib->ptr[ib->length_dw++] = 0;
2130 pe += ndw * 4;
2131 addr += (ndw / 2) * incr;
2132 count -= ndw / 2;
2042 } 2133 }
2043 } 2134 }
2044 while (ib->length_dw & 0x7) 2135 while (ib->length_dw & 0x7)
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 079dee202a9e..e226faf16fea 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
46 46
47#define DMIF_ADDR_CONFIG 0xBD4 47#define DMIF_ADDR_CONFIG 0xBD4
48
49/* DCE6 only */
50#define DMIF_ADDR_CALC 0xC00
51
48#define SRBM_GFX_CNTL 0x0E44 52#define SRBM_GFX_CNTL 0x0E44
49#define RINGID(x) (((x) & 0x3) << 0) 53#define RINGID(x) (((x) & 0x3) << 0)
50#define VMID(x) (((x) & 0x7) << 0) 54#define VMID(x) (((x) & 0x7) << 0)
@@ -486,6 +490,18 @@
486# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 490# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
487 491
488/* 492/*
493 * UVD
494 */
495#define UVD_SEMA_ADDR_LOW 0xEF00
496#define UVD_SEMA_ADDR_HIGH 0xEF04
497#define UVD_SEMA_CMD 0xEF08
498#define UVD_UDEC_ADDR_CONFIG 0xEF4C
499#define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
500#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
501#define UVD_RBC_RB_RPTR 0xF690
502#define UVD_RBC_RB_WPTR 0xF694
503
504/*
489 * PM4 505 * PM4
490 */ 506 */
491#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 507#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
@@ -668,6 +684,11 @@
668 (((vmid) & 0xF) << 20) | \ 684 (((vmid) & 0xF) << 20) | \
669 (((n) & 0xFFFFF) << 0)) 685 (((n) & 0xFFFFF) << 0))
670 686
687#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
688 (1 << 26) | \
689 (1 << 21) | \
690 (((n) & 0xFFFFF) << 0))
691
671/* async DMA Packet types */ 692/* async DMA Packet types */
672#define DMA_PACKET_WRITE 0x2 693#define DMA_PACKET_WRITE 0x2
673#define DMA_PACKET_COPY 0x3 694#define DMA_PACKET_COPY 0x3
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0740db3fcd22..5fe9e74d6360 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1145,7 +1145,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
1145 } 1145 }
1146 if (rdev->flags & RADEON_IS_AGP) { 1146 if (rdev->flags & RADEON_IS_AGP) {
1147 size_bf = mc->gtt_start; 1147 size_bf = mc->gtt_start;
1148 size_af = 0xFFFFFFFF - mc->gtt_end; 1148 size_af = mc->mc_mask - mc->gtt_end;
1149 if (size_bf > size_af) { 1149 if (size_bf > size_af) {
1150 if (mc->mc_vram_size > size_bf) { 1150 if (mc->mc_vram_size > size_bf) {
1151 dev_warn(rdev->dev, "limiting VRAM\n"); 1151 dev_warn(rdev->dev, "limiting VRAM\n");
@@ -2552,6 +2552,185 @@ void r600_dma_fini(struct radeon_device *rdev)
2552} 2552}
2553 2553
2554/* 2554/*
2555 * UVD
2556 */
2557int r600_uvd_rbc_start(struct radeon_device *rdev)
2558{
2559 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2560 uint64_t rptr_addr;
2561 uint32_t rb_bufsz, tmp;
2562 int r;
2563
2564 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
2565
2566 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
2567 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2568 return -EINVAL;
2569 }
2570
2571 /* force RBC into idle state */
2572 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2573
2574 /* Set the write pointer delay */
2575 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2576
2577 /* set the wb address */
2578 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
2579
2580 /* programm the 4GB memory segment for rptr and ring buffer */
2581 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
2582 (0x7 << 16) | (0x1 << 31));
2583
2584 /* Initialize the ring buffer's read and write pointers */
2585 WREG32(UVD_RBC_RB_RPTR, 0x0);
2586
2587 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2588 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2589
2590 /* set the ring address */
2591 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2592
2593 /* Set ring buffer size */
2594 rb_bufsz = drm_order(ring->ring_size);
2595 rb_bufsz = (0x1 << 8) | rb_bufsz;
2596 WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
2597
2598 ring->ready = true;
2599 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2600 if (r) {
2601 ring->ready = false;
2602 return r;
2603 }
2604
2605 r = radeon_ring_lock(rdev, ring, 10);
2606 if (r) {
2607 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2608 return r;
2609 }
2610
2611 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2612 radeon_ring_write(ring, tmp);
2613 radeon_ring_write(ring, 0xFFFFF);
2614
2615 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2616 radeon_ring_write(ring, tmp);
2617 radeon_ring_write(ring, 0xFFFFF);
2618
2619 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2620 radeon_ring_write(ring, tmp);
2621 radeon_ring_write(ring, 0xFFFFF);
2622
2623 /* Clear timeout status bits */
2624 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2625 radeon_ring_write(ring, 0x8);
2626
2627 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2628 radeon_ring_write(ring, 1);
2629
2630 radeon_ring_unlock_commit(rdev, ring);
2631
2632 return 0;
2633}
2634
2635void r600_uvd_rbc_stop(struct radeon_device *rdev)
2636{
2637 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2638
2639 /* force RBC into idle state */
2640 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2641 ring->ready = false;
2642}
2643
2644int r600_uvd_init(struct radeon_device *rdev)
2645{
2646 int i, j, r;
2647
2648 /* disable clock gating */
2649 WREG32(UVD_CGC_GATE, 0);
2650
2651 /* disable interupt */
2652 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2653
2654 /* put LMI, VCPU, RBC etc... into reset */
2655 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2656 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2657 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2658 mdelay(5);
2659
2660 /* take UVD block out of reset */
2661 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2662 mdelay(5);
2663
2664 /* initialize UVD memory controller */
2665 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2666 (1 << 21) | (1 << 9) | (1 << 20));
2667
2668 /* disable byte swapping */
2669 WREG32(UVD_LMI_SWAP_CNTL, 0);
2670 WREG32(UVD_MP_SWAP_CNTL, 0);
2671
2672 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2673 WREG32(UVD_MPC_SET_MUXA1, 0x0);
2674 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2675 WREG32(UVD_MPC_SET_MUXB1, 0x0);
2676 WREG32(UVD_MPC_SET_ALU, 0);
2677 WREG32(UVD_MPC_SET_MUX, 0x88);
2678
2679 /* Stall UMC */
2680 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2681 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2682
2683 /* take all subblocks out of reset, except VCPU */
2684 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2685 mdelay(5);
2686
2687 /* enable VCPU clock */
2688 WREG32(UVD_VCPU_CNTL, 1 << 9);
2689
2690 /* enable UMC */
2691 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2692
2693 /* boot up the VCPU */
2694 WREG32(UVD_SOFT_RESET, 0);
2695 mdelay(10);
2696
2697 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2698
2699 for (i = 0; i < 10; ++i) {
2700 uint32_t status;
2701 for (j = 0; j < 100; ++j) {
2702 status = RREG32(UVD_STATUS);
2703 if (status & 2)
2704 break;
2705 mdelay(10);
2706 }
2707 r = 0;
2708 if (status & 2)
2709 break;
2710
2711 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2712 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2713 mdelay(10);
2714 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2715 mdelay(10);
2716 r = -1;
2717 }
2718 if (r) {
2719 DRM_ERROR("UVD not responding, giving up!!!\n");
2720 return r;
2721 }
2722 /* enable interupt */
2723 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2724
2725 r = r600_uvd_rbc_start(rdev);
2726 if (r)
2727 return r;
2728
2729 DRM_INFO("UVD initialized successfully.\n");
2730 return 0;
2731}
2732
2733/*
2555 * GPU scratch registers helpers function. 2734 * GPU scratch registers helpers function.
2556 */ 2735 */
2557void r600_scratch_init(struct radeon_device *rdev) 2736void r600_scratch_init(struct radeon_device *rdev)
@@ -2660,6 +2839,40 @@ int r600_dma_ring_test(struct radeon_device *rdev,
2660 return r; 2839 return r;
2661} 2840}
2662 2841
2842int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2843{
2844 uint32_t tmp = 0;
2845 unsigned i;
2846 int r;
2847
2848 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
2849 r = radeon_ring_lock(rdev, ring, 3);
2850 if (r) {
2851 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2852 ring->idx, r);
2853 return r;
2854 }
2855 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2856 radeon_ring_write(ring, 0xDEADBEEF);
2857 radeon_ring_unlock_commit(rdev, ring);
2858 for (i = 0; i < rdev->usec_timeout; i++) {
2859 tmp = RREG32(UVD_CONTEXT_ID);
2860 if (tmp == 0xDEADBEEF)
2861 break;
2862 DRM_UDELAY(1);
2863 }
2864
2865 if (i < rdev->usec_timeout) {
2866 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2867 ring->idx, i);
2868 } else {
2869 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2870 ring->idx, tmp);
2871 r = -EINVAL;
2872 }
2873 return r;
2874}
2875
2663/* 2876/*
2664 * CP fences/semaphores 2877 * CP fences/semaphores
2665 */ 2878 */
@@ -2711,6 +2924,30 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2711 } 2924 }
2712} 2925}
2713 2926
2927void r600_uvd_fence_emit(struct radeon_device *rdev,
2928 struct radeon_fence *fence)
2929{
2930 struct radeon_ring *ring = &rdev->ring[fence->ring];
2931 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
2932
2933 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2934 radeon_ring_write(ring, fence->seq);
2935 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2936 radeon_ring_write(ring, addr & 0xffffffff);
2937 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2938 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2939 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2940 radeon_ring_write(ring, 0);
2941
2942 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2943 radeon_ring_write(ring, 0);
2944 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2945 radeon_ring_write(ring, 0);
2946 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2947 radeon_ring_write(ring, 2);
2948 return;
2949}
2950
2714void r600_semaphore_ring_emit(struct radeon_device *rdev, 2951void r600_semaphore_ring_emit(struct radeon_device *rdev,
2715 struct radeon_ring *ring, 2952 struct radeon_ring *ring,
2716 struct radeon_semaphore *semaphore, 2953 struct radeon_semaphore *semaphore,
@@ -2780,6 +3017,23 @@ void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2780 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3017 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2781} 3018}
2782 3019
3020void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3021 struct radeon_ring *ring,
3022 struct radeon_semaphore *semaphore,
3023 bool emit_wait)
3024{
3025 uint64_t addr = semaphore->gpu_addr;
3026
3027 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3028 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3029
3030 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3031 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3032
3033 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3034 radeon_ring_write(ring, emit_wait ? 1 : 0);
3035}
3036
2783int r600_copy_blit(struct radeon_device *rdev, 3037int r600_copy_blit(struct radeon_device *rdev,
2784 uint64_t src_offset, 3038 uint64_t src_offset,
2785 uint64_t dst_offset, 3039 uint64_t dst_offset,
@@ -3183,6 +3437,16 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3183 radeon_ring_write(ring, ib->length_dw); 3437 radeon_ring_write(ring, ib->length_dw);
3184} 3438}
3185 3439
3440void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3441{
3442 struct radeon_ring *ring = &rdev->ring[ib->ring];
3443
3444 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3445 radeon_ring_write(ring, ib->gpu_addr);
3446 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3447 radeon_ring_write(ring, ib->length_dw);
3448}
3449
3186int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3450int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3187{ 3451{
3188 struct radeon_ib ib; 3452 struct radeon_ib ib;
@@ -3300,6 +3564,33 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3300 return r; 3564 return r;
3301} 3565}
3302 3566
3567int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3568{
3569 struct radeon_fence *fence;
3570 int r;
3571
3572 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3573 if (r) {
3574 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3575 return r;
3576 }
3577
3578 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3579 if (r) {
3580 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3581 return r;
3582 }
3583
3584 r = radeon_fence_wait(fence, false);
3585 if (r) {
3586 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3587 return r;
3588 }
3589 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
3590 radeon_fence_unref(&fence);
3591 return r;
3592}
3593
3303/** 3594/**
3304 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3595 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3305 * 3596 *
@@ -4232,7 +4523,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4232 4523
4233void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4524void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4234{ 4525{
4235 u32 link_width_cntl, mask, target_reg; 4526 u32 link_width_cntl, mask;
4236 4527
4237 if (rdev->flags & RADEON_IS_IGP) 4528 if (rdev->flags & RADEON_IS_IGP)
4238 return; 4529 return;
@@ -4244,7 +4535,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4244 if (ASIC_IS_X2(rdev)) 4535 if (ASIC_IS_X2(rdev))
4245 return; 4536 return;
4246 4537
4247 /* FIXME wait for idle */ 4538 radeon_gui_idle(rdev);
4248 4539
4249 switch (lanes) { 4540 switch (lanes) {
4250 case 0: 4541 case 0:
@@ -4263,53 +4554,24 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4263 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4554 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4264 break; 4555 break;
4265 case 12: 4556 case 12:
4557 /* not actually supported */
4266 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4558 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4267 break; 4559 break;
4268 case 16: 4560 case 16:
4269 default:
4270 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4561 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4271 break; 4562 break;
4272 } 4563 default:
4273 4564 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4274 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4275
4276 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4277 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4278 return;
4279
4280 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4281 return; 4565 return;
4566 }
4282 4567
4283 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4568 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4284 RADEON_PCIE_LC_RECONFIG_NOW | 4569 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4285 R600_PCIE_LC_RENEGOTIATE_EN | 4570 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4286 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4571 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4287 link_width_cntl |= mask; 4572 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4288
4289 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4290
4291 /* some northbridges can renegotiate the link rather than requiring
4292 * a complete re-config.
4293 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4294 */
4295 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4296 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4297 else
4298 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4299
4300 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4301 RADEON_PCIE_LC_RECONFIG_NOW));
4302
4303 if (rdev->family >= CHIP_RV770)
4304 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4305 else
4306 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4307
4308 /* wait for lane set to complete */
4309 link_width_cntl = RREG32(target_reg);
4310 while (link_width_cntl == 0xffffffff)
4311 link_width_cntl = RREG32(target_reg);
4312 4573
4574 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4313} 4575}
4314 4576
4315int r600_get_pcie_lanes(struct radeon_device *rdev) 4577int r600_get_pcie_lanes(struct radeon_device *rdev)
@@ -4326,13 +4588,11 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
4326 if (ASIC_IS_X2(rdev)) 4588 if (ASIC_IS_X2(rdev))
4327 return 0; 4589 return 0;
4328 4590
4329 /* FIXME wait for idle */ 4591 radeon_gui_idle(rdev);
4330 4592
4331 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4593 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4332 4594
4333 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4595 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4334 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4335 return 0;
4336 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4596 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4337 return 1; 4597 return 1;
4338 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4598 case RADEON_PCIE_LC_LINK_WIDTH_X2:
@@ -4341,6 +4601,10 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
4341 return 4; 4601 return 4;
4342 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4602 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4343 return 8; 4603 return 8;
4604 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4605 /* not actually supported */
4606 return 12;
4607 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4344 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4608 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4345 default: 4609 default:
4346 return 16; 4610 return 16;
@@ -4378,7 +4642,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4378 if (!(mask & DRM_PCIE_SPEED_50)) 4642 if (!(mask & DRM_PCIE_SPEED_50))
4379 return; 4643 return;
4380 4644
4381 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4645 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4382 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4646 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4383 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4647 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4384 return; 4648 return;
@@ -4391,23 +4655,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4391 (rdev->family == CHIP_RV620) || 4655 (rdev->family == CHIP_RV620) ||
4392 (rdev->family == CHIP_RV635)) { 4656 (rdev->family == CHIP_RV635)) {
4393 /* advertise upconfig capability */ 4657 /* advertise upconfig capability */
4394 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4658 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4395 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4659 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4396 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4660 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4397 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4661 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4398 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4662 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4399 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4663 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4400 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4664 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4401 LC_RECONFIG_ARC_MISSING_ESCAPE); 4665 LC_RECONFIG_ARC_MISSING_ESCAPE);
4402 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4666 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4403 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4667 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4404 } else { 4668 } else {
4405 link_width_cntl |= LC_UPCONFIGURE_DIS; 4669 link_width_cntl |= LC_UPCONFIGURE_DIS;
4406 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4670 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4407 } 4671 }
4408 } 4672 }
4409 4673
4410 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4674 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4411 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4675 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4412 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4676 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4413 4677
@@ -4428,7 +4692,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4428 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4692 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4429 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4693 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4430 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4694 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4431 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4695 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4432 4696
4433 tmp = RREG32(0x541c); 4697 tmp = RREG32(0x541c);
4434 WREG32(0x541c, tmp | 0x8); 4698 WREG32(0x541c, tmp | 0x8);
@@ -4442,27 +4706,27 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4442 if ((rdev->family == CHIP_RV670) || 4706 if ((rdev->family == CHIP_RV670) ||
4443 (rdev->family == CHIP_RV620) || 4707 (rdev->family == CHIP_RV620) ||
4444 (rdev->family == CHIP_RV635)) { 4708 (rdev->family == CHIP_RV635)) {
4445 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4709 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4446 training_cntl &= ~LC_POINT_7_PLUS_EN; 4710 training_cntl &= ~LC_POINT_7_PLUS_EN;
4447 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4711 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4448 } else { 4712 } else {
4449 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4713 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4450 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4714 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4451 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4715 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4452 } 4716 }
4453 4717
4454 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4718 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4455 speed_cntl |= LC_GEN2_EN_STRAP; 4719 speed_cntl |= LC_GEN2_EN_STRAP;
4456 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4720 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4457 4721
4458 } else { 4722 } else {
4459 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4723 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4460 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4724 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4461 if (1) 4725 if (1)
4462 link_width_cntl |= LC_UPCONFIGURE_DIS; 4726 link_width_cntl |= LC_UPCONFIGURE_DIS;
4463 else 4727 else
4464 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4728 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4465 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4729 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4466 } 4730 }
4467} 4731}
4468 4732
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a42ba11a3bed..441bdb809a0b 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -691,6 +691,7 @@
691#define SRBM_SOFT_RESET 0xe60 691#define SRBM_SOFT_RESET 0xe60
692# define SOFT_RESET_DMA (1 << 12) 692# define SOFT_RESET_DMA (1 << 12)
693# define SOFT_RESET_RLC (1 << 13) 693# define SOFT_RESET_RLC (1 << 13)
694# define SOFT_RESET_UVD (1 << 18)
694# define RV770_SOFT_RESET_DMA (1 << 20) 695# define RV770_SOFT_RESET_DMA (1 << 20)
695 696
696#define CP_INT_CNTL 0xc124 697#define CP_INT_CNTL 0xc124
@@ -1143,6 +1144,66 @@
1143# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1144# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1144 1145
1145/* 1146/*
1147 * UVD
1148 */
1149#define UVD_SEMA_ADDR_LOW 0xef00
1150#define UVD_SEMA_ADDR_HIGH 0xef04
1151#define UVD_SEMA_CMD 0xef08
1152
1153#define UVD_GPCOM_VCPU_CMD 0xef0c
1154#define UVD_GPCOM_VCPU_DATA0 0xef10
1155#define UVD_GPCOM_VCPU_DATA1 0xef14
1156#define UVD_ENGINE_CNTL 0xef18
1157
1158#define UVD_SEMA_CNTL 0xf400
1159#define UVD_RB_ARB_CTRL 0xf480
1160
1161#define UVD_LMI_EXT40_ADDR 0xf498
1162#define UVD_CGC_GATE 0xf4a8
1163#define UVD_LMI_CTRL2 0xf4f4
1164#define UVD_MASTINT_EN 0xf500
1165#define UVD_LMI_ADDR_EXT 0xf594
1166#define UVD_LMI_CTRL 0xf598
1167#define UVD_LMI_SWAP_CNTL 0xf5b4
1168#define UVD_MP_SWAP_CNTL 0xf5bC
1169#define UVD_MPC_CNTL 0xf5dC
1170#define UVD_MPC_SET_MUXA0 0xf5e4
1171#define UVD_MPC_SET_MUXA1 0xf5e8
1172#define UVD_MPC_SET_MUXB0 0xf5eC
1173#define UVD_MPC_SET_MUXB1 0xf5f0
1174#define UVD_MPC_SET_MUX 0xf5f4
1175#define UVD_MPC_SET_ALU 0xf5f8
1176
1177#define UVD_VCPU_CNTL 0xf660
1178#define UVD_SOFT_RESET 0xf680
1179#define RBC_SOFT_RESET (1<<0)
1180#define LBSI_SOFT_RESET (1<<1)
1181#define LMI_SOFT_RESET (1<<2)
1182#define VCPU_SOFT_RESET (1<<3)
1183#define CSM_SOFT_RESET (1<<5)
1184#define CXW_SOFT_RESET (1<<6)
1185#define TAP_SOFT_RESET (1<<7)
1186#define LMI_UMC_SOFT_RESET (1<<13)
1187#define UVD_RBC_IB_BASE 0xf684
1188#define UVD_RBC_IB_SIZE 0xf688
1189#define UVD_RBC_RB_BASE 0xf68c
1190#define UVD_RBC_RB_RPTR 0xf690
1191#define UVD_RBC_RB_WPTR 0xf694
1192#define UVD_RBC_RB_WPTR_CNTL 0xf698
1193
1194#define UVD_STATUS 0xf6bc
1195
1196#define UVD_SEMA_TIMEOUT_STATUS 0xf6c0
1197#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4
1198#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8
1199#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc
1200
1201#define UVD_RBC_RB_CNTL 0xf6a4
1202#define UVD_RBC_RB_RPTR_ADDR 0xf6a8
1203
1204#define UVD_CONTEXT_ID 0xf6f4
1205
1206/*
1146 * PM4 1207 * PM4
1147 */ 1208 */
1148#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1209#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8263af3fd832..18904fb83d3a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -95,6 +95,7 @@ extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2; 95extern int radeon_pcie_gen2;
96extern int radeon_msi; 96extern int radeon_msi;
97extern int radeon_lockup_timeout; 97extern int radeon_lockup_timeout;
98extern int radeon_fastfb;
98 99
99/* 100/*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting 101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -109,24 +110,27 @@ extern int radeon_lockup_timeout;
109#define RADEON_BIOS_NUM_SCRATCH 8 110#define RADEON_BIOS_NUM_SCRATCH 8
110 111
111/* max number of rings */ 112/* max number of rings */
112#define RADEON_NUM_RINGS 5 113#define RADEON_NUM_RINGS 6
113 114
114/* fence seq are set to this number when signaled */ 115/* fence seq are set to this number when signaled */
115#define RADEON_FENCE_SIGNALED_SEQ 0LL 116#define RADEON_FENCE_SIGNALED_SEQ 0LL
116 117
117/* internal ring indices */ 118/* internal ring indices */
118/* r1xx+ has gfx CP ring */ 119/* r1xx+ has gfx CP ring */
119#define RADEON_RING_TYPE_GFX_INDEX 0 120#define RADEON_RING_TYPE_GFX_INDEX 0
120 121
121/* cayman has 2 compute CP rings */ 122/* cayman has 2 compute CP rings */
122#define CAYMAN_RING_TYPE_CP1_INDEX 1 123#define CAYMAN_RING_TYPE_CP1_INDEX 1
123#define CAYMAN_RING_TYPE_CP2_INDEX 2 124#define CAYMAN_RING_TYPE_CP2_INDEX 2
124 125
125/* R600+ has an async dma ring */ 126/* R600+ has an async dma ring */
126#define R600_RING_TYPE_DMA_INDEX 3 127#define R600_RING_TYPE_DMA_INDEX 3
127/* cayman add a second async dma ring */ 128/* cayman add a second async dma ring */
128#define CAYMAN_RING_TYPE_DMA1_INDEX 4 129#define CAYMAN_RING_TYPE_DMA1_INDEX 4
129 130
131/* R600+ */
132#define R600_RING_TYPE_UVD_INDEX 5
133
130/* hardcode those limit for now */ 134/* hardcode those limit for now */
131#define RADEON_VA_IB_OFFSET (1 << 20) 135#define RADEON_VA_IB_OFFSET (1 << 20)
132#define RADEON_VA_RESERVED_SIZE (8 << 20) 136#define RADEON_VA_RESERVED_SIZE (8 << 20)
@@ -202,6 +206,11 @@ void radeon_pm_suspend(struct radeon_device *rdev);
202void radeon_pm_resume(struct radeon_device *rdev); 206void radeon_pm_resume(struct radeon_device *rdev);
203void radeon_combios_get_power_modes(struct radeon_device *rdev); 207void radeon_combios_get_power_modes(struct radeon_device *rdev);
204void radeon_atombios_get_power_modes(struct radeon_device *rdev); 208void radeon_atombios_get_power_modes(struct radeon_device *rdev);
209int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
210 u8 clock_type,
211 u32 clock,
212 bool strobe_mode,
213 struct atom_clock_dividers *dividers);
205void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 214void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
206void rs690_pm_info(struct radeon_device *rdev); 215void rs690_pm_info(struct radeon_device *rdev);
207extern int rv6xx_get_temp(struct radeon_device *rdev); 216extern int rv6xx_get_temp(struct radeon_device *rdev);
@@ -357,8 +366,9 @@ struct radeon_bo_list {
357 struct ttm_validate_buffer tv; 366 struct ttm_validate_buffer tv;
358 struct radeon_bo *bo; 367 struct radeon_bo *bo;
359 uint64_t gpu_offset; 368 uint64_t gpu_offset;
360 unsigned rdomain; 369 bool written;
361 unsigned wdomain; 370 unsigned domain;
371 unsigned alt_domain;
362 u32 tiling_flags; 372 u32 tiling_flags;
363}; 373};
364 374
@@ -517,6 +527,7 @@ struct radeon_mc {
517 bool vram_is_ddr; 527 bool vram_is_ddr;
518 bool igp_sideport_enabled; 528 bool igp_sideport_enabled;
519 u64 gtt_base_align; 529 u64 gtt_base_align;
530 u64 mc_mask;
520}; 531};
521 532
522bool radeon_combios_sideport_present(struct radeon_device *rdev); 533bool radeon_combios_sideport_present(struct radeon_device *rdev);
@@ -918,6 +929,7 @@ struct radeon_wb {
918#define R600_WB_DMA_RPTR_OFFSET 1792 929#define R600_WB_DMA_RPTR_OFFSET 1792
919#define R600_WB_IH_WPTR_OFFSET 2048 930#define R600_WB_IH_WPTR_OFFSET 2048
920#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 931#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
932#define R600_WB_UVD_RPTR_OFFSET 2560
921#define R600_WB_EVENT_OFFSET 3072 933#define R600_WB_EVENT_OFFSET 3072
922 934
923/** 935/**
@@ -1118,6 +1130,33 @@ struct radeon_pm {
1118int radeon_pm_get_type_index(struct radeon_device *rdev, 1130int radeon_pm_get_type_index(struct radeon_device *rdev,
1119 enum radeon_pm_state_type ps_type, 1131 enum radeon_pm_state_type ps_type,
1120 int instance); 1132 int instance);
1133/*
1134 * UVD
1135 */
1136#define RADEON_MAX_UVD_HANDLES 10
1137#define RADEON_UVD_STACK_SIZE (1024*1024)
1138#define RADEON_UVD_HEAP_SIZE (1024*1024)
1139
1140struct radeon_uvd {
1141 struct radeon_bo *vcpu_bo;
1142 void *cpu_addr;
1143 uint64_t gpu_addr;
1144 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1145 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1146};
1147
1148int radeon_uvd_init(struct radeon_device *rdev);
1149void radeon_uvd_fini(struct radeon_device *rdev);
1150int radeon_uvd_suspend(struct radeon_device *rdev);
1151int radeon_uvd_resume(struct radeon_device *rdev);
1152int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1153 uint32_t handle, struct radeon_fence **fence);
1154int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1155 uint32_t handle, struct radeon_fence **fence);
1156void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1157void radeon_uvd_free_handles(struct radeon_device *rdev,
1158 struct drm_file *filp);
1159int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1121 1160
1122struct r600_audio { 1161struct r600_audio {
1123 int channels; 1162 int channels;
@@ -1281,6 +1320,7 @@ struct radeon_asic {
1281 int (*get_pcie_lanes)(struct radeon_device *rdev); 1320 int (*get_pcie_lanes)(struct radeon_device *rdev);
1282 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1321 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1283 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1322 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1323 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1284 } pm; 1324 } pm;
1285 /* pageflipping */ 1325 /* pageflipping */
1286 struct { 1326 struct {
@@ -1443,6 +1483,7 @@ struct si_asic {
1443 unsigned multi_gpu_tile_size; 1483 unsigned multi_gpu_tile_size;
1444 1484
1445 unsigned tile_config; 1485 unsigned tile_config;
1486 uint32_t tile_mode_array[32];
1446}; 1487};
1447 1488
1448union radeon_asic_config { 1489union radeon_asic_config {
@@ -1608,6 +1649,7 @@ struct radeon_device {
1608 struct radeon_asic *asic; 1649 struct radeon_asic *asic;
1609 struct radeon_gem gem; 1650 struct radeon_gem gem;
1610 struct radeon_pm pm; 1651 struct radeon_pm pm;
1652 struct radeon_uvd uvd;
1611 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1653 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1612 struct radeon_wb wb; 1654 struct radeon_wb wb;
1613 struct radeon_dummy_page dummy_page; 1655 struct radeon_dummy_page dummy_page;
@@ -1615,12 +1657,14 @@ struct radeon_device {
1615 bool suspend; 1657 bool suspend;
1616 bool need_dma32; 1658 bool need_dma32;
1617 bool accel_working; 1659 bool accel_working;
1660 bool fastfb_working; /* IGP feature*/
1618 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1661 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1619 const struct firmware *me_fw; /* all family ME firmware */ 1662 const struct firmware *me_fw; /* all family ME firmware */
1620 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1663 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1621 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1664 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1622 const struct firmware *mc_fw; /* NI MC firmware */ 1665 const struct firmware *mc_fw; /* NI MC firmware */
1623 const struct firmware *ce_fw; /* SI CE firmware */ 1666 const struct firmware *ce_fw; /* SI CE firmware */
1667 const struct firmware *uvd_fw; /* UVD firmware */
1624 struct r600_blit r600_blit; 1668 struct r600_blit r600_blit;
1625 struct r600_vram_scratch vram_scratch; 1669 struct r600_vram_scratch vram_scratch;
1626 int msi_enabled; /* msi enabled */ 1670 int msi_enabled; /* msi enabled */
@@ -1688,8 +1732,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1688#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1732#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1689#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1733#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1690#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1734#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1691#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1735#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1692#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1736#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1693#define WREG32_P(reg, val, mask) \ 1737#define WREG32_P(reg, val, mask) \
1694 do { \ 1738 do { \
1695 uint32_t tmp_ = RREG32(reg); \ 1739 uint32_t tmp_ = RREG32(reg); \
@@ -1845,6 +1889,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1845#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1889#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1846#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1890#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1847#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1891#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1892#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1848#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1893#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1849#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1894#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1850#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1895#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index aba0a893ea98..48d020057100 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1130,6 +1130,15 @@ static struct radeon_asic rv770_asic = {
1130 .ring_test = &r600_dma_ring_test, 1130 .ring_test = &r600_dma_ring_test,
1131 .ib_test = &r600_dma_ib_test, 1131 .ib_test = &r600_dma_ib_test,
1132 .is_lockup = &r600_dma_is_lockup, 1132 .is_lockup = &r600_dma_is_lockup,
1133 },
1134 [R600_RING_TYPE_UVD_INDEX] = {
1135 .ib_execute = &r600_uvd_ib_execute,
1136 .emit_fence = &r600_uvd_fence_emit,
1137 .emit_semaphore = &r600_uvd_semaphore_emit,
1138 .cs_parse = &radeon_uvd_cs_parse,
1139 .ring_test = &r600_uvd_ring_test,
1140 .ib_test = &r600_uvd_ib_test,
1141 .is_lockup = &radeon_ring_test_lockup,
1133 } 1142 }
1134 }, 1143 },
1135 .irq = { 1144 .irq = {
@@ -1174,6 +1183,7 @@ static struct radeon_asic rv770_asic = {
1174 .get_pcie_lanes = &r600_get_pcie_lanes, 1183 .get_pcie_lanes = &r600_get_pcie_lanes,
1175 .set_pcie_lanes = &r600_set_pcie_lanes, 1184 .set_pcie_lanes = &r600_set_pcie_lanes,
1176 .set_clock_gating = &radeon_atom_set_clock_gating, 1185 .set_clock_gating = &radeon_atom_set_clock_gating,
1186 .set_uvd_clocks = &rv770_set_uvd_clocks,
1177 }, 1187 },
1178 .pflip = { 1188 .pflip = {
1179 .pre_page_flip = &rs600_pre_page_flip, 1189 .pre_page_flip = &rs600_pre_page_flip,
@@ -1216,6 +1226,15 @@ static struct radeon_asic evergreen_asic = {
1216 .ring_test = &r600_dma_ring_test, 1226 .ring_test = &r600_dma_ring_test,
1217 .ib_test = &r600_dma_ib_test, 1227 .ib_test = &r600_dma_ib_test,
1218 .is_lockup = &evergreen_dma_is_lockup, 1228 .is_lockup = &evergreen_dma_is_lockup,
1229 },
1230 [R600_RING_TYPE_UVD_INDEX] = {
1231 .ib_execute = &r600_uvd_ib_execute,
1232 .emit_fence = &r600_uvd_fence_emit,
1233 .emit_semaphore = &r600_uvd_semaphore_emit,
1234 .cs_parse = &radeon_uvd_cs_parse,
1235 .ring_test = &r600_uvd_ring_test,
1236 .ib_test = &r600_uvd_ib_test,
1237 .is_lockup = &radeon_ring_test_lockup,
1219 } 1238 }
1220 }, 1239 },
1221 .irq = { 1240 .irq = {
@@ -1260,6 +1279,7 @@ static struct radeon_asic evergreen_asic = {
1260 .get_pcie_lanes = &r600_get_pcie_lanes, 1279 .get_pcie_lanes = &r600_get_pcie_lanes,
1261 .set_pcie_lanes = &r600_set_pcie_lanes, 1280 .set_pcie_lanes = &r600_set_pcie_lanes,
1262 .set_clock_gating = NULL, 1281 .set_clock_gating = NULL,
1282 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1263 }, 1283 },
1264 .pflip = { 1284 .pflip = {
1265 .pre_page_flip = &evergreen_pre_page_flip, 1285 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1302,6 +1322,15 @@ static struct radeon_asic sumo_asic = {
1302 .ring_test = &r600_dma_ring_test, 1322 .ring_test = &r600_dma_ring_test,
1303 .ib_test = &r600_dma_ib_test, 1323 .ib_test = &r600_dma_ib_test,
1304 .is_lockup = &evergreen_dma_is_lockup, 1324 .is_lockup = &evergreen_dma_is_lockup,
1325 },
1326 [R600_RING_TYPE_UVD_INDEX] = {
1327 .ib_execute = &r600_uvd_ib_execute,
1328 .emit_fence = &r600_uvd_fence_emit,
1329 .emit_semaphore = &r600_uvd_semaphore_emit,
1330 .cs_parse = &radeon_uvd_cs_parse,
1331 .ring_test = &r600_uvd_ring_test,
1332 .ib_test = &r600_uvd_ib_test,
1333 .is_lockup = &radeon_ring_test_lockup,
1305 } 1334 }
1306 }, 1335 },
1307 .irq = { 1336 .irq = {
@@ -1346,6 +1375,7 @@ static struct radeon_asic sumo_asic = {
1346 .get_pcie_lanes = NULL, 1375 .get_pcie_lanes = NULL,
1347 .set_pcie_lanes = NULL, 1376 .set_pcie_lanes = NULL,
1348 .set_clock_gating = NULL, 1377 .set_clock_gating = NULL,
1378 .set_uvd_clocks = &sumo_set_uvd_clocks,
1349 }, 1379 },
1350 .pflip = { 1380 .pflip = {
1351 .pre_page_flip = &evergreen_pre_page_flip, 1381 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1388,6 +1418,15 @@ static struct radeon_asic btc_asic = {
1388 .ring_test = &r600_dma_ring_test, 1418 .ring_test = &r600_dma_ring_test,
1389 .ib_test = &r600_dma_ib_test, 1419 .ib_test = &r600_dma_ib_test,
1390 .is_lockup = &evergreen_dma_is_lockup, 1420 .is_lockup = &evergreen_dma_is_lockup,
1421 },
1422 [R600_RING_TYPE_UVD_INDEX] = {
1423 .ib_execute = &r600_uvd_ib_execute,
1424 .emit_fence = &r600_uvd_fence_emit,
1425 .emit_semaphore = &r600_uvd_semaphore_emit,
1426 .cs_parse = &radeon_uvd_cs_parse,
1427 .ring_test = &r600_uvd_ring_test,
1428 .ib_test = &r600_uvd_ib_test,
1429 .is_lockup = &radeon_ring_test_lockup,
1391 } 1430 }
1392 }, 1431 },
1393 .irq = { 1432 .irq = {
@@ -1429,9 +1468,10 @@ static struct radeon_asic btc_asic = {
1429 .set_engine_clock = &radeon_atom_set_engine_clock, 1468 .set_engine_clock = &radeon_atom_set_engine_clock,
1430 .get_memory_clock = &radeon_atom_get_memory_clock, 1469 .get_memory_clock = &radeon_atom_get_memory_clock,
1431 .set_memory_clock = &radeon_atom_set_memory_clock, 1470 .set_memory_clock = &radeon_atom_set_memory_clock,
1432 .get_pcie_lanes = NULL, 1471 .get_pcie_lanes = &r600_get_pcie_lanes,
1433 .set_pcie_lanes = NULL, 1472 .set_pcie_lanes = &r600_set_pcie_lanes,
1434 .set_clock_gating = NULL, 1473 .set_clock_gating = NULL,
1474 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1435 }, 1475 },
1436 .pflip = { 1476 .pflip = {
1437 .pre_page_flip = &evergreen_pre_page_flip, 1477 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1517,6 +1557,15 @@ static struct radeon_asic cayman_asic = {
1517 .ib_test = &r600_dma_ib_test, 1557 .ib_test = &r600_dma_ib_test,
1518 .is_lockup = &cayman_dma_is_lockup, 1558 .is_lockup = &cayman_dma_is_lockup,
1519 .vm_flush = &cayman_dma_vm_flush, 1559 .vm_flush = &cayman_dma_vm_flush,
1560 },
1561 [R600_RING_TYPE_UVD_INDEX] = {
1562 .ib_execute = &r600_uvd_ib_execute,
1563 .emit_fence = &r600_uvd_fence_emit,
1564 .emit_semaphore = &cayman_uvd_semaphore_emit,
1565 .cs_parse = &radeon_uvd_cs_parse,
1566 .ring_test = &r600_uvd_ring_test,
1567 .ib_test = &r600_uvd_ib_test,
1568 .is_lockup = &radeon_ring_test_lockup,
1520 } 1569 }
1521 }, 1570 },
1522 .irq = { 1571 .irq = {
@@ -1558,9 +1607,10 @@ static struct radeon_asic cayman_asic = {
1558 .set_engine_clock = &radeon_atom_set_engine_clock, 1607 .set_engine_clock = &radeon_atom_set_engine_clock,
1559 .get_memory_clock = &radeon_atom_get_memory_clock, 1608 .get_memory_clock = &radeon_atom_get_memory_clock,
1560 .set_memory_clock = &radeon_atom_set_memory_clock, 1609 .set_memory_clock = &radeon_atom_set_memory_clock,
1561 .get_pcie_lanes = NULL, 1610 .get_pcie_lanes = &r600_get_pcie_lanes,
1562 .set_pcie_lanes = NULL, 1611 .set_pcie_lanes = &r600_set_pcie_lanes,
1563 .set_clock_gating = NULL, 1612 .set_clock_gating = NULL,
1613 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1564 }, 1614 },
1565 .pflip = { 1615 .pflip = {
1566 .pre_page_flip = &evergreen_pre_page_flip, 1616 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1646,6 +1696,15 @@ static struct radeon_asic trinity_asic = {
1646 .ib_test = &r600_dma_ib_test, 1696 .ib_test = &r600_dma_ib_test,
1647 .is_lockup = &cayman_dma_is_lockup, 1697 .is_lockup = &cayman_dma_is_lockup,
1648 .vm_flush = &cayman_dma_vm_flush, 1698 .vm_flush = &cayman_dma_vm_flush,
1699 },
1700 [R600_RING_TYPE_UVD_INDEX] = {
1701 .ib_execute = &r600_uvd_ib_execute,
1702 .emit_fence = &r600_uvd_fence_emit,
1703 .emit_semaphore = &cayman_uvd_semaphore_emit,
1704 .cs_parse = &radeon_uvd_cs_parse,
1705 .ring_test = &r600_uvd_ring_test,
1706 .ib_test = &r600_uvd_ib_test,
1707 .is_lockup = &radeon_ring_test_lockup,
1649 } 1708 }
1650 }, 1709 },
1651 .irq = { 1710 .irq = {
@@ -1690,6 +1749,7 @@ static struct radeon_asic trinity_asic = {
1690 .get_pcie_lanes = NULL, 1749 .get_pcie_lanes = NULL,
1691 .set_pcie_lanes = NULL, 1750 .set_pcie_lanes = NULL,
1692 .set_clock_gating = NULL, 1751 .set_clock_gating = NULL,
1752 .set_uvd_clocks = &sumo_set_uvd_clocks,
1693 }, 1753 },
1694 .pflip = { 1754 .pflip = {
1695 .pre_page_flip = &evergreen_pre_page_flip, 1755 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1775,6 +1835,15 @@ static struct radeon_asic si_asic = {
1775 .ib_test = &r600_dma_ib_test, 1835 .ib_test = &r600_dma_ib_test,
1776 .is_lockup = &si_dma_is_lockup, 1836 .is_lockup = &si_dma_is_lockup,
1777 .vm_flush = &si_dma_vm_flush, 1837 .vm_flush = &si_dma_vm_flush,
1838 },
1839 [R600_RING_TYPE_UVD_INDEX] = {
1840 .ib_execute = &r600_uvd_ib_execute,
1841 .emit_fence = &r600_uvd_fence_emit,
1842 .emit_semaphore = &cayman_uvd_semaphore_emit,
1843 .cs_parse = &radeon_uvd_cs_parse,
1844 .ring_test = &r600_uvd_ring_test,
1845 .ib_test = &r600_uvd_ib_test,
1846 .is_lockup = &radeon_ring_test_lockup,
1778 } 1847 }
1779 }, 1848 },
1780 .irq = { 1849 .irq = {
@@ -1816,9 +1885,10 @@ static struct radeon_asic si_asic = {
1816 .set_engine_clock = &radeon_atom_set_engine_clock, 1885 .set_engine_clock = &radeon_atom_set_engine_clock,
1817 .get_memory_clock = &radeon_atom_get_memory_clock, 1886 .get_memory_clock = &radeon_atom_get_memory_clock,
1818 .set_memory_clock = &radeon_atom_set_memory_clock, 1887 .set_memory_clock = &radeon_atom_set_memory_clock,
1819 .get_pcie_lanes = NULL, 1888 .get_pcie_lanes = &r600_get_pcie_lanes,
1820 .set_pcie_lanes = NULL, 1889 .set_pcie_lanes = &r600_set_pcie_lanes,
1821 .set_clock_gating = NULL, 1890 .set_clock_gating = NULL,
1891 .set_uvd_clocks = &si_set_uvd_clocks,
1822 }, 1892 },
1823 .pflip = { 1893 .pflip = {
1824 .pre_page_flip = &evergreen_pre_page_flip, 1894 .pre_page_flip = &evergreen_pre_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 3535f73ad3e2..2add5268d280 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -330,6 +330,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
330void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 330void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
331int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 331int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
332int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 332int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
333int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
333int r600_copy_blit(struct radeon_device *rdev, 334int r600_copy_blit(struct radeon_device *rdev,
334 uint64_t src_offset, uint64_t dst_offset, 335 uint64_t src_offset, uint64_t dst_offset,
335 unsigned num_gpu_pages, struct radeon_fence **fence); 336 unsigned num_gpu_pages, struct radeon_fence **fence);
@@ -392,6 +393,19 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
392u32 r600_get_xclk(struct radeon_device *rdev); 393u32 r600_get_xclk(struct radeon_device *rdev);
393uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 394uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
394 395
396/* uvd */
397int r600_uvd_init(struct radeon_device *rdev);
398int r600_uvd_rbc_start(struct radeon_device *rdev);
399void r600_uvd_rbc_stop(struct radeon_device *rdev);
400int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
401void r600_uvd_fence_emit(struct radeon_device *rdev,
402 struct radeon_fence *fence);
403void r600_uvd_semaphore_emit(struct radeon_device *rdev,
404 struct radeon_ring *ring,
405 struct radeon_semaphore *semaphore,
406 bool emit_wait);
407void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
408
395/* 409/*
396 * rv770,rv730,rv710,rv740 410 * rv770,rv730,rv710,rv740
397 */ 411 */
@@ -409,6 +423,8 @@ int rv770_copy_dma(struct radeon_device *rdev,
409 unsigned num_gpu_pages, 423 unsigned num_gpu_pages,
410 struct radeon_fence **fence); 424 struct radeon_fence **fence);
411u32 rv770_get_xclk(struct radeon_device *rdev); 425u32 rv770_get_xclk(struct radeon_device *rdev);
426int rv770_uvd_resume(struct radeon_device *rdev);
427int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
412 428
413/* 429/*
414 * evergreen 430 * evergreen
@@ -444,6 +460,8 @@ extern void evergreen_pm_prepare(struct radeon_device *rdev);
444extern void evergreen_pm_finish(struct radeon_device *rdev); 460extern void evergreen_pm_finish(struct radeon_device *rdev);
445extern void sumo_pm_init_profile(struct radeon_device *rdev); 461extern void sumo_pm_init_profile(struct radeon_device *rdev);
446extern void btc_pm_init_profile(struct radeon_device *rdev); 462extern void btc_pm_init_profile(struct radeon_device *rdev);
463int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
464int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
447extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 465extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
448extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 466extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
449extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 467extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
@@ -465,6 +483,10 @@ int evergreen_copy_dma(struct radeon_device *rdev,
465 */ 483 */
466void cayman_fence_ring_emit(struct radeon_device *rdev, 484void cayman_fence_ring_emit(struct radeon_device *rdev,
467 struct radeon_fence *fence); 485 struct radeon_fence *fence);
486void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
487 struct radeon_ring *ring,
488 struct radeon_semaphore *semaphore,
489 bool emit_wait);
468void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 490void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
469int cayman_init(struct radeon_device *rdev); 491int cayman_init(struct radeon_device *rdev);
470void cayman_fini(struct radeon_device *rdev); 492void cayman_fini(struct radeon_device *rdev);
@@ -524,5 +546,6 @@ int si_copy_dma(struct radeon_device *rdev,
524void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 546void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
525u32 si_get_xclk(struct radeon_device *rdev); 547u32 si_get_xclk(struct radeon_device *rdev);
526uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 548uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
549int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
527 550
528#endif 551#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f22eb5713528..8c1779cba1f3 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2654,6 +2654,113 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2654 rdev->pm.current_vddc = 0; 2654 rdev->pm.current_vddc = 0;
2655} 2655}
2656 2656
2657union get_clock_dividers {
2658 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2659 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2660 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2661 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2662 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2663};
2664
2665int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2666 u8 clock_type,
2667 u32 clock,
2668 bool strobe_mode,
2669 struct atom_clock_dividers *dividers)
2670{
2671 union get_clock_dividers args;
2672 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2673 u8 frev, crev;
2674
2675 memset(&args, 0, sizeof(args));
2676 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2677
2678 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2679 return -EINVAL;
2680
2681 switch (crev) {
2682 case 1:
2683 /* r4xx, r5xx */
2684 args.v1.ucAction = clock_type;
2685 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2686
2687 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2688
2689 dividers->post_div = args.v1.ucPostDiv;
2690 dividers->fb_div = args.v1.ucFbDiv;
2691 dividers->enable_post_div = true;
2692 break;
2693 case 2:
2694 case 3:
2695 /* r6xx, r7xx, evergreen, ni */
2696 if (rdev->family <= CHIP_RV770) {
2697 args.v2.ucAction = clock_type;
2698 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2699
2700 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2701
2702 dividers->post_div = args.v2.ucPostDiv;
2703 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2704 dividers->ref_div = args.v2.ucAction;
2705 if (rdev->family == CHIP_RV770) {
2706 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2707 true : false;
2708 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2709 } else
2710 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2711 } else {
2712 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2713 args.v3.ulClock.ulComputeClockFlag = clock_type;
2714 args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2715
2716 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2717
2718 dividers->post_div = args.v3.ucPostDiv;
2719 dividers->enable_post_div = (args.v3.ucCntlFlag &
2720 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2721 dividers->enable_dithen = (args.v3.ucCntlFlag &
2722 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2723 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2724 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2725 dividers->ref_div = args.v3.ucRefDiv;
2726 dividers->vco_mode = (args.v3.ucCntlFlag &
2727 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2728 } else {
2729 args.v5.ulClock.ulComputeClockFlag = clock_type;
2730 args.v5.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2731 if (strobe_mode)
2732 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2733
2734 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2735
2736 dividers->post_div = args.v5.ucPostDiv;
2737 dividers->enable_post_div = (args.v5.ucCntlFlag &
2738 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2739 dividers->enable_dithen = (args.v5.ucCntlFlag &
2740 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2741 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2742 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2743 dividers->ref_div = args.v5.ucRefDiv;
2744 dividers->vco_mode = (args.v5.ucCntlFlag &
2745 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2746 }
2747 }
2748 break;
2749 case 4:
2750 /* fusion */
2751 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2752
2753 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2754
2755 dividers->post_div = args.v4.ucPostDiv;
2756 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2757 break;
2758 default:
2759 return -EINVAL;
2760 }
2761 return 0;
2762}
2763
2657void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2764void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2658{ 2765{
2659 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2766 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 70d38241b083..c7407074c09b 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -63,30 +63,50 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
63 break; 63 break;
64 } 64 }
65 } 65 }
66 if (!duplicate) { 66 if (duplicate) {
67 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
68 p->filp,
69 r->handle);
70 if (p->relocs[i].gobj == NULL) {
71 DRM_ERROR("gem object lookup failed 0x%x\n",
72 r->handle);
73 return -ENOENT;
74 }
75 p->relocs_ptr[i] = &p->relocs[i];
76 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
77 p->relocs[i].lobj.bo = p->relocs[i].robj;
78 p->relocs[i].lobj.wdomain = r->write_domain;
79 p->relocs[i].lobj.rdomain = r->read_domains;
80 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
81 p->relocs[i].handle = r->handle;
82 p->relocs[i].flags = r->flags;
83 radeon_bo_list_add_object(&p->relocs[i].lobj,
84 &p->validated);
85
86 } else
87 p->relocs[i].handle = 0; 67 p->relocs[i].handle = 0;
68 continue;
69 }
70
71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
72 r->handle);
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
75 r->handle);
76 return -ENOENT;
77 }
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.written = !!r->write_domain;
82
83 /* the first reloc of an UVD job is the
84 msg and that must be in VRAM */
85 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
86 /* TODO: is this still needed for NI+ ? */
87 p->relocs[i].lobj.domain =
88 RADEON_GEM_DOMAIN_VRAM;
89
90 p->relocs[i].lobj.alt_domain =
91 RADEON_GEM_DOMAIN_VRAM;
92
93 } else {
94 uint32_t domain = r->write_domain ?
95 r->write_domain : r->read_domains;
96
97 p->relocs[i].lobj.domain = domain;
98 if (domain == RADEON_GEM_DOMAIN_VRAM)
99 domain |= RADEON_GEM_DOMAIN_GTT;
100 p->relocs[i].lobj.alt_domain = domain;
101 }
102
103 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
104 p->relocs[i].handle = r->handle;
105
106 radeon_bo_list_add_object(&p->relocs[i].lobj,
107 &p->validated);
88 } 108 }
89 return radeon_bo_list_validate(&p->validated); 109 return radeon_bo_list_validate(&p->validated, p->ring);
90} 110}
91 111
92static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 112static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
@@ -121,6 +141,9 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
121 return -EINVAL; 141 return -EINVAL;
122 } 142 }
123 break; 143 break;
144 case RADEON_CS_RING_UVD:
145 p->ring = R600_RING_TYPE_UVD_INDEX;
146 break;
124 } 147 }
125 return 0; 148 return 0;
126} 149}
@@ -241,15 +264,15 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
241 return -EINVAL; 264 return -EINVAL;
242 } 265 }
243 266
244 /* we only support VM on SI+ */ 267 if (radeon_cs_get_ring(p, ring, priority))
245 if ((p->rdev->family >= CHIP_TAHITI) &&
246 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
247 DRM_ERROR("VM required on SI+!\n");
248 return -EINVAL; 268 return -EINVAL;
249 }
250 269
251 if (radeon_cs_get_ring(p, ring, priority)) 270 /* we only support VM on some SI+ rings */
271 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
272 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
273 DRM_ERROR("Ring %d requires VM!\n", p->ring);
252 return -EINVAL; 274 return -EINVAL;
275 }
253 } 276 }
254 277
255 /* deal with non-vm */ 278 /* deal with non-vm */
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 44b8034a400d..62d0ba338582 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -359,7 +359,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 359 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
360 360
361 mc->vram_start = base; 361 mc->vram_start = base;
362 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 362 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size; 364 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size; 365 mc->mc_vram_size = mc->aper_size;
@@ -394,7 +394,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
394{ 394{
395 u64 size_af, size_bf; 395 u64 size_af, size_bf;
396 396
397 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 397 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align; 398 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) { 399 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) { 400 if (mc->gtt_size > size_bf) {
@@ -1068,6 +1068,17 @@ int radeon_device_init(struct radeon_device *rdev,
1068 radeon_agp_disable(rdev); 1068 radeon_agp_disable(rdev);
1069 } 1069 }
1070 1070
1071 /* Set the internal MC address mask
1072 * This is the max address of the GPU's
1073 * internal address space.
1074 */
1075 if (rdev->family >= CHIP_CAYMAN)
1076 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1077 else if (rdev->family >= CHIP_CEDAR)
1078 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1079 else
1080 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1081
1071 /* set DMA mask + need_dma32 flags. 1082 /* set DMA mask + need_dma32 flags.
1072 * PCIE - can handle 40-bits. 1083 * PCIE - can handle 40-bits.
1073 * IGP - can handle 40-bits 1084 * IGP - can handle 40-bits
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 66a7f0fd9620..d33f484ace48 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -71,9 +71,12 @@
71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
72 * 2.29.0 - R500 FP16 color clear registers 72 * 2.29.0 - R500 FP16 color clear registers
73 * 2.30.0 - fix for FMASK texturing 73 * 2.30.0 - fix for FMASK texturing
74 * 2.31.0 - Add fastfb support for rs690
75 * 2.32.0 - new info request for rings working
76 * 2.33.0 - Add SI tiling mode array query
74 */ 77 */
75#define KMS_DRIVER_MAJOR 2 78#define KMS_DRIVER_MAJOR 2
76#define KMS_DRIVER_MINOR 30 79#define KMS_DRIVER_MINOR 33
77#define KMS_DRIVER_PATCHLEVEL 0 80#define KMS_DRIVER_PATCHLEVEL 0
78int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 81int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
79int radeon_driver_unload_kms(struct drm_device *dev); 82int radeon_driver_unload_kms(struct drm_device *dev);
@@ -160,6 +163,7 @@ int radeon_hw_i2c = 0;
160int radeon_pcie_gen2 = -1; 163int radeon_pcie_gen2 = -1;
161int radeon_msi = -1; 164int radeon_msi = -1;
162int radeon_lockup_timeout = 10000; 165int radeon_lockup_timeout = 10000;
166int radeon_fastfb = 0;
163 167
164MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 168MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
165module_param_named(no_wb, radeon_no_wb, int, 0444); 169module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -212,6 +216,9 @@ module_param_named(msi, radeon_msi, int, 0444);
212MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 216MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
213module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 217module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
214 218
219MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
220module_param_named(fastfb, radeon_fastfb, int, 0444);
221
215static struct pci_device_id pciidlist[] = { 222static struct pci_device_id pciidlist[] = {
216 radeon_PCI_IDS 223 radeon_PCI_IDS
217}; 224};
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 34356252567a..82fe1835ff8c 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -31,9 +31,9 @@
31#include <linux/seq_file.h> 31#include <linux/seq_file.h>
32#include <linux/atomic.h> 32#include <linux/atomic.h>
33#include <linux/wait.h> 33#include <linux/wait.h>
34#include <linux/list.h>
35#include <linux/kref.h> 34#include <linux/kref.h>
36#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <drm/drmP.h> 37#include <drm/drmP.h>
38#include "radeon_reg.h" 38#include "radeon_reg.h"
39#include "radeon.h" 39#include "radeon.h"
@@ -767,8 +767,21 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
767 767
768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); 768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) { 769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
770 rdev->fence_drv[ring].scratch_reg = 0; 770 if (ring != R600_RING_TYPE_UVD_INDEX) {
771 index = R600_WB_EVENT_OFFSET + ring * 4; 771 rdev->fence_drv[ring].scratch_reg = 0;
772 index = R600_WB_EVENT_OFFSET + ring * 4;
773 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
774 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
775 index;
776
777 } else {
778 /* put fence directly behind firmware */
779 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr +
780 rdev->uvd_fw->size;
781 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr +
782 rdev->uvd_fw->size;
783 }
784
772 } else { 785 } else {
773 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg); 786 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
774 if (r) { 787 if (r) {
@@ -778,9 +791,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
778 index = RADEON_WB_SCRATCH_OFFSET + 791 index = RADEON_WB_SCRATCH_OFFSET +
779 rdev->fence_drv[ring].scratch_reg - 792 rdev->fence_drv[ring].scratch_reg -
780 rdev->scratch.reg_base; 793 rdev->scratch.reg_base;
794 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
795 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
781 } 796 }
782 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
783 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
784 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring); 797 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
785 rdev->fence_drv[ring].initialized = true; 798 rdev->fence_drv[ring].initialized = true;
786 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n", 799 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index c75cb2c6ba71..4f2d4f4c1dab 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -50,9 +50,13 @@ int radeon_driver_unload_kms(struct drm_device *dev)
50 50
51 if (rdev == NULL) 51 if (rdev == NULL)
52 return 0; 52 return 0;
53 if (rdev->rmmio == NULL)
54 goto done_free;
53 radeon_acpi_fini(rdev); 55 radeon_acpi_fini(rdev);
54 radeon_modeset_fini(rdev); 56 radeon_modeset_fini(rdev);
55 radeon_device_fini(rdev); 57 radeon_device_fini(rdev);
58
59done_free:
56 kfree(rdev); 60 kfree(rdev);
57 dev->dev_private = NULL; 61 dev->dev_private = NULL;
58 return 0; 62 return 0;
@@ -176,80 +180,65 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
176 struct radeon_device *rdev = dev->dev_private; 180 struct radeon_device *rdev = dev->dev_private;
177 struct drm_radeon_info *info = data; 181 struct drm_radeon_info *info = data;
178 struct radeon_mode_info *minfo = &rdev->mode_info; 182 struct radeon_mode_info *minfo = &rdev->mode_info;
179 uint32_t value, *value_ptr; 183 uint32_t *value, value_tmp, *value_ptr, value_size;
180 uint64_t value64, *value_ptr64; 184 uint64_t value64;
181 struct drm_crtc *crtc; 185 struct drm_crtc *crtc;
182 int i, found; 186 int i, found;
183 187
184 /* TIMESTAMP is a 64-bit value, needs special handling. */
185 if (info->request == RADEON_INFO_TIMESTAMP) {
186 if (rdev->family >= CHIP_R600) {
187 value_ptr64 = (uint64_t*)((unsigned long)info->value);
188 value64 = radeon_get_gpu_clock_counter(rdev);
189
190 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
191 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
192 return -EFAULT;
193 }
194 return 0;
195 } else {
196 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
197 return -EINVAL;
198 }
199 }
200
201 value_ptr = (uint32_t *)((unsigned long)info->value); 188 value_ptr = (uint32_t *)((unsigned long)info->value);
202 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) { 189 value = &value_tmp;
203 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 190 value_size = sizeof(uint32_t);
204 return -EFAULT;
205 }
206 191
207 switch (info->request) { 192 switch (info->request) {
208 case RADEON_INFO_DEVICE_ID: 193 case RADEON_INFO_DEVICE_ID:
209 value = dev->pci_device; 194 *value = dev->pci_device;
210 break; 195 break;
211 case RADEON_INFO_NUM_GB_PIPES: 196 case RADEON_INFO_NUM_GB_PIPES:
212 value = rdev->num_gb_pipes; 197 *value = rdev->num_gb_pipes;
213 break; 198 break;
214 case RADEON_INFO_NUM_Z_PIPES: 199 case RADEON_INFO_NUM_Z_PIPES:
215 value = rdev->num_z_pipes; 200 *value = rdev->num_z_pipes;
216 break; 201 break;
217 case RADEON_INFO_ACCEL_WORKING: 202 case RADEON_INFO_ACCEL_WORKING:
218 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 203 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
219 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 204 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
220 value = false; 205 *value = false;
221 else 206 else
222 value = rdev->accel_working; 207 *value = rdev->accel_working;
223 break; 208 break;
224 case RADEON_INFO_CRTC_FROM_ID: 209 case RADEON_INFO_CRTC_FROM_ID:
210 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
211 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
212 return -EFAULT;
213 }
225 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 214 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
226 crtc = (struct drm_crtc *)minfo->crtcs[i]; 215 crtc = (struct drm_crtc *)minfo->crtcs[i];
227 if (crtc && crtc->base.id == value) { 216 if (crtc && crtc->base.id == *value) {
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 value = radeon_crtc->crtc_id; 218 *value = radeon_crtc->crtc_id;
230 found = 1; 219 found = 1;
231 break; 220 break;
232 } 221 }
233 } 222 }
234 if (!found) { 223 if (!found) {
235 DRM_DEBUG_KMS("unknown crtc id %d\n", value); 224 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
236 return -EINVAL; 225 return -EINVAL;
237 } 226 }
238 break; 227 break;
239 case RADEON_INFO_ACCEL_WORKING2: 228 case RADEON_INFO_ACCEL_WORKING2:
240 value = rdev->accel_working; 229 *value = rdev->accel_working;
241 break; 230 break;
242 case RADEON_INFO_TILING_CONFIG: 231 case RADEON_INFO_TILING_CONFIG:
243 if (rdev->family >= CHIP_TAHITI) 232 if (rdev->family >= CHIP_TAHITI)
244 value = rdev->config.si.tile_config; 233 *value = rdev->config.si.tile_config;
245 else if (rdev->family >= CHIP_CAYMAN) 234 else if (rdev->family >= CHIP_CAYMAN)
246 value = rdev->config.cayman.tile_config; 235 *value = rdev->config.cayman.tile_config;
247 else if (rdev->family >= CHIP_CEDAR) 236 else if (rdev->family >= CHIP_CEDAR)
248 value = rdev->config.evergreen.tile_config; 237 *value = rdev->config.evergreen.tile_config;
249 else if (rdev->family >= CHIP_RV770) 238 else if (rdev->family >= CHIP_RV770)
250 value = rdev->config.rv770.tile_config; 239 *value = rdev->config.rv770.tile_config;
251 else if (rdev->family >= CHIP_R600) 240 else if (rdev->family >= CHIP_R600)
252 value = rdev->config.r600.tile_config; 241 *value = rdev->config.r600.tile_config;
253 else { 242 else {
254 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 243 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
255 return -EINVAL; 244 return -EINVAL;
@@ -262,73 +251,81 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
262 * 251 *
263 * When returning, the value is 1 if filp owns hyper-z access, 252 * When returning, the value is 1 if filp owns hyper-z access,
264 * 0 otherwise. */ 253 * 0 otherwise. */
265 if (value >= 2) { 254 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
266 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); 255 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
256 return -EFAULT;
257 }
258 if (*value >= 2) {
259 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
267 return -EINVAL; 260 return -EINVAL;
268 } 261 }
269 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); 262 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
270 break; 263 break;
271 case RADEON_INFO_WANT_CMASK: 264 case RADEON_INFO_WANT_CMASK:
272 /* The same logic as Hyper-Z. */ 265 /* The same logic as Hyper-Z. */
273 if (value >= 2) { 266 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
274 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); 267 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
268 return -EFAULT;
269 }
270 if (*value >= 2) {
271 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
275 return -EINVAL; 272 return -EINVAL;
276 } 273 }
277 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); 274 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
278 break; 275 break;
279 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 276 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
280 /* return clock value in KHz */ 277 /* return clock value in KHz */
281 if (rdev->asic->get_xclk) 278 if (rdev->asic->get_xclk)
282 value = radeon_get_xclk(rdev) * 10; 279 *value = radeon_get_xclk(rdev) * 10;
283 else 280 else
284 value = rdev->clock.spll.reference_freq * 10; 281 *value = rdev->clock.spll.reference_freq * 10;
285 break; 282 break;
286 case RADEON_INFO_NUM_BACKENDS: 283 case RADEON_INFO_NUM_BACKENDS:
287 if (rdev->family >= CHIP_TAHITI) 284 if (rdev->family >= CHIP_TAHITI)
288 value = rdev->config.si.max_backends_per_se * 285 *value = rdev->config.si.max_backends_per_se *
289 rdev->config.si.max_shader_engines; 286 rdev->config.si.max_shader_engines;
290 else if (rdev->family >= CHIP_CAYMAN) 287 else if (rdev->family >= CHIP_CAYMAN)
291 value = rdev->config.cayman.max_backends_per_se * 288 *value = rdev->config.cayman.max_backends_per_se *
292 rdev->config.cayman.max_shader_engines; 289 rdev->config.cayman.max_shader_engines;
293 else if (rdev->family >= CHIP_CEDAR) 290 else if (rdev->family >= CHIP_CEDAR)
294 value = rdev->config.evergreen.max_backends; 291 *value = rdev->config.evergreen.max_backends;
295 else if (rdev->family >= CHIP_RV770) 292 else if (rdev->family >= CHIP_RV770)
296 value = rdev->config.rv770.max_backends; 293 *value = rdev->config.rv770.max_backends;
297 else if (rdev->family >= CHIP_R600) 294 else if (rdev->family >= CHIP_R600)
298 value = rdev->config.r600.max_backends; 295 *value = rdev->config.r600.max_backends;
299 else { 296 else {
300 return -EINVAL; 297 return -EINVAL;
301 } 298 }
302 break; 299 break;
303 case RADEON_INFO_NUM_TILE_PIPES: 300 case RADEON_INFO_NUM_TILE_PIPES:
304 if (rdev->family >= CHIP_TAHITI) 301 if (rdev->family >= CHIP_TAHITI)
305 value = rdev->config.si.max_tile_pipes; 302 *value = rdev->config.si.max_tile_pipes;
306 else if (rdev->family >= CHIP_CAYMAN) 303 else if (rdev->family >= CHIP_CAYMAN)
307 value = rdev->config.cayman.max_tile_pipes; 304 *value = rdev->config.cayman.max_tile_pipes;
308 else if (rdev->family >= CHIP_CEDAR) 305 else if (rdev->family >= CHIP_CEDAR)
309 value = rdev->config.evergreen.max_tile_pipes; 306 *value = rdev->config.evergreen.max_tile_pipes;
310 else if (rdev->family >= CHIP_RV770) 307 else if (rdev->family >= CHIP_RV770)
311 value = rdev->config.rv770.max_tile_pipes; 308 *value = rdev->config.rv770.max_tile_pipes;
312 else if (rdev->family >= CHIP_R600) 309 else if (rdev->family >= CHIP_R600)
313 value = rdev->config.r600.max_tile_pipes; 310 *value = rdev->config.r600.max_tile_pipes;
314 else { 311 else {
315 return -EINVAL; 312 return -EINVAL;
316 } 313 }
317 break; 314 break;
318 case RADEON_INFO_FUSION_GART_WORKING: 315 case RADEON_INFO_FUSION_GART_WORKING:
319 value = 1; 316 *value = 1;
320 break; 317 break;
321 case RADEON_INFO_BACKEND_MAP: 318 case RADEON_INFO_BACKEND_MAP:
322 if (rdev->family >= CHIP_TAHITI) 319 if (rdev->family >= CHIP_TAHITI)
323 value = rdev->config.si.backend_map; 320 *value = rdev->config.si.backend_map;
324 else if (rdev->family >= CHIP_CAYMAN) 321 else if (rdev->family >= CHIP_CAYMAN)
325 value = rdev->config.cayman.backend_map; 322 *value = rdev->config.cayman.backend_map;
326 else if (rdev->family >= CHIP_CEDAR) 323 else if (rdev->family >= CHIP_CEDAR)
327 value = rdev->config.evergreen.backend_map; 324 *value = rdev->config.evergreen.backend_map;
328 else if (rdev->family >= CHIP_RV770) 325 else if (rdev->family >= CHIP_RV770)
329 value = rdev->config.rv770.backend_map; 326 *value = rdev->config.rv770.backend_map;
330 else if (rdev->family >= CHIP_R600) 327 else if (rdev->family >= CHIP_R600)
331 value = rdev->config.r600.backend_map; 328 *value = rdev->config.r600.backend_map;
332 else { 329 else {
333 return -EINVAL; 330 return -EINVAL;
334 } 331 }
@@ -337,50 +334,91 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
337 /* this is where we report if vm is supported or not */ 334 /* this is where we report if vm is supported or not */
338 if (rdev->family < CHIP_CAYMAN) 335 if (rdev->family < CHIP_CAYMAN)
339 return -EINVAL; 336 return -EINVAL;
340 value = RADEON_VA_RESERVED_SIZE; 337 *value = RADEON_VA_RESERVED_SIZE;
341 break; 338 break;
342 case RADEON_INFO_IB_VM_MAX_SIZE: 339 case RADEON_INFO_IB_VM_MAX_SIZE:
343 /* this is where we report if vm is supported or not */ 340 /* this is where we report if vm is supported or not */
344 if (rdev->family < CHIP_CAYMAN) 341 if (rdev->family < CHIP_CAYMAN)
345 return -EINVAL; 342 return -EINVAL;
346 value = RADEON_IB_VM_MAX_SIZE; 343 *value = RADEON_IB_VM_MAX_SIZE;
347 break; 344 break;
348 case RADEON_INFO_MAX_PIPES: 345 case RADEON_INFO_MAX_PIPES:
349 if (rdev->family >= CHIP_TAHITI) 346 if (rdev->family >= CHIP_TAHITI)
350 value = rdev->config.si.max_cu_per_sh; 347 *value = rdev->config.si.max_cu_per_sh;
351 else if (rdev->family >= CHIP_CAYMAN) 348 else if (rdev->family >= CHIP_CAYMAN)
352 value = rdev->config.cayman.max_pipes_per_simd; 349 *value = rdev->config.cayman.max_pipes_per_simd;
353 else if (rdev->family >= CHIP_CEDAR) 350 else if (rdev->family >= CHIP_CEDAR)
354 value = rdev->config.evergreen.max_pipes; 351 *value = rdev->config.evergreen.max_pipes;
355 else if (rdev->family >= CHIP_RV770) 352 else if (rdev->family >= CHIP_RV770)
356 value = rdev->config.rv770.max_pipes; 353 *value = rdev->config.rv770.max_pipes;
357 else if (rdev->family >= CHIP_R600) 354 else if (rdev->family >= CHIP_R600)
358 value = rdev->config.r600.max_pipes; 355 *value = rdev->config.r600.max_pipes;
359 else { 356 else {
360 return -EINVAL; 357 return -EINVAL;
361 } 358 }
362 break; 359 break;
360 case RADEON_INFO_TIMESTAMP:
361 if (rdev->family < CHIP_R600) {
362 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
363 return -EINVAL;
364 }
365 value = (uint32_t*)&value64;
366 value_size = sizeof(uint64_t);
367 value64 = radeon_get_gpu_clock_counter(rdev);
368 break;
363 case RADEON_INFO_MAX_SE: 369 case RADEON_INFO_MAX_SE:
364 if (rdev->family >= CHIP_TAHITI) 370 if (rdev->family >= CHIP_TAHITI)
365 value = rdev->config.si.max_shader_engines; 371 *value = rdev->config.si.max_shader_engines;
366 else if (rdev->family >= CHIP_CAYMAN) 372 else if (rdev->family >= CHIP_CAYMAN)
367 value = rdev->config.cayman.max_shader_engines; 373 *value = rdev->config.cayman.max_shader_engines;
368 else if (rdev->family >= CHIP_CEDAR) 374 else if (rdev->family >= CHIP_CEDAR)
369 value = rdev->config.evergreen.num_ses; 375 *value = rdev->config.evergreen.num_ses;
370 else 376 else
371 value = 1; 377 *value = 1;
372 break; 378 break;
373 case RADEON_INFO_MAX_SH_PER_SE: 379 case RADEON_INFO_MAX_SH_PER_SE:
374 if (rdev->family >= CHIP_TAHITI) 380 if (rdev->family >= CHIP_TAHITI)
375 value = rdev->config.si.max_sh_per_se; 381 *value = rdev->config.si.max_sh_per_se;
376 else 382 else
377 return -EINVAL; 383 return -EINVAL;
378 break; 384 break;
385 case RADEON_INFO_FASTFB_WORKING:
386 *value = rdev->fastfb_working;
387 break;
388 case RADEON_INFO_RING_WORKING:
389 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
390 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
391 return -EFAULT;
392 }
393 switch (*value) {
394 case RADEON_CS_RING_GFX:
395 case RADEON_CS_RING_COMPUTE:
396 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
397 break;
398 case RADEON_CS_RING_DMA:
399 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
400 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
401 break;
402 case RADEON_CS_RING_UVD:
403 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
404 break;
405 default:
406 return -EINVAL;
407 }
408 break;
409 case RADEON_INFO_SI_TILE_MODE_ARRAY:
410 if (rdev->family < CHIP_TAHITI) {
411 DRM_DEBUG_KMS("tile mode array is si only!\n");
412 return -EINVAL;
413 }
414 value = rdev->config.si.tile_mode_array;
415 value_size = sizeof(uint32_t)*32;
416 break;
379 default: 417 default:
380 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 418 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
381 return -EINVAL; 419 return -EINVAL;
382 } 420 }
383 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 421 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
384 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 422 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
385 return -EFAULT; 423 return -EFAULT;
386 } 424 }
@@ -513,6 +551,7 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
513 rdev->hyperz_filp = NULL; 551 rdev->hyperz_filp = NULL;
514 if (rdev->cmask_filp == file_priv) 552 if (rdev->cmask_filp == file_priv)
515 rdev->cmask_filp = NULL; 553 rdev->cmask_filp = NULL;
554 radeon_uvd_free_handles(rdev, file_priv);
516} 555}
517 556
518/* 557/*
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 4003f5a68c09..44e579e75fd0 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -492,6 +492,29 @@ struct radeon_framebuffer {
492#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 492#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
493 ((em) == ATOM_ENCODER_MODE_DP_MST)) 493 ((em) == ATOM_ENCODER_MODE_DP_MST))
494 494
495struct atom_clock_dividers {
496 u32 post_div;
497 union {
498 struct {
499#ifdef __BIG_ENDIAN
500 u32 reserved : 6;
501 u32 whole_fb_div : 12;
502 u32 frac_fb_div : 14;
503#else
504 u32 frac_fb_div : 14;
505 u32 whole_fb_div : 12;
506 u32 reserved : 6;
507#endif
508 };
509 u32 fb_div;
510 };
511 u32 ref_div;
512 bool enable_post_div;
513 bool enable_dithen;
514 u32 vco_mode;
515 u32 real_clock;
516};
517
495extern enum radeon_tv_std 518extern enum radeon_tv_std
496radeon_combios_get_tv_info(struct radeon_device *rdev); 519radeon_combios_get_tv_info(struct radeon_device *rdev);
497extern enum radeon_tv_std 520extern enum radeon_tv_std
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d3aface2d12d..1424ccde2377 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -321,8 +321,10 @@ void radeon_bo_force_delete(struct radeon_device *rdev)
321int radeon_bo_init(struct radeon_device *rdev) 321int radeon_bo_init(struct radeon_device *rdev)
322{ 322{
323 /* Add an MTRR for the VRAM */ 323 /* Add an MTRR for the VRAM */
324 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 324 if (!rdev->fastfb_working) {
325 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
325 MTRR_TYPE_WRCOMB, 1); 326 MTRR_TYPE_WRCOMB, 1);
327 }
326 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 328 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
327 rdev->mc.mc_vram_size >> 20, 329 rdev->mc.mc_vram_size >> 20,
328 (unsigned long long)rdev->mc.aper_size >> 20); 330 (unsigned long long)rdev->mc.aper_size >> 20);
@@ -339,14 +341,14 @@ void radeon_bo_fini(struct radeon_device *rdev)
339void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 341void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
340 struct list_head *head) 342 struct list_head *head)
341{ 343{
342 if (lobj->wdomain) { 344 if (lobj->written) {
343 list_add(&lobj->tv.head, head); 345 list_add(&lobj->tv.head, head);
344 } else { 346 } else {
345 list_add_tail(&lobj->tv.head, head); 347 list_add_tail(&lobj->tv.head, head);
346 } 348 }
347} 349}
348 350
349int radeon_bo_list_validate(struct list_head *head) 351int radeon_bo_list_validate(struct list_head *head, int ring)
350{ 352{
351 struct radeon_bo_list *lobj; 353 struct radeon_bo_list *lobj;
352 struct radeon_bo *bo; 354 struct radeon_bo *bo;
@@ -360,15 +362,17 @@ int radeon_bo_list_validate(struct list_head *head)
360 list_for_each_entry(lobj, head, tv.head) { 362 list_for_each_entry(lobj, head, tv.head) {
361 bo = lobj->bo; 363 bo = lobj->bo;
362 if (!bo->pin_count) { 364 if (!bo->pin_count) {
363 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 365 domain = lobj->domain;
364 366
365 retry: 367 retry:
366 radeon_ttm_placement_from_domain(bo, domain); 368 radeon_ttm_placement_from_domain(bo, domain);
369 if (ring == R600_RING_TYPE_UVD_INDEX)
370 radeon_uvd_force_into_uvd_segment(bo);
367 r = ttm_bo_validate(&bo->tbo, &bo->placement, 371 r = ttm_bo_validate(&bo->tbo, &bo->placement,
368 true, false); 372 true, false);
369 if (unlikely(r)) { 373 if (unlikely(r)) {
370 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 374 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
371 domain |= RADEON_GEM_DOMAIN_GTT; 375 domain = lobj->alt_domain;
372 goto retry; 376 goto retry;
373 } 377 }
374 return r; 378 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 5fc86b03043b..e2cb80a96b51 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -128,7 +128,7 @@ extern int radeon_bo_init(struct radeon_device *rdev);
128extern void radeon_bo_fini(struct radeon_device *rdev); 128extern void radeon_bo_fini(struct radeon_device *rdev);
129extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 129extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
130 struct list_head *head); 130 struct list_head *head);
131extern int radeon_bo_list_validate(struct list_head *head); 131extern int radeon_bo_list_validate(struct list_head *head, int ring);
132extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 132extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
133 struct vm_area_struct *vma); 133 struct vm_area_struct *vma);
134extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 134extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 338fd6a74e87..788c64cb4b47 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -843,7 +843,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
843 struct radeon_device *rdev = dev->dev_private; 843 struct radeon_device *rdev = dev->dev_private;
844 844
845 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 845 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
846 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 846 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
847 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
848 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
849 else
850 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
847 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 851 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
848 if (rdev->asic->pm.get_memory_clock) 852 if (rdev->asic->pm.get_memory_clock)
849 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 853 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 8d58e268ff6d..e17faa7cf732 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -180,7 +180,8 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
180 radeon_semaphore_free(rdev, &ib->semaphore, NULL); 180 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
181 } 181 }
182 /* if we can't remember our last VM flush then flush now! */ 182 /* if we can't remember our last VM flush then flush now! */
183 if (ib->vm && !ib->vm->last_flush) { 183 /* XXX figure out why we have to flush for every IB */
184 if (ib->vm /*&& !ib->vm->last_flush*/) {
184 radeon_ring_vm_flush(rdev, ib->ring, ib->vm); 185 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
185 } 186 }
186 if (const_ib) { 187 if (const_ib) {
@@ -368,7 +369,7 @@ void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
368{ 369{
369 u32 rptr; 370 u32 rptr;
370 371
371 if (rdev->wb.enabled) 372 if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
372 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 373 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
373 else 374 else
374 rptr = RREG32(ring->rptr_reg); 375 rptr = RREG32(ring->rptr_reg);
@@ -821,18 +822,20 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
821 return 0; 822 return 0;
822} 823}
823 824
824static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 825static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
825static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 826static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
826static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 827static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
827static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; 828static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
828static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 829static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
830static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
829 831
830static struct drm_info_list radeon_debugfs_ring_info_list[] = { 832static struct drm_info_list radeon_debugfs_ring_info_list[] = {
831 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, 833 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
832 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, 834 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
833 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, 835 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
834 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, 836 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
835 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, 837 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
838 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
836}; 839};
837 840
838static int radeon_debugfs_sa_info(struct seq_file *m, void *data) 841static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index fda09c9ea689..bbed4af8d0bc 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -252,6 +252,36 @@ void radeon_test_moves(struct radeon_device *rdev)
252 radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT); 252 radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
253} 253}
254 254
255static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
256 struct radeon_ring *ring,
257 struct radeon_fence **fence)
258{
259 int r;
260
261 if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
262 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
263 if (r) {
264 DRM_ERROR("Failed to get dummy create msg\n");
265 return r;
266 }
267
268 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence);
269 if (r) {
270 DRM_ERROR("Failed to get dummy destroy msg\n");
271 return r;
272 }
273 } else {
274 r = radeon_ring_lock(rdev, ring, 64);
275 if (r) {
276 DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
277 return r;
278 }
279 radeon_fence_emit(rdev, fence, ring->idx);
280 radeon_ring_unlock_commit(rdev, ring);
281 }
282 return 0;
283}
284
255void radeon_test_ring_sync(struct radeon_device *rdev, 285void radeon_test_ring_sync(struct radeon_device *rdev,
256 struct radeon_ring *ringA, 286 struct radeon_ring *ringA,
257 struct radeon_ring *ringB) 287 struct radeon_ring *ringB)
@@ -272,21 +302,24 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
272 goto out_cleanup; 302 goto out_cleanup;
273 } 303 }
274 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 304 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
275 r = radeon_fence_emit(rdev, &fence1, ringA->idx); 305 radeon_ring_unlock_commit(rdev, ringA);
276 if (r) { 306
277 DRM_ERROR("Failed to emit fence 1\n"); 307 r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
278 radeon_ring_unlock_undo(rdev, ringA); 308 if (r)
279 goto out_cleanup; 309 goto out_cleanup;
280 } 310
281 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 311 r = radeon_ring_lock(rdev, ringA, 64);
282 r = radeon_fence_emit(rdev, &fence2, ringA->idx);
283 if (r) { 312 if (r) {
284 DRM_ERROR("Failed to emit fence 2\n"); 313 DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
285 radeon_ring_unlock_undo(rdev, ringA);
286 goto out_cleanup; 314 goto out_cleanup;
287 } 315 }
316 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
288 radeon_ring_unlock_commit(rdev, ringA); 317 radeon_ring_unlock_commit(rdev, ringA);
289 318
319 r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
320 if (r)
321 goto out_cleanup;
322
290 mdelay(1000); 323 mdelay(1000);
291 324
292 if (radeon_fence_signaled(fence1)) { 325 if (radeon_fence_signaled(fence1)) {
@@ -364,27 +397,22 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
364 goto out_cleanup; 397 goto out_cleanup;
365 } 398 }
366 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 399 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
367 r = radeon_fence_emit(rdev, &fenceA, ringA->idx);
368 if (r) {
369 DRM_ERROR("Failed to emit sync fence 1\n");
370 radeon_ring_unlock_undo(rdev, ringA);
371 goto out_cleanup;
372 }
373 radeon_ring_unlock_commit(rdev, ringA); 400 radeon_ring_unlock_commit(rdev, ringA);
374 401
402 r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
403 if (r)
404 goto out_cleanup;
405
375 r = radeon_ring_lock(rdev, ringB, 64); 406 r = radeon_ring_lock(rdev, ringB, 64);
376 if (r) { 407 if (r) {
377 DRM_ERROR("Failed to lock ring B %d\n", ringB->idx); 408 DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
378 goto out_cleanup; 409 goto out_cleanup;
379 } 410 }
380 radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); 411 radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
381 r = radeon_fence_emit(rdev, &fenceB, ringB->idx);
382 if (r) {
383 DRM_ERROR("Failed to create sync fence 2\n");
384 radeon_ring_unlock_undo(rdev, ringB);
385 goto out_cleanup;
386 }
387 radeon_ring_unlock_commit(rdev, ringB); 412 radeon_ring_unlock_commit(rdev, ringB);
413 r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
414 if (r)
415 goto out_cleanup;
388 416
389 mdelay(1000); 417 mdelay(1000);
390 418
@@ -393,7 +421,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
393 goto out_cleanup; 421 goto out_cleanup;
394 } 422 }
395 if (radeon_fence_signaled(fenceB)) { 423 if (radeon_fence_signaled(fenceB)) {
396 DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); 424 DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
397 goto out_cleanup; 425 goto out_cleanup;
398 } 426 }
399 427
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
new file mode 100644
index 000000000000..30a94609672a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -0,0 +1,666 @@
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "radeon.h"
37#include "r600d.h"
38
39/* Firmware Names */
40#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
41#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
42#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
43#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
44
45MODULE_FIRMWARE(FIRMWARE_RV710);
46MODULE_FIRMWARE(FIRMWARE_CYPRESS);
47MODULE_FIRMWARE(FIRMWARE_SUMO);
48MODULE_FIRMWARE(FIRMWARE_TAHITI);
49
50int radeon_uvd_init(struct radeon_device *rdev)
51{
52 struct platform_device *pdev;
53 unsigned long bo_size;
54 const char *fw_name;
55 int i, r;
56
57 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0);
58 r = IS_ERR(pdev);
59 if (r) {
60 dev_err(rdev->dev, "radeon_uvd: Failed to register firmware\n");
61 return -EINVAL;
62 }
63
64 switch (rdev->family) {
65 case CHIP_RV710:
66 case CHIP_RV730:
67 case CHIP_RV740:
68 fw_name = FIRMWARE_RV710;
69 break;
70
71 case CHIP_CYPRESS:
72 case CHIP_HEMLOCK:
73 case CHIP_JUNIPER:
74 case CHIP_REDWOOD:
75 case CHIP_CEDAR:
76 fw_name = FIRMWARE_CYPRESS;
77 break;
78
79 case CHIP_SUMO:
80 case CHIP_SUMO2:
81 case CHIP_PALM:
82 case CHIP_CAYMAN:
83 case CHIP_BARTS:
84 case CHIP_TURKS:
85 case CHIP_CAICOS:
86 fw_name = FIRMWARE_SUMO;
87 break;
88
89 case CHIP_TAHITI:
90 case CHIP_VERDE:
91 case CHIP_PITCAIRN:
92 case CHIP_ARUBA:
93 fw_name = FIRMWARE_TAHITI;
94 break;
95
96 default:
97 return -EINVAL;
98 }
99
100 r = request_firmware(&rdev->uvd_fw, fw_name, &pdev->dev);
101 if (r) {
102 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
103 fw_name);
104 platform_device_unregister(pdev);
105 return r;
106 }
107
108 platform_device_unregister(pdev);
109
110 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) +
111 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
112 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
113 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
114 if (r) {
115 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
116 return r;
117 }
118
119 r = radeon_uvd_resume(rdev);
120 if (r)
121 return r;
122
123 memset(rdev->uvd.cpu_addr, 0, bo_size);
124 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
125
126 r = radeon_uvd_suspend(rdev);
127 if (r)
128 return r;
129
130 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
131 atomic_set(&rdev->uvd.handles[i], 0);
132 rdev->uvd.filp[i] = NULL;
133 }
134
135 return 0;
136}
137
138void radeon_uvd_fini(struct radeon_device *rdev)
139{
140 radeon_uvd_suspend(rdev);
141 radeon_bo_unref(&rdev->uvd.vcpu_bo);
142}
143
144int radeon_uvd_suspend(struct radeon_device *rdev)
145{
146 int r;
147
148 if (rdev->uvd.vcpu_bo == NULL)
149 return 0;
150
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
152 if (!r) {
153 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
154 radeon_bo_unpin(rdev->uvd.vcpu_bo);
155 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
156 }
157 return r;
158}
159
160int radeon_uvd_resume(struct radeon_device *rdev)
161{
162 int r;
163
164 if (rdev->uvd.vcpu_bo == NULL)
165 return -EINVAL;
166
167 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
168 if (r) {
169 radeon_bo_unref(&rdev->uvd.vcpu_bo);
170 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
171 return r;
172 }
173
174 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
175 &rdev->uvd.gpu_addr);
176 if (r) {
177 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
178 radeon_bo_unref(&rdev->uvd.vcpu_bo);
179 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
180 return r;
181 }
182
183 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
184 if (r) {
185 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
186 return r;
187 }
188
189 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
190
191 radeon_set_uvd_clocks(rdev, 53300, 40000);
192
193 return 0;
194}
195
196void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
197{
198 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
199 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
200}
201
202void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
203{
204 int i, r;
205 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
206 if (rdev->uvd.filp[i] == filp) {
207 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
208 struct radeon_fence *fence;
209
210 r = radeon_uvd_get_destroy_msg(rdev,
211 R600_RING_TYPE_UVD_INDEX, handle, &fence);
212 if (r) {
213 DRM_ERROR("Error destroying UVD (%d)!\n", r);
214 continue;
215 }
216
217 radeon_fence_wait(fence, false);
218 radeon_fence_unref(&fence);
219
220 rdev->uvd.filp[i] = NULL;
221 atomic_set(&rdev->uvd.handles[i], 0);
222 }
223 }
224}
225
226static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
227{
228 unsigned stream_type = msg[4];
229 unsigned width = msg[6];
230 unsigned height = msg[7];
231 unsigned dpb_size = msg[9];
232 unsigned pitch = msg[28];
233
234 unsigned width_in_mb = width / 16;
235 unsigned height_in_mb = ALIGN(height / 16, 2);
236
237 unsigned image_size, tmp, min_dpb_size;
238
239 image_size = width * height;
240 image_size += image_size / 2;
241 image_size = ALIGN(image_size, 1024);
242
243 switch (stream_type) {
244 case 0: /* H264 */
245
246 /* reference picture buffer */
247 min_dpb_size = image_size * 17;
248
249 /* macroblock context buffer */
250 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
251
252 /* IT surface buffer */
253 min_dpb_size += width_in_mb * height_in_mb * 32;
254 break;
255
256 case 1: /* VC1 */
257
258 /* reference picture buffer */
259 min_dpb_size = image_size * 3;
260
261 /* CONTEXT_BUFFER */
262 min_dpb_size += width_in_mb * height_in_mb * 128;
263
264 /* IT surface buffer */
265 min_dpb_size += width_in_mb * 64;
266
267 /* DB surface buffer */
268 min_dpb_size += width_in_mb * 128;
269
270 /* BP */
271 tmp = max(width_in_mb, height_in_mb);
272 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
273 break;
274
275 case 3: /* MPEG2 */
276
277 /* reference picture buffer */
278 min_dpb_size = image_size * 3;
279 break;
280
281 case 4: /* MPEG4 */
282
283 /* reference picture buffer */
284 min_dpb_size = image_size * 3;
285
286 /* CM */
287 min_dpb_size += width_in_mb * height_in_mb * 64;
288
289 /* IT surface buffer */
290 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
291 break;
292
293 default:
294 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
295 return -EINVAL;
296 }
297
298 if (width > pitch) {
299 DRM_ERROR("Invalid UVD decoding target pitch!\n");
300 return -EINVAL;
301 }
302
303 if (dpb_size < min_dpb_size) {
304 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
305 dpb_size, min_dpb_size);
306 return -EINVAL;
307 }
308
309 buf_sizes[0x1] = dpb_size;
310 buf_sizes[0x2] = image_size;
311 return 0;
312}
313
314static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
315 unsigned offset, unsigned buf_sizes[])
316{
317 int32_t *msg, msg_type, handle;
318 void *ptr;
319
320 int i, r;
321
322 if (offset & 0x3F) {
323 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
324 return -EINVAL;
325 }
326
327 r = radeon_bo_kmap(bo, &ptr);
328 if (r)
329 return r;
330
331 msg = ptr + offset;
332
333 msg_type = msg[1];
334 handle = msg[2];
335
336 if (handle == 0) {
337 DRM_ERROR("Invalid UVD handle!\n");
338 return -EINVAL;
339 }
340
341 if (msg_type == 1) {
342 /* it's a decode msg, calc buffer sizes */
343 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
344 radeon_bo_kunmap(bo);
345 if (r)
346 return r;
347
348 } else if (msg_type == 2) {
349 /* it's a destroy msg, free the handle */
350 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
351 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
352 radeon_bo_kunmap(bo);
353 return 0;
354 } else {
355 /* it's a create msg, no special handling needed */
356 radeon_bo_kunmap(bo);
357 }
358
359 /* create or decode, validate the handle */
360 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
361 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
362 return 0;
363 }
364
365 /* handle not found try to alloc a new one */
366 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
367 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
368 p->rdev->uvd.filp[i] = p->filp;
369 return 0;
370 }
371 }
372
373 DRM_ERROR("No more free UVD handles!\n");
374 return -EINVAL;
375}
376
377static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
378 int data0, int data1,
379 unsigned buf_sizes[])
380{
381 struct radeon_cs_chunk *relocs_chunk;
382 struct radeon_cs_reloc *reloc;
383 unsigned idx, cmd, offset;
384 uint64_t start, end;
385 int r;
386
387 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
388 offset = radeon_get_ib_value(p, data0);
389 idx = radeon_get_ib_value(p, data1);
390 if (idx >= relocs_chunk->length_dw) {
391 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
392 idx, relocs_chunk->length_dw);
393 return -EINVAL;
394 }
395
396 reloc = p->relocs_ptr[(idx / 4)];
397 start = reloc->lobj.gpu_offset;
398 end = start + radeon_bo_size(reloc->robj);
399 start += offset;
400
401 p->ib.ptr[data0] = start & 0xFFFFFFFF;
402 p->ib.ptr[data1] = start >> 32;
403
404 cmd = radeon_get_ib_value(p, p->idx) >> 1;
405
406 if (cmd < 0x4) {
407 if ((end - start) < buf_sizes[cmd]) {
408 DRM_ERROR("buffer to small (%d / %d)!\n",
409 (unsigned)(end - start), buf_sizes[cmd]);
410 return -EINVAL;
411 }
412
413 } else if (cmd != 0x100) {
414 DRM_ERROR("invalid UVD command %X!\n", cmd);
415 return -EINVAL;
416 }
417
418 if (cmd == 0) {
419 if (end & 0xFFFFFFFFF0000000) {
420 DRM_ERROR("msg buffer %LX-%LX out of 256MB segment!\n",
421 start, end);
422 return -EINVAL;
423 }
424
425 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
426 if (r)
427 return r;
428 }
429
430 if ((start & 0xFFFFFFFFF0000000) != (end & 0xFFFFFFFFF0000000)) {
431 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
432 start, end);
433 return -EINVAL;
434 }
435
436 return 0;
437}
438
439static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
440 struct radeon_cs_packet *pkt,
441 int *data0, int *data1,
442 unsigned buf_sizes[])
443{
444 int i, r;
445
446 p->idx++;
447 for (i = 0; i <= pkt->count; ++i) {
448 switch (pkt->reg + i*4) {
449 case UVD_GPCOM_VCPU_DATA0:
450 *data0 = p->idx;
451 break;
452 case UVD_GPCOM_VCPU_DATA1:
453 *data1 = p->idx;
454 break;
455 case UVD_GPCOM_VCPU_CMD:
456 r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
457 if (r)
458 return r;
459 break;
460 case UVD_ENGINE_CNTL:
461 break;
462 default:
463 DRM_ERROR("Invalid reg 0x%X!\n",
464 pkt->reg + i*4);
465 return -EINVAL;
466 }
467 p->idx++;
468 }
469 return 0;
470}
471
472int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
473{
474 struct radeon_cs_packet pkt;
475 int r, data0 = 0, data1 = 0;
476
477 /* minimum buffer sizes */
478 unsigned buf_sizes[] = {
479 [0x00000000] = 2048,
480 [0x00000001] = 32 * 1024 * 1024,
481 [0x00000002] = 2048 * 1152 * 3,
482 [0x00000003] = 2048,
483 };
484
485 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
486 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
487 p->chunks[p->chunk_ib_idx].length_dw);
488 return -EINVAL;
489 }
490
491 if (p->chunk_relocs_idx == -1) {
492 DRM_ERROR("No relocation chunk !\n");
493 return -EINVAL;
494 }
495
496
497 do {
498 r = radeon_cs_packet_parse(p, &pkt, p->idx);
499 if (r)
500 return r;
501 switch (pkt.type) {
502 case RADEON_PACKET_TYPE0:
503 r = radeon_uvd_cs_reg(p, &pkt, &data0,
504 &data1, buf_sizes);
505 if (r)
506 return r;
507 break;
508 case RADEON_PACKET_TYPE2:
509 p->idx += pkt.count + 2;
510 break;
511 default:
512 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
513 return -EINVAL;
514 }
515 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
516 return 0;
517}
518
519static int radeon_uvd_send_msg(struct radeon_device *rdev,
520 int ring, struct radeon_bo *bo,
521 struct radeon_fence **fence)
522{
523 struct ttm_validate_buffer tv;
524 struct list_head head;
525 struct radeon_ib ib;
526 uint64_t addr;
527 int i, r;
528
529 memset(&tv, 0, sizeof(tv));
530 tv.bo = &bo->tbo;
531
532 INIT_LIST_HEAD(&head);
533 list_add(&tv.head, &head);
534
535 r = ttm_eu_reserve_buffers(&head);
536 if (r)
537 return r;
538
539 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
540 radeon_uvd_force_into_uvd_segment(bo);
541
542 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
543 if (r) {
544 ttm_eu_backoff_reservation(&head);
545 return r;
546 }
547
548 r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
549 if (r) {
550 ttm_eu_backoff_reservation(&head);
551 return r;
552 }
553
554 addr = radeon_bo_gpu_offset(bo);
555 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
556 ib.ptr[1] = addr;
557 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
558 ib.ptr[3] = addr >> 32;
559 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
560 ib.ptr[5] = 0;
561 for (i = 6; i < 16; ++i)
562 ib.ptr[i] = PACKET2(0);
563 ib.length_dw = 16;
564
565 r = radeon_ib_schedule(rdev, &ib, NULL);
566 if (r) {
567 ttm_eu_backoff_reservation(&head);
568 return r;
569 }
570 ttm_eu_fence_buffer_objects(&head, ib.fence);
571
572 if (fence)
573 *fence = radeon_fence_ref(ib.fence);
574
575 radeon_ib_free(rdev, &ib);
576 radeon_bo_unref(&bo);
577 return 0;
578}
579
580/* multiple fence commands without any stream commands in between can
581 crash the vcpu so just try to emmit a dummy create/destroy msg to
582 avoid this */
583int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
584 uint32_t handle, struct radeon_fence **fence)
585{
586 struct radeon_bo *bo;
587 uint32_t *msg;
588 int r, i;
589
590 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
591 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
592 if (r)
593 return r;
594
595 r = radeon_bo_reserve(bo, false);
596 if (r) {
597 radeon_bo_unref(&bo);
598 return r;
599 }
600
601 r = radeon_bo_kmap(bo, (void **)&msg);
602 if (r) {
603 radeon_bo_unreserve(bo);
604 radeon_bo_unref(&bo);
605 return r;
606 }
607
608 /* stitch together an UVD create msg */
609 msg[0] = 0x00000de4;
610 msg[1] = 0x00000000;
611 msg[2] = handle;
612 msg[3] = 0x00000000;
613 msg[4] = 0x00000000;
614 msg[5] = 0x00000000;
615 msg[6] = 0x00000000;
616 msg[7] = 0x00000780;
617 msg[8] = 0x00000440;
618 msg[9] = 0x00000000;
619 msg[10] = 0x01b37000;
620 for (i = 11; i < 1024; ++i)
621 msg[i] = 0x0;
622
623 radeon_bo_kunmap(bo);
624 radeon_bo_unreserve(bo);
625
626 return radeon_uvd_send_msg(rdev, ring, bo, fence);
627}
628
629int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
630 uint32_t handle, struct radeon_fence **fence)
631{
632 struct radeon_bo *bo;
633 uint32_t *msg;
634 int r, i;
635
636 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
637 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
638 if (r)
639 return r;
640
641 r = radeon_bo_reserve(bo, false);
642 if (r) {
643 radeon_bo_unref(&bo);
644 return r;
645 }
646
647 r = radeon_bo_kmap(bo, (void **)&msg);
648 if (r) {
649 radeon_bo_unreserve(bo);
650 radeon_bo_unref(&bo);
651 return r;
652 }
653
654 /* stitch together an UVD destroy msg */
655 msg[0] = 0x00000de4;
656 msg[1] = 0x00000002;
657 msg[2] = handle;
658 msg[3] = 0x00000000;
659 for (i = 4; i < 1024; ++i)
660 msg[i] = 0x0;
661
662 radeon_bo_kunmap(bo);
663 radeon_bo_unreserve(bo);
664
665 return radeon_uvd_send_msg(rdev, ring, bo, fence);
666}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 5706d2ac75ab..ab4c86cfd552 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -148,6 +148,8 @@ void rs690_pm_info(struct radeon_device *rdev)
148static void rs690_mc_init(struct radeon_device *rdev) 148static void rs690_mc_init(struct radeon_device *rdev)
149{ 149{
150 u64 base; 150 u64 base;
151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
151 153
152 rs400_gart_adjust_size(rdev); 154 rs400_gart_adjust_size(rdev);
153 rdev->mc.vram_is_ddr = true; 155 rdev->mc.vram_is_ddr = true;
@@ -160,6 +162,27 @@ static void rs690_mc_init(struct radeon_device *rdev)
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 163 base = G_000100_MC_FB_START(base) << 16;
162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
165
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
173#endif
174 {
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
176 * memory is present.
177 */
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
183 }
184 }
185
163 rs690_pm_info(rdev); 186 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 187 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h
index 36e6398a98ae..8af3ccf20cc0 100644
--- a/drivers/gpu/drm/radeon/rs690d.h
+++ b/drivers/gpu/drm/radeon/rs690d.h
@@ -29,6 +29,9 @@
29#define __RS690D_H__ 29#define __RS690D_H__
30 30
31/* Registers */ 31/* Registers */
32#define R_00001E_K8_FB_LOCATION 0x00001E
33#define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34#define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
32#define R_000078_MC_INDEX 0x000078 35#define R_000078_MC_INDEX 0x000078
33#define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) 36#define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
34#define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) 37#define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 435ed3551364..5e1ba16c7a77 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -348,7 +348,7 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
348 /* update crtc base addresses */ 348 /* update crtc base addresses */
349 for (i = 0; i < rdev->num_crtc; i++) { 349 for (i = 0; i < rdev->num_crtc; i++) {
350 if (rdev->family >= CHIP_RV770) { 350 if (rdev->family >= CHIP_RV770) {
351 if (i == 1) { 351 if (i == 0) {
352 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 352 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
353 upper_32_bits(rdev->mc.vram_start)); 353 upper_32_bits(rdev->mc.vram_start));
354 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 354 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index d63fe1d0f53f..777f537a32c7 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -42,6 +42,162 @@
42static void rv770_gpu_init(struct radeon_device *rdev); 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev); 43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46
47static int rv770_uvd_calc_post_div(unsigned target_freq,
48 unsigned vco_freq,
49 unsigned *div)
50{
51 /* Fclk = Fvco / PDIV */
52 *div = vco_freq / target_freq;
53
54 /* we alway need a frequency less than or equal the target */
55 if ((vco_freq / *div) > target_freq)
56 *div += 1;
57
58 /* out of range ? */
59 if (*div > 30)
60 return -1; /* forget it */
61
62 *div -= 1;
63 return vco_freq / (*div + 1);
64}
65
66static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev)
67{
68 unsigned i;
69
70 /* assert UPLL_CTLREQ */
71 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
72
73 /* wait for CTLACK and CTLACK2 to get asserted */
74 for (i = 0; i < 100; ++i) {
75 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
76 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
77 break;
78 mdelay(10);
79 }
80 if (i == 100)
81 return -ETIMEDOUT;
82
83 /* deassert UPLL_CTLREQ */
84 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
85
86 return 0;
87}
88
89int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
90{
91 /* start off with something large */
92 int optimal_diff_score = 0x7FFFFFF;
93 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
94 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
95 unsigned vco_freq, vco_min = 50000, vco_max = 160000;
96 unsigned ref_freq = rdev->clock.spll.reference_freq;
97 int r;
98
99 /* RV740 uses evergreen uvd clk programming */
100 if (rdev->family == CHIP_RV740)
101 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
102
103 /* loop through vco from low to high */
104 vco_min = max(max(vco_min, vclk), dclk);
105 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
106 uint64_t fb_div = (uint64_t)vco_freq * 43663;
107 int calc_clk, diff_score, diff_vclk, diff_dclk;
108 unsigned vclk_div, dclk_div;
109
110 do_div(fb_div, ref_freq);
111 fb_div |= 1;
112
113 /* fb div out of range ? */
114 if (fb_div > 0x03FFFFFF)
115 break; /* it can oly get worse */
116
117 /* calc vclk with current vco freq. */
118 calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
119 if (calc_clk == -1)
120 break; /* vco is too big, it has to stop. */
121 diff_vclk = vclk - calc_clk;
122
123 /* calc dclk with current vco freq. */
124 calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
125 if (calc_clk == -1)
126 break; /* vco is too big, it has to stop. */
127 diff_dclk = dclk - calc_clk;
128
129 /* determine if this vco setting is better than current optimal settings */
130 diff_score = abs(diff_vclk) + abs(diff_dclk);
131 if (diff_score < optimal_diff_score) {
132 optimal_fb_div = fb_div;
133 optimal_vclk_div = vclk_div;
134 optimal_dclk_div = dclk_div;
135 optimal_vco_freq = vco_freq;
136 optimal_diff_score = diff_score;
137 if (optimal_diff_score == 0)
138 break; /* it can't get better than this */
139 }
140 }
141
142 /* bypass vclk and dclk with bclk */
143 WREG32_P(CG_UPLL_FUNC_CNTL_2,
144 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
145 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
146
147 /* set UPLL_FB_DIV to 0x50000 */
148 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
149
150 /* deassert UPLL_RESET */
151 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
152
153 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
154 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
155 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
156
157 r = rv770_uvd_send_upll_ctlreq(rdev);
158 if (r)
159 return r;
160
161 /* assert PLL_RESET */
162 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
163
164 /* set the required FB_DIV, REF_DIV, Post divder values */
165 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
166 WREG32_P(CG_UPLL_FUNC_CNTL_2,
167 UPLL_SW_HILEN(optimal_vclk_div >> 1) |
168 UPLL_SW_LOLEN((optimal_vclk_div >> 1) + (optimal_vclk_div & 1)) |
169 UPLL_SW_HILEN2(optimal_dclk_div >> 1) |
170 UPLL_SW_LOLEN2((optimal_dclk_div >> 1) + (optimal_dclk_div & 1)),
171 ~UPLL_SW_MASK);
172
173 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div),
174 ~UPLL_FB_DIV_MASK);
175
176 /* give the PLL some time to settle */
177 mdelay(15);
178
179 /* deassert PLL_RESET */
180 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
181
182 mdelay(15);
183
184 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
185 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
186 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
187
188 r = rv770_uvd_send_upll_ctlreq(rdev);
189 if (r)
190 return r;
191
192 /* switch VCLK and DCLK selection */
193 WREG32_P(CG_UPLL_FUNC_CNTL_2,
194 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
195 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
196
197 mdelay(100);
198
199 return 0;
200}
45 201
46#define PCIE_BUS_CLK 10000 202#define PCIE_BUS_CLK 10000
47#define TCLK (PCIE_BUS_CLK / 10) 203#define TCLK (PCIE_BUS_CLK / 10)
@@ -68,6 +224,105 @@ u32 rv770_get_xclk(struct radeon_device *rdev)
68 return reference_clock; 224 return reference_clock;
69} 225}
70 226
227int rv770_uvd_resume(struct radeon_device *rdev)
228{
229 uint64_t addr;
230 uint32_t chip_id, size;
231 int r;
232
233 r = radeon_uvd_resume(rdev);
234 if (r)
235 return r;
236
237 /* programm the VCPU memory controller bits 0-27 */
238 addr = rdev->uvd.gpu_addr >> 3;
239 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
240 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
241 WREG32(UVD_VCPU_CACHE_SIZE0, size);
242
243 addr += size;
244 size = RADEON_UVD_STACK_SIZE >> 3;
245 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
246 WREG32(UVD_VCPU_CACHE_SIZE1, size);
247
248 addr += size;
249 size = RADEON_UVD_HEAP_SIZE >> 3;
250 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
251 WREG32(UVD_VCPU_CACHE_SIZE2, size);
252
253 /* bits 28-31 */
254 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
255 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
256
257 /* bits 32-39 */
258 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
259 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
260
261 /* tell firmware which hardware it is running on */
262 switch (rdev->family) {
263 default:
264 return -EINVAL;
265 case CHIP_RV710:
266 chip_id = 0x01000005;
267 break;
268 case CHIP_RV730:
269 chip_id = 0x01000006;
270 break;
271 case CHIP_RV740:
272 chip_id = 0x01000007;
273 break;
274 case CHIP_CYPRESS:
275 case CHIP_HEMLOCK:
276 chip_id = 0x01000008;
277 break;
278 case CHIP_JUNIPER:
279 chip_id = 0x01000009;
280 break;
281 case CHIP_REDWOOD:
282 chip_id = 0x0100000a;
283 break;
284 case CHIP_CEDAR:
285 chip_id = 0x0100000b;
286 break;
287 case CHIP_SUMO:
288 chip_id = 0x0100000c;
289 break;
290 case CHIP_SUMO2:
291 chip_id = 0x0100000d;
292 break;
293 case CHIP_PALM:
294 chip_id = 0x0100000e;
295 break;
296 case CHIP_CAYMAN:
297 chip_id = 0x0100000f;
298 break;
299 case CHIP_BARTS:
300 chip_id = 0x01000010;
301 break;
302 case CHIP_TURKS:
303 chip_id = 0x01000011;
304 break;
305 case CHIP_CAICOS:
306 chip_id = 0x01000012;
307 break;
308 case CHIP_TAHITI:
309 chip_id = 0x01000014;
310 break;
311 case CHIP_VERDE:
312 chip_id = 0x01000015;
313 break;
314 case CHIP_PITCAIRN:
315 chip_id = 0x01000016;
316 break;
317 case CHIP_ARUBA:
318 chip_id = 0x01000017;
319 break;
320 }
321 WREG32(UVD_VCPU_CHIP_ID, chip_id);
322
323 return 0;
324}
325
71u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 326u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
72{ 327{
73 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 328 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
@@ -611,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
611 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 866 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
612 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 867 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
613 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 868 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
869 if (rdev->family == CHIP_RV730) {
870 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
871 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
872 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
873 }
614 874
615 WREG32(CGTS_SYS_TCC_DISABLE, 0); 875 WREG32(CGTS_SYS_TCC_DISABLE, 0);
616 WREG32(CGTS_TCC_DISABLE, 0); 876 WREG32(CGTS_TCC_DISABLE, 0);
@@ -840,7 +1100,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
840 } 1100 }
841 if (rdev->flags & RADEON_IS_AGP) { 1101 if (rdev->flags & RADEON_IS_AGP) {
842 size_bf = mc->gtt_start; 1102 size_bf = mc->gtt_start;
843 size_af = 0xFFFFFFFF - mc->gtt_end; 1103 size_af = mc->mc_mask - mc->gtt_end;
844 if (size_bf > size_af) { 1104 if (size_bf > size_af) {
845 if (mc->mc_vram_size > size_bf) { 1105 if (mc->mc_vram_size > size_bf) {
846 dev_warn(rdev->dev, "limiting VRAM\n"); 1106 dev_warn(rdev->dev, "limiting VRAM\n");
@@ -1040,6 +1300,17 @@ static int rv770_startup(struct radeon_device *rdev)
1040 return r; 1300 return r;
1041 } 1301 }
1042 1302
1303 r = rv770_uvd_resume(rdev);
1304 if (!r) {
1305 r = radeon_fence_driver_start_ring(rdev,
1306 R600_RING_TYPE_UVD_INDEX);
1307 if (r)
1308 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1309 }
1310
1311 if (r)
1312 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1313
1043 /* Enable IRQ */ 1314 /* Enable IRQ */
1044 r = r600_irq_init(rdev); 1315 r = r600_irq_init(rdev);
1045 if (r) { 1316 if (r) {
@@ -1074,6 +1345,19 @@ static int rv770_startup(struct radeon_device *rdev)
1074 if (r) 1345 if (r)
1075 return r; 1346 return r;
1076 1347
1348 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1349 if (ring->ring_size) {
1350 r = radeon_ring_init(rdev, ring, ring->ring_size,
1351 R600_WB_UVD_RPTR_OFFSET,
1352 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1353 0, 0xfffff, RADEON_CP_PACKET2);
1354 if (!r)
1355 r = r600_uvd_init(rdev);
1356
1357 if (r)
1358 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1359 }
1360
1077 r = radeon_ib_pool_init(rdev); 1361 r = radeon_ib_pool_init(rdev);
1078 if (r) { 1362 if (r) {
1079 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1363 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -1115,6 +1399,7 @@ int rv770_resume(struct radeon_device *rdev)
1115int rv770_suspend(struct radeon_device *rdev) 1399int rv770_suspend(struct radeon_device *rdev)
1116{ 1400{
1117 r600_audio_fini(rdev); 1401 r600_audio_fini(rdev);
1402 radeon_uvd_suspend(rdev);
1118 r700_cp_stop(rdev); 1403 r700_cp_stop(rdev);
1119 r600_dma_stop(rdev); 1404 r600_dma_stop(rdev);
1120 r600_irq_suspend(rdev); 1405 r600_irq_suspend(rdev);
@@ -1190,6 +1475,13 @@ int rv770_init(struct radeon_device *rdev)
1190 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 1475 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1191 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 1476 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1192 1477
1478 r = radeon_uvd_init(rdev);
1479 if (!r) {
1480 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1481 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
1482 4096);
1483 }
1484
1193 rdev->ih.ring_obj = NULL; 1485 rdev->ih.ring_obj = NULL;
1194 r600_ih_ring_init(rdev, 64 * 1024); 1486 r600_ih_ring_init(rdev, 64 * 1024);
1195 1487
@@ -1224,6 +1516,7 @@ void rv770_fini(struct radeon_device *rdev)
1224 radeon_ib_pool_fini(rdev); 1516 radeon_ib_pool_fini(rdev);
1225 radeon_irq_kms_fini(rdev); 1517 radeon_irq_kms_fini(rdev);
1226 rv770_pcie_gart_fini(rdev); 1518 rv770_pcie_gart_fini(rdev);
1519 radeon_uvd_fini(rdev);
1227 r600_vram_scratch_fini(rdev); 1520 r600_vram_scratch_fini(rdev);
1228 radeon_gem_fini(rdev); 1521 radeon_gem_fini(rdev);
1229 radeon_fence_driver_fini(rdev); 1522 radeon_fence_driver_fini(rdev);
@@ -1264,23 +1557,23 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1264 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 1557 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1265 1558
1266 /* advertise upconfig capability */ 1559 /* advertise upconfig capability */
1267 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1560 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1268 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1561 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1269 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1562 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1270 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1563 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1271 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 1564 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1272 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 1565 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1273 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 1566 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1274 LC_RECONFIG_ARC_MISSING_ESCAPE); 1567 LC_RECONFIG_ARC_MISSING_ESCAPE);
1275 link_width_cntl |= lanes | LC_RECONFIG_NOW | 1568 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1276 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 1569 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1277 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1570 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1278 } else { 1571 } else {
1279 link_width_cntl |= LC_UPCONFIGURE_DIS; 1572 link_width_cntl |= LC_UPCONFIGURE_DIS;
1280 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1573 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1281 } 1574 }
1282 1575
1283 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1576 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1284 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 1577 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1285 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 1578 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1286 1579
@@ -1293,29 +1586,29 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1293 WREG16(0x4088, link_cntl2); 1586 WREG16(0x4088, link_cntl2);
1294 WREG32(MM_CFGREGS_CNTL, 0); 1587 WREG32(MM_CFGREGS_CNTL, 0);
1295 1588
1296 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1589 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1297 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 1590 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1298 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1591 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1299 1592
1300 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1593 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1301 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 1594 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1302 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1595 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1303 1596
1304 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1597 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1305 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 1598 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1306 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1599 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1307 1600
1308 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1601 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1309 speed_cntl |= LC_GEN2_EN_STRAP; 1602 speed_cntl |= LC_GEN2_EN_STRAP;
1310 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1603 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1311 1604
1312 } else { 1605 } else {
1313 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1606 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1314 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 1607 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1315 if (1) 1608 if (1)
1316 link_width_cntl |= LC_UPCONFIGURE_DIS; 1609 link_width_cntl |= LC_UPCONFIGURE_DIS;
1317 else 1610 else
1318 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1611 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1319 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1612 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1320 } 1613 }
1321} 1614}
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index c55f950a4af7..6a52b2054f32 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -38,6 +38,30 @@
38#define R7XX_MAX_PIPES 8 38#define R7XX_MAX_PIPES 8
39#define R7XX_MAX_PIPES_MASK 0xff 39#define R7XX_MAX_PIPES_MASK 0xff
40 40
41/* discrete uvd clocks */
42#define CG_UPLL_FUNC_CNTL 0x718
43# define UPLL_RESET_MASK 0x00000001
44# define UPLL_SLEEP_MASK 0x00000002
45# define UPLL_BYPASS_EN_MASK 0x00000004
46# define UPLL_CTLREQ_MASK 0x00000008
47# define UPLL_REF_DIV(x) ((x) << 16)
48# define UPLL_REF_DIV_MASK 0x001F0000
49# define UPLL_CTLACK_MASK 0x40000000
50# define UPLL_CTLACK2_MASK 0x80000000
51#define CG_UPLL_FUNC_CNTL_2 0x71c
52# define UPLL_SW_HILEN(x) ((x) << 0)
53# define UPLL_SW_LOLEN(x) ((x) << 4)
54# define UPLL_SW_HILEN2(x) ((x) << 8)
55# define UPLL_SW_LOLEN2(x) ((x) << 12)
56# define UPLL_SW_MASK 0x0000FFFF
57# define VCLK_SRC_SEL(x) ((x) << 20)
58# define VCLK_SRC_SEL_MASK 0x01F00000
59# define DCLK_SRC_SEL(x) ((x) << 25)
60# define DCLK_SRC_SEL_MASK 0x3E000000
61#define CG_UPLL_FUNC_CNTL_3 0x720
62# define UPLL_FB_DIV(x) ((x) << 0)
63# define UPLL_FB_DIV_MASK 0x01FFFFFF
64
41/* Registers */ 65/* Registers */
42#define CB_COLOR0_BASE 0x28040 66#define CB_COLOR0_BASE 0x28040
43#define CB_COLOR1_BASE 0x28044 67#define CB_COLOR1_BASE 0x28044
@@ -112,6 +136,11 @@
112#define DMA_TILING_CONFIG 0x3ec8 136#define DMA_TILING_CONFIG 0x3ec8
113#define DMA_TILING_CONFIG2 0xd0b8 137#define DMA_TILING_CONFIG2 0xd0b8
114 138
139/* RV730 only */
140#define UVD_UDEC_TILING_CONFIG 0xef40
141#define UVD_UDEC_DB_TILING_CONFIG 0xef44
142#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
143
115#define GC_USER_SHADER_PIPE_CONFIG 0x8954 144#define GC_USER_SHADER_PIPE_CONFIG 0x8954
116#define INACTIVE_QD_PIPES(x) ((x) << 8) 145#define INACTIVE_QD_PIPES(x) ((x) << 8)
117#define INACTIVE_QD_PIPES_MASK 0x0000FF00 146#define INACTIVE_QD_PIPES_MASK 0x0000FF00
@@ -671,4 +700,18 @@
671# define TARGET_LINK_SPEED_MASK (0xf << 0) 700# define TARGET_LINK_SPEED_MASK (0xf << 0)
672# define SELECTABLE_DEEMPHASIS (1 << 6) 701# define SELECTABLE_DEEMPHASIS (1 << 6)
673 702
703/* UVD */
704#define UVD_LMI_EXT40_ADDR 0xf498
705#define UVD_VCPU_CHIP_ID 0xf4d4
706#define UVD_VCPU_CACHE_OFFSET0 0xf4d8
707#define UVD_VCPU_CACHE_SIZE0 0xf4dc
708#define UVD_VCPU_CACHE_OFFSET1 0xf4e0
709#define UVD_VCPU_CACHE_SIZE1 0xf4e4
710#define UVD_VCPU_CACHE_OFFSET2 0xf4e8
711#define UVD_VCPU_CACHE_SIZE2 0xf4ec
712#define UVD_LMI_ADDR_EXT 0xf594
713
714#define UVD_RBC_RB_RPTR 0xf690
715#define UVD_RBC_RB_WPTR 0xf694
716
674#endif 717#endif
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index bafbe3216952..aa2c555ba877 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1211,6 +1211,7 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1211 gb_tile_moden = 0; 1211 gb_tile_moden = 0;
1212 break; 1212 break;
1213 } 1213 }
1214 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
1214 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1215 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1215 } 1216 }
1216 } else if ((rdev->family == CHIP_VERDE) || 1217 } else if ((rdev->family == CHIP_VERDE) ||
@@ -1451,6 +1452,7 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1451 gb_tile_moden = 0; 1452 gb_tile_moden = 0;
1452 break; 1453 break;
1453 } 1454 }
1455 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
1454 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1456 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1455 } 1457 }
1456 } else 1458 } else
@@ -1765,9 +1767,13 @@ static void si_gpu_init(struct radeon_device *rdev)
1765 1767
1766 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1768 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1767 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1769 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1770 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1768 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1771 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1769 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1772 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1770 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1773 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1774 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1775 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1776 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1771 1777
1772 si_tiling_mode_table_init(rdev); 1778 si_tiling_mode_table_init(rdev);
1773 1779
@@ -2538,46 +2544,6 @@ static void si_mc_program(struct radeon_device *rdev)
2538 rv515_vga_render_disable(rdev); 2544 rv515_vga_render_disable(rdev);
2539} 2545}
2540 2546
2541/* SI MC address space is 40 bits */
2542static void si_vram_location(struct radeon_device *rdev,
2543 struct radeon_mc *mc, u64 base)
2544{
2545 mc->vram_start = base;
2546 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2547 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2548 mc->real_vram_size = mc->aper_size;
2549 mc->mc_vram_size = mc->aper_size;
2550 }
2551 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2552 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2553 mc->mc_vram_size >> 20, mc->vram_start,
2554 mc->vram_end, mc->real_vram_size >> 20);
2555}
2556
2557static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2558{
2559 u64 size_af, size_bf;
2560
2561 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2562 size_bf = mc->vram_start & ~mc->gtt_base_align;
2563 if (size_bf > size_af) {
2564 if (mc->gtt_size > size_bf) {
2565 dev_warn(rdev->dev, "limiting GTT\n");
2566 mc->gtt_size = size_bf;
2567 }
2568 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2569 } else {
2570 if (mc->gtt_size > size_af) {
2571 dev_warn(rdev->dev, "limiting GTT\n");
2572 mc->gtt_size = size_af;
2573 }
2574 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2575 }
2576 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2577 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2578 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2579}
2580
2581static void si_vram_gtt_location(struct radeon_device *rdev, 2547static void si_vram_gtt_location(struct radeon_device *rdev,
2582 struct radeon_mc *mc) 2548 struct radeon_mc *mc)
2583{ 2549{
@@ -2587,9 +2553,9 @@ static void si_vram_gtt_location(struct radeon_device *rdev,
2587 mc->real_vram_size = 0xFFC0000000ULL; 2553 mc->real_vram_size = 0xFFC0000000ULL;
2588 mc->mc_vram_size = 0xFFC0000000ULL; 2554 mc->mc_vram_size = 0xFFC0000000ULL;
2589 } 2555 }
2590 si_vram_location(rdev, &rdev->mc, 0); 2556 radeon_vram_location(rdev, &rdev->mc, 0);
2591 rdev->mc.gtt_base_align = 0; 2557 rdev->mc.gtt_base_align = 0;
2592 si_gtt_location(rdev, mc); 2558 radeon_gtt_location(rdev, mc);
2593} 2559}
2594 2560
2595static int si_mc_init(struct radeon_device *rdev) 2561static int si_mc_init(struct radeon_device *rdev)
@@ -4322,14 +4288,6 @@ static int si_startup(struct radeon_device *rdev)
4322 return r; 4288 return r;
4323 si_gpu_init(rdev); 4289 si_gpu_init(rdev);
4324 4290
4325#if 0
4326 r = evergreen_blit_init(rdev);
4327 if (r) {
4328 r600_blit_fini(rdev);
4329 rdev->asic->copy = NULL;
4330 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4331 }
4332#endif
4333 /* allocate rlc buffers */ 4291 /* allocate rlc buffers */
4334 r = si_rlc_init(rdev); 4292 r = si_rlc_init(rdev);
4335 if (r) { 4293 if (r) {
@@ -4372,6 +4330,16 @@ static int si_startup(struct radeon_device *rdev)
4372 return r; 4330 return r;
4373 } 4331 }
4374 4332
4333 r = rv770_uvd_resume(rdev);
4334 if (!r) {
4335 r = radeon_fence_driver_start_ring(rdev,
4336 R600_RING_TYPE_UVD_INDEX);
4337 if (r)
4338 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
4339 }
4340 if (r)
4341 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4342
4375 /* Enable IRQ */ 4343 /* Enable IRQ */
4376 r = si_irq_init(rdev); 4344 r = si_irq_init(rdev);
4377 if (r) { 4345 if (r) {
@@ -4429,6 +4397,18 @@ static int si_startup(struct radeon_device *rdev)
4429 if (r) 4397 if (r)
4430 return r; 4398 return r;
4431 4399
4400 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4401 if (ring->ring_size) {
4402 r = radeon_ring_init(rdev, ring, ring->ring_size,
4403 R600_WB_UVD_RPTR_OFFSET,
4404 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
4405 0, 0xfffff, RADEON_CP_PACKET2);
4406 if (!r)
4407 r = r600_uvd_init(rdev);
4408 if (r)
4409 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
4410 }
4411
4432 r = radeon_ib_pool_init(rdev); 4412 r = radeon_ib_pool_init(rdev);
4433 if (r) { 4413 if (r) {
4434 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4414 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -4472,6 +4452,8 @@ int si_suspend(struct radeon_device *rdev)
4472 radeon_vm_manager_fini(rdev); 4452 radeon_vm_manager_fini(rdev);
4473 si_cp_enable(rdev, false); 4453 si_cp_enable(rdev, false);
4474 cayman_dma_stop(rdev); 4454 cayman_dma_stop(rdev);
4455 r600_uvd_rbc_stop(rdev);
4456 radeon_uvd_suspend(rdev);
4475 si_irq_suspend(rdev); 4457 si_irq_suspend(rdev);
4476 radeon_wb_disable(rdev); 4458 radeon_wb_disable(rdev);
4477 si_pcie_gart_disable(rdev); 4459 si_pcie_gart_disable(rdev);
@@ -4557,6 +4539,13 @@ int si_init(struct radeon_device *rdev)
4557 ring->ring_obj = NULL; 4539 ring->ring_obj = NULL;
4558 r600_ring_init(rdev, ring, 64 * 1024); 4540 r600_ring_init(rdev, ring, 64 * 1024);
4559 4541
4542 r = radeon_uvd_init(rdev);
4543 if (!r) {
4544 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4545 ring->ring_obj = NULL;
4546 r600_ring_init(rdev, ring, 4096);
4547 }
4548
4560 rdev->ih.ring_obj = NULL; 4549 rdev->ih.ring_obj = NULL;
4561 r600_ih_ring_init(rdev, 64 * 1024); 4550 r600_ih_ring_init(rdev, 64 * 1024);
4562 4551
@@ -4594,9 +4583,6 @@ int si_init(struct radeon_device *rdev)
4594 4583
4595void si_fini(struct radeon_device *rdev) 4584void si_fini(struct radeon_device *rdev)
4596{ 4585{
4597#if 0
4598 r600_blit_fini(rdev);
4599#endif
4600 si_cp_fini(rdev); 4586 si_cp_fini(rdev);
4601 cayman_dma_fini(rdev); 4587 cayman_dma_fini(rdev);
4602 si_irq_fini(rdev); 4588 si_irq_fini(rdev);
@@ -4605,6 +4591,7 @@ void si_fini(struct radeon_device *rdev)
4605 radeon_vm_manager_fini(rdev); 4591 radeon_vm_manager_fini(rdev);
4606 radeon_ib_pool_fini(rdev); 4592 radeon_ib_pool_fini(rdev);
4607 radeon_irq_kms_fini(rdev); 4593 radeon_irq_kms_fini(rdev);
4594 radeon_uvd_fini(rdev);
4608 si_pcie_gart_fini(rdev); 4595 si_pcie_gart_fini(rdev);
4609 r600_vram_scratch_fini(rdev); 4596 r600_vram_scratch_fini(rdev);
4610 radeon_gem_fini(rdev); 4597 radeon_gem_fini(rdev);
@@ -4634,3 +4621,170 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
4634 mutex_unlock(&rdev->gpu_clock_mutex); 4621 mutex_unlock(&rdev->gpu_clock_mutex);
4635 return clock; 4622 return clock;
4636} 4623}
4624
4625static int si_uvd_calc_post_div(unsigned target_freq,
4626 unsigned vco_freq,
4627 unsigned *div)
4628{
4629 /* target larger than vco frequency ? */
4630 if (vco_freq < target_freq)
4631 return -1; /* forget it */
4632
4633 /* Fclk = Fvco / PDIV */
4634 *div = vco_freq / target_freq;
4635
4636 /* we alway need a frequency less than or equal the target */
4637 if ((vco_freq / *div) > target_freq)
4638 *div += 1;
4639
4640 /* dividers above 5 must be even */
4641 if (*div > 5 && *div % 2)
4642 *div += 1;
4643
4644 /* out of range ? */
4645 if (*div >= 128)
4646 return -1; /* forget it */
4647
4648 return vco_freq / *div;
4649}
4650
4651static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev)
4652{
4653 unsigned i;
4654
4655 /* assert UPLL_CTLREQ */
4656 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
4657
4658 /* wait for CTLACK and CTLACK2 to get asserted */
4659 for (i = 0; i < 100; ++i) {
4660 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
4661 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
4662 break;
4663 mdelay(10);
4664 }
4665 if (i == 100)
4666 return -ETIMEDOUT;
4667
4668 /* deassert UPLL_CTLREQ */
4669 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
4670
4671 return 0;
4672}
4673
4674int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
4675{
4676 /* start off with something large */
4677 int optimal_diff_score = 0x7FFFFFF;
4678 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
4679 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
4680 unsigned vco_freq;
4681 int r;
4682
4683 /* loop through vco from low to high */
4684 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
4685 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
4686 int calc_clk, diff_score, diff_vclk, diff_dclk;
4687 unsigned vclk_div, dclk_div;
4688
4689 /* fb div out of range ? */
4690 if (fb_div > 0x03FFFFFF)
4691 break; /* it can oly get worse */
4692
4693 /* calc vclk with current vco freq. */
4694 calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
4695 if (calc_clk == -1)
4696 break; /* vco is too big, it has to stop. */
4697 diff_vclk = vclk - calc_clk;
4698
4699 /* calc dclk with current vco freq. */
4700 calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
4701 if (calc_clk == -1)
4702 break; /* vco is too big, it has to stop. */
4703 diff_dclk = dclk - calc_clk;
4704
4705 /* determine if this vco setting is better than current optimal settings */
4706 diff_score = abs(diff_vclk) + abs(diff_dclk);
4707 if (diff_score < optimal_diff_score) {
4708 optimal_fb_div = fb_div;
4709 optimal_vclk_div = vclk_div;
4710 optimal_dclk_div = dclk_div;
4711 optimal_vco_freq = vco_freq;
4712 optimal_diff_score = diff_score;
4713 if (optimal_diff_score == 0)
4714 break; /* it can't get better than this */
4715 }
4716 }
4717
4718 /* set RESET_ANTI_MUX to 0 */
4719 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
4720
4721 /* set VCO_MODE to 1 */
4722 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
4723
4724 /* toggle UPLL_SLEEP to 1 then back to 0 */
4725 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
4726 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
4727
4728 /* deassert UPLL_RESET */
4729 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
4730
4731 mdelay(1);
4732
4733 /* bypass vclk and dclk with bclk */
4734 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4735 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
4736 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
4737
4738 /* put PLL in bypass mode */
4739 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
4740
4741 r = si_uvd_send_upll_ctlreq(rdev);
4742 if (r)
4743 return r;
4744
4745 /* assert UPLL_RESET again */
4746 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
4747
4748 /* disable spread spectrum. */
4749 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
4750
4751 /* set feedback divider */
4752 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
4753
4754 /* set ref divider to 0 */
4755 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
4756
4757 if (optimal_vco_freq < 187500)
4758 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
4759 else
4760 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
4761
4762 /* set PDIV_A and PDIV_B */
4763 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4764 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
4765 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
4766
4767 /* give the PLL some time to settle */
4768 mdelay(15);
4769
4770 /* deassert PLL_RESET */
4771 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
4772
4773 mdelay(15);
4774
4775 /* switch from bypass mode to normal mode */
4776 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
4777
4778 r = si_uvd_send_upll_ctlreq(rdev);
4779 if (r)
4780 return r;
4781
4782 /* switch VCLK and DCLK selection */
4783 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4784 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
4785 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
4786
4787 mdelay(100);
4788
4789 return 0;
4790}
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 23fc08fc8e7f..042b91d6c941 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -29,6 +29,35 @@
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 31
32/* discrete uvd clocks */
33#define CG_UPLL_FUNC_CNTL 0x634
34# define UPLL_RESET_MASK 0x00000001
35# define UPLL_SLEEP_MASK 0x00000002
36# define UPLL_BYPASS_EN_MASK 0x00000004
37# define UPLL_CTLREQ_MASK 0x00000008
38# define UPLL_VCO_MODE_MASK 0x00000600
39# define UPLL_REF_DIV_MASK 0x001F0000
40# define UPLL_CTLACK_MASK 0x40000000
41# define UPLL_CTLACK2_MASK 0x80000000
42#define CG_UPLL_FUNC_CNTL_2 0x638
43# define UPLL_PDIV_A(x) ((x) << 0)
44# define UPLL_PDIV_A_MASK 0x0000007F
45# define UPLL_PDIV_B(x) ((x) << 8)
46# define UPLL_PDIV_B_MASK 0x00007F00
47# define VCLK_SRC_SEL(x) ((x) << 20)
48# define VCLK_SRC_SEL_MASK 0x01F00000
49# define DCLK_SRC_SEL(x) ((x) << 25)
50# define DCLK_SRC_SEL_MASK 0x3E000000
51#define CG_UPLL_FUNC_CNTL_3 0x63C
52# define UPLL_FB_DIV(x) ((x) << 0)
53# define UPLL_FB_DIV_MASK 0x01FFFFFF
54#define CG_UPLL_FUNC_CNTL_4 0x644
55# define UPLL_SPARE_ISPARE9 0x00020000
56#define CG_UPLL_FUNC_CNTL_5 0x648
57# define RESET_ANTI_MUX_MASK 0x00000200
58#define CG_UPLL_SPREAD_SPECTRUM 0x650
59# define SSEN_MASK 0x00000001
60
32#define CG_MULT_THERMAL_STATUS 0x714 61#define CG_MULT_THERMAL_STATUS 0x714
33#define ASIC_MAX_TEMP(x) ((x) << 0) 62#define ASIC_MAX_TEMP(x) ((x) << 0)
34#define ASIC_MAX_TEMP_MASK 0x000001ff 63#define ASIC_MAX_TEMP_MASK 0x000001ff
@@ -65,6 +94,8 @@
65 94
66#define DMIF_ADDR_CONFIG 0xBD4 95#define DMIF_ADDR_CONFIG 0xBD4
67 96
97#define DMIF_ADDR_CALC 0xC00
98
68#define SRBM_STATUS 0xE50 99#define SRBM_STATUS 0xE50
69#define GRBM_RQ_PENDING (1 << 5) 100#define GRBM_RQ_PENDING (1 << 5)
70#define VMC_BUSY (1 << 8) 101#define VMC_BUSY (1 << 8)
@@ -798,6 +829,15 @@
798# define THREAD_TRACE_FINISH (55 << 0) 829# define THREAD_TRACE_FINISH (55 << 0)
799 830
800/* 831/*
832 * UVD
833 */
834#define UVD_UDEC_ADDR_CONFIG 0xEF4C
835#define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
836#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
837#define UVD_RBC_RB_RPTR 0xF690
838#define UVD_RBC_RB_WPTR 0xF694
839
840/*
801 * PM4 841 * PM4
802 */ 842 */
803#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 843#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index eeda91774c8a..321d4ac5c512 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -918,6 +918,7 @@ struct drm_radeon_gem_va {
918#define RADEON_CS_RING_GFX 0 918#define RADEON_CS_RING_GFX 0
919#define RADEON_CS_RING_COMPUTE 1 919#define RADEON_CS_RING_COMPUTE 1
920#define RADEON_CS_RING_DMA 2 920#define RADEON_CS_RING_DMA 2
921#define RADEON_CS_RING_UVD 3
921/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 922/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
922/* 0 = normal, + = higher priority, - = lower priority */ 923/* 0 = normal, + = higher priority, - = lower priority */
923 924
@@ -972,6 +973,13 @@ struct drm_radeon_cs {
972#define RADEON_INFO_MAX_SE 0x12 973#define RADEON_INFO_MAX_SE 0x12
973/* max SH per SE */ 974/* max SH per SE */
974#define RADEON_INFO_MAX_SH_PER_SE 0x13 975#define RADEON_INFO_MAX_SH_PER_SE 0x13
976/* fast fb access is enabled */
977#define RADEON_INFO_FASTFB_WORKING 0x14
978/* query if a RADEON_CS_RING_* submission is supported */
979#define RADEON_INFO_RING_WORKING 0x15
980/* SI tile mode array */
981#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
982
975 983
976struct drm_radeon_info { 984struct drm_radeon_info {
977 uint32_t request; 985 uint32_t request;
@@ -979,4 +987,22 @@ struct drm_radeon_info {
979 uint64_t value; 987 uint64_t value;
980}; 988};
981 989
990/* Those correspond to the tile index to use, this is to explicitly state
991 * the API that is implicitly defined by the tile mode array.
992 */
993#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
994#define SI_TILE_MODE_COLOR_1D 13
995#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
996#define SI_TILE_MODE_COLOR_2D_8BPP 14
997#define SI_TILE_MODE_COLOR_2D_16BPP 15
998#define SI_TILE_MODE_COLOR_2D_32BPP 16
999#define SI_TILE_MODE_COLOR_2D_64BPP 17
1000#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
1001#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
1002#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
1003#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
1004#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
1005#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
1006#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
1007
982#endif 1008#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-10 08:47:26 -0400