diff options
author | Eric Miao <eric.miao@marvell.com> | 2008-11-28 01:54:39 -0500 |
---|---|---|
committer | Eric Miao <eric.miao@marvell.com> | 2008-12-02 01:42:39 -0500 |
commit | f1647e4c068139b5f6c988b0862eb1d233dfffe2 (patch) | |
tree | 46cce8492e42e2351a23c90aaf8d07bd03eda287 | |
parent | 1f017a9964c5b3b9581d3a5732110cb1e0444281 (diff) |
[ARM] pxa: move GPIOx_BASE and GPIO register offsets to gpio.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
-rw-r--r-- | arch/arm/mach-pxa/gpio.c | 12 | ||||
-rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa-regs.h | 28 |
2 files changed, 12 insertions, 28 deletions
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 843144ff1f61..5fec1e479cb3 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c | |||
@@ -25,6 +25,18 @@ | |||
25 | 25 | ||
26 | #include "generic.h" | 26 | #include "generic.h" |
27 | 27 | ||
28 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
29 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
30 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
31 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
32 | |||
33 | #define GPLR_OFFSET 0x00 | ||
34 | #define GPDR_OFFSET 0x0C | ||
35 | #define GPSR_OFFSET 0x18 | ||
36 | #define GPCR_OFFSET 0x24 | ||
37 | #define GRER_OFFSET 0x30 | ||
38 | #define GFER_OFFSET 0x3C | ||
39 | #define GEDR_OFFSET 0x48 | ||
28 | 40 | ||
29 | struct pxa_gpio_chip { | 41 | struct pxa_gpio_chip { |
30 | struct gpio_chip chip; | 42 | struct gpio_chip chip; |
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index a56502898030..782ad4ab8055 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h | |||
@@ -203,19 +203,6 @@ | |||
203 | * General Purpose I/O | 203 | * General Purpose I/O |
204 | */ | 204 | */ |
205 | 205 | ||
206 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
207 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
208 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
209 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
210 | |||
211 | #define GPLR_OFFSET 0x00 | ||
212 | #define GPDR_OFFSET 0x0C | ||
213 | #define GPSR_OFFSET 0x18 | ||
214 | #define GPCR_OFFSET 0x24 | ||
215 | #define GRER_OFFSET 0x30 | ||
216 | #define GFER_OFFSET 0x3C | ||
217 | #define GEDR_OFFSET 0x48 | ||
218 | |||
219 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | 206 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ |
220 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | 207 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ |
221 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | 208 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ |
@@ -265,10 +252,6 @@ | |||
265 | 252 | ||
266 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | 253 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) |
267 | 254 | ||
268 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
269 | |||
270 | /* Interrupt Controller */ | ||
271 | |||
272 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | 255 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
273 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | 256 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
274 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | 257 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
@@ -287,18 +270,7 @@ | |||
287 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | 270 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) |
288 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | 271 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ |
289 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | 272 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) |
290 | #else | ||
291 | |||
292 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
293 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
294 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
295 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
296 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
297 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
298 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
299 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
300 | 273 | ||
301 | #endif | ||
302 | 274 | ||
303 | /* | 275 | /* |
304 | * Power Manager - see pxa2xx-regs.h | 276 | * Power Manager - see pxa2xx-regs.h |