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authorHariprasad Shenai <hariprasad@chelsio.com>2015-01-05 06:00:44 -0500
committerDavid S. Miller <davem@davemloft.net>2015-01-05 16:34:47 -0500
commitf061de42e6ae697dd22cd0acbfd50fa3c4ecb9b8 (patch)
treedd83a9e487842aa3f8a0badd8bb00d6aa7e14d27
parentf612b815d75b054ec06c8be260409a7ab271c253 (diff)
cxgb4/cxgb4vf/csiostor: Cleanup SGE and PCI related register defines
This patch cleansup remaining SGE related macros/register defines and all PCI related ones that are defined in t4_regs.h and the affected files. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c68
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/sge.c78
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c224
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h605
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_values.h4
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c12
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c6
-rw-r--r--drivers/scsi/csiostor/csio_hw.c33
-rw-r--r--drivers/scsi/csiostor/csio_hw_chip.h4
-rw-r--r--drivers/scsi/csiostor/csio_hw_t4.c112
-rw-r--r--drivers/scsi/csiostor/csio_hw_t5.c114
-rw-r--r--drivers/scsi/csiostor/csio_isr.c2
-rw-r--r--drivers/scsi/csiostor/csio_wr.c36
13 files changed, 766 insertions, 532 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 5e0d57a7b3b6..16c633f4bf8b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -1590,9 +1590,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1590 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data); 1590 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1591 data += sizeof(struct queue_port_stats) / sizeof(u64); 1591 data += sizeof(struct queue_port_stats) / sizeof(u64);
1592 if (!is_t4(adapter->params.chip)) { 1592 if (!is_t4(adapter->params.chip)) {
1593 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7)); 1593 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7));
1594 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL); 1594 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL_A);
1595 val2 = t4_read_reg(adapter, SGE_STAT_MATCH); 1595 val2 = t4_read_reg(adapter, SGE_STAT_MATCH_A);
1596 *data = val1 - val2; 1596 *data = val1 - val2;
1597 data++; 1597 data++;
1598 *data = val2; 1598 *data = val2;
@@ -3601,14 +3601,14 @@ unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3601 struct adapter *adap = netdev2adap(dev); 3601 struct adapter *adap = netdev2adap(dev);
3602 u32 v1, v2, lp_count, hp_count; 3602 u32 v1, v2, lp_count, hp_count;
3603 3603
3604 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); 3604 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
3605 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2); 3605 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
3606 if (is_t4(adap->params.chip)) { 3606 if (is_t4(adap->params.chip)) {
3607 lp_count = G_LP_COUNT(v1); 3607 lp_count = LP_COUNT_G(v1);
3608 hp_count = G_HP_COUNT(v1); 3608 hp_count = HP_COUNT_G(v1);
3609 } else { 3609 } else {
3610 lp_count = G_LP_COUNT_T5(v1); 3610 lp_count = LP_COUNT_T5_G(v1);
3611 hp_count = G_HP_COUNT_T5(v2); 3611 hp_count = HP_COUNT_T5_G(v2);
3612 } 3612 }
3613 return lpfifo ? lp_count : hp_count; 3613 return lpfifo ? lp_count : hp_count;
3614} 3614}
@@ -3667,14 +3667,14 @@ int cxgb4_flush_eq_cache(struct net_device *dev)
3667 int ret; 3667 int ret;
3668 3668
3669 ret = t4_fwaddrspace_write(adap, adap->mbox, 3669 ret = t4_fwaddrspace_write(adap, adap->mbox,
3670 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000); 3670 0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
3671 return ret; 3671 return ret;
3672} 3672}
3673EXPORT_SYMBOL(cxgb4_flush_eq_cache); 3673EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3674 3674
3675static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 3675static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3676{ 3676{
3677 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8; 3677 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3678 __be64 indices; 3678 __be64 indices;
3679 int ret; 3679 int ret;
3680 3680
@@ -3728,7 +3728,7 @@ void cxgb4_disable_db_coalescing(struct net_device *dev)
3728 struct adapter *adap; 3728 struct adapter *adap;
3729 3729
3730 adap = netdev2adap(dev); 3730 adap = netdev2adap(dev);
3731 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 3731 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
3732 NOCOALESCE_F); 3732 NOCOALESCE_F);
3733} 3733}
3734EXPORT_SYMBOL(cxgb4_disable_db_coalescing); 3734EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
@@ -3738,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev)
3738 struct adapter *adap; 3738 struct adapter *adap;
3739 3739
3740 adap = netdev2adap(dev); 3740 adap = netdev2adap(dev);
3741 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 0); 3741 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
3742} 3742}
3743EXPORT_SYMBOL(cxgb4_enable_db_coalescing); 3743EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3744 3744
@@ -3877,14 +3877,14 @@ static void drain_db_fifo(struct adapter *adap, int usecs)
3877 u32 v1, v2, lp_count, hp_count; 3877 u32 v1, v2, lp_count, hp_count;
3878 3878
3879 do { 3879 do {
3880 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); 3880 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
3881 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2); 3881 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
3882 if (is_t4(adap->params.chip)) { 3882 if (is_t4(adap->params.chip)) {
3883 lp_count = G_LP_COUNT(v1); 3883 lp_count = LP_COUNT_G(v1);
3884 hp_count = G_HP_COUNT(v1); 3884 hp_count = HP_COUNT_G(v1);
3885 } else { 3885 } else {
3886 lp_count = G_LP_COUNT_T5(v1); 3886 lp_count = LP_COUNT_T5_G(v1);
3887 hp_count = G_HP_COUNT_T5(v2); 3887 hp_count = HP_COUNT_T5_G(v2);
3888 } 3888 }
3889 3889
3890 if (lp_count == 0 && hp_count == 0) 3890 if (lp_count == 0 && hp_count == 0)
@@ -4044,7 +4044,7 @@ static void process_db_drop(struct work_struct *work)
4044 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 4044 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4045 } 4045 }
4046 4046
4047 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0); 4047 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
4048} 4048}
4049 4049
4050void t4_db_full(struct adapter *adap) 4050void t4_db_full(struct adapter *adap)
@@ -4871,16 +4871,16 @@ static void setup_memwin(struct adapter *adap)
4871 mem_win2_base = MEMWIN2_BASE_T5; 4871 mem_win2_base = MEMWIN2_BASE_T5;
4872 mem_win2_aperture = MEMWIN2_APERTURE_T5; 4872 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4873 } 4873 }
4874 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0), 4874 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
4875 mem_win0_base | BIR(0) | 4875 mem_win0_base | BIR_V(0) |
4876 WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 4876 WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
4877 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1), 4877 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
4878 mem_win1_base | BIR(0) | 4878 mem_win1_base | BIR_V(0) |
4879 WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 4879 WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
4880 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2), 4880 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
4881 mem_win2_base | BIR(0) | 4881 mem_win2_base | BIR_V(0) |
4882 WINDOW(ilog2(mem_win2_aperture) - 10)); 4882 WINDOW_V(ilog2(mem_win2_aperture) - 10));
4883 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2)); 4883 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
4884} 4884}
4885 4885
4886static void setup_memwin_rdma(struct adapter *adap) 4886static void setup_memwin_rdma(struct adapter *adap)
@@ -4894,13 +4894,13 @@ static void setup_memwin_rdma(struct adapter *adap)
4894 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 4894 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4895 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 4895 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4896 t4_write_reg(adap, 4896 t4_write_reg(adap,
4897 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3), 4897 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
4898 start | BIR(1) | WINDOW(ilog2(sz_kb))); 4898 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
4899 t4_write_reg(adap, 4899 t4_write_reg(adap,
4900 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3), 4900 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
4901 adap->vres.ocq.start); 4901 adap->vres.ocq.start);
4902 t4_read_reg(adap, 4902 t4_read_reg(adap,
4903 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3)); 4903 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
4904 } 4904 }
4905} 4905}
4906 4906
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 4449fc7ec14e..d7c301c77060 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -2098,7 +2098,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie)
2098{ 2098{
2099 struct adapter *adap = cookie; 2099 struct adapter *adap = cookie;
2100 2100
2101 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0); 2101 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
2102 if (t4_slow_intr_handler(adap) | process_intrq(adap)) 2102 if (t4_slow_intr_handler(adap) | process_intrq(adap))
2103 return IRQ_HANDLED; 2103 return IRQ_HANDLED;
2104 return IRQ_NONE; /* probably shared interrupt */ 2104 return IRQ_NONE; /* probably shared interrupt */
@@ -2145,9 +2145,9 @@ static void sge_rx_timer_cb(unsigned long data)
2145 } 2145 }
2146 } 2146 }
2147 2147
2148 t4_write_reg(adap, SGE_DEBUG_INDEX, 13); 2148 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
2149 idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH); 2149 idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
2150 idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); 2150 idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2151 2151
2152 for (i = 0; i < 2; i++) { 2152 for (i = 0; i < 2; i++) {
2153 u32 debug0, debug11; 2153 u32 debug0, debug11;
@@ -2191,12 +2191,12 @@ static void sge_rx_timer_cb(unsigned long data)
2191 /* Read and save the SGE IDMA State and Queue ID information. 2191 /* Read and save the SGE IDMA State and Queue ID information.
2192 * We do this every time in case it changes across time ... 2192 * We do this every time in case it changes across time ...
2193 */ 2193 */
2194 t4_write_reg(adap, SGE_DEBUG_INDEX, 0); 2194 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
2195 debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); 2195 debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2196 s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 2196 s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
2197 2197
2198 t4_write_reg(adap, SGE_DEBUG_INDEX, 11); 2198 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
2199 debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); 2199 debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2200 s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 2200 s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
2201 2201
2202 CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n", 2202 CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
@@ -2826,21 +2826,21 @@ static int t4_sge_init_soft(struct adapter *adap)
2826 * Retrieve our RX interrupt holdoff timer values and counter 2826 * Retrieve our RX interrupt holdoff timer values and counter
2827 * threshold values from the SGE parameters. 2827 * threshold values from the SGE parameters.
2828 */ 2828 */
2829 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1); 2829 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
2830 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3); 2830 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
2831 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5); 2831 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
2832 s->timer_val[0] = core_ticks_to_us(adap, 2832 s->timer_val[0] = core_ticks_to_us(adap,
2833 TIMERVALUE0_GET(timer_value_0_and_1)); 2833 TIMERVALUE0_G(timer_value_0_and_1));
2834 s->timer_val[1] = core_ticks_to_us(adap, 2834 s->timer_val[1] = core_ticks_to_us(adap,
2835 TIMERVALUE1_GET(timer_value_0_and_1)); 2835 TIMERVALUE1_G(timer_value_0_and_1));
2836 s->timer_val[2] = core_ticks_to_us(adap, 2836 s->timer_val[2] = core_ticks_to_us(adap,
2837 TIMERVALUE2_GET(timer_value_2_and_3)); 2837 TIMERVALUE2_G(timer_value_2_and_3));
2838 s->timer_val[3] = core_ticks_to_us(adap, 2838 s->timer_val[3] = core_ticks_to_us(adap,
2839 TIMERVALUE3_GET(timer_value_2_and_3)); 2839 TIMERVALUE3_G(timer_value_2_and_3));
2840 s->timer_val[4] = core_ticks_to_us(adap, 2840 s->timer_val[4] = core_ticks_to_us(adap,
2841 TIMERVALUE4_GET(timer_value_4_and_5)); 2841 TIMERVALUE4_G(timer_value_4_and_5));
2842 s->timer_val[5] = core_ticks_to_us(adap, 2842 s->timer_val[5] = core_ticks_to_us(adap,
2843 TIMERVALUE5_GET(timer_value_4_and_5)); 2843 TIMERVALUE5_G(timer_value_4_and_5));
2844 2844
2845 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); 2845 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
2846 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); 2846 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
@@ -2866,21 +2866,21 @@ static int t4_sge_init_hard(struct adapter *adap)
2866 * and generate an interrupt when this occurs so we can recover. 2866 * and generate an interrupt when this occurs so we can recover.
2867 */ 2867 */
2868 if (is_t4(adap->params.chip)) { 2868 if (is_t4(adap->params.chip)) {
2869 t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, 2869 t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
2870 V_HP_INT_THRESH(M_HP_INT_THRESH) | 2870 HP_INT_THRESH_V(HP_INT_THRESH_M) |
2871 V_LP_INT_THRESH(M_LP_INT_THRESH), 2871 LP_INT_THRESH_V(LP_INT_THRESH_M),
2872 V_HP_INT_THRESH(dbfifo_int_thresh) | 2872 HP_INT_THRESH_V(dbfifo_int_thresh) |
2873 V_LP_INT_THRESH(dbfifo_int_thresh)); 2873 LP_INT_THRESH_V(dbfifo_int_thresh));
2874 } else { 2874 } else {
2875 t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, 2875 t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
2876 V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5), 2876 LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
2877 V_LP_INT_THRESH_T5(dbfifo_int_thresh)); 2877 LP_INT_THRESH_T5_V(dbfifo_int_thresh));
2878 t4_set_reg_field(adap, SGE_DBFIFO_STATUS2, 2878 t4_set_reg_field(adap, SGE_DBFIFO_STATUS2_A,
2879 V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5), 2879 HP_INT_THRESH_T5_V(HP_INT_THRESH_T5_M),
2880 V_HP_INT_THRESH_T5(dbfifo_int_thresh)); 2880 HP_INT_THRESH_T5_V(dbfifo_int_thresh));
2881 } 2881 }
2882 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP, 2882 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
2883 F_ENABLE_DROP); 2883 ENABLE_DROP_F);
2884 2884
2885 /* 2885 /*
2886 * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by 2886 * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
@@ -2905,15 +2905,15 @@ static int t4_sge_init_hard(struct adapter *adap)
2905 THRESHOLD_1_V(s->counter_val[1]) | 2905 THRESHOLD_1_V(s->counter_val[1]) |
2906 THRESHOLD_2_V(s->counter_val[2]) | 2906 THRESHOLD_2_V(s->counter_val[2]) |
2907 THRESHOLD_3_V(s->counter_val[3])); 2907 THRESHOLD_3_V(s->counter_val[3]));
2908 t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1, 2908 t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1_A,
2909 TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) | 2909 TIMERVALUE0_V(us_to_core_ticks(adap, s->timer_val[0])) |
2910 TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1]))); 2910 TIMERVALUE1_V(us_to_core_ticks(adap, s->timer_val[1])));
2911 t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3, 2911 t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3_A,
2912 TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) | 2912 TIMERVALUE2_V(us_to_core_ticks(adap, s->timer_val[2])) |
2913 TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3]))); 2913 TIMERVALUE3_V(us_to_core_ticks(adap, s->timer_val[3])));
2914 t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5, 2914 t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5_A,
2915 TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) | 2915 TIMERVALUE4_V(us_to_core_ticks(adap, s->timer_val[4])) |
2916 TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5]))); 2916 TIMERVALUE5_V(us_to_core_ticks(adap, s->timer_val[5])));
2917 2917
2918 return 0; 2918 return 0;
2919} 2919}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index ac00cab0052b..9f8cd561250a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -150,20 +150,20 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
150 */ 150 */
151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) 151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
152{ 152{
153 u32 req = ENABLE | FUNCTION(adap->fn) | reg; 153 u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);
154 154
155 if (is_t4(adap->params.chip)) 155 if (is_t4(adap->params.chip))
156 req |= F_LOCALCFG; 156 req |= LOCALCFG_F;
157 157
158 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req); 158 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
159 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA); 159 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
160 160
161 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 161 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
162 * Configuration Space read. (None of the other fields matter when 162 * Configuration Space read. (None of the other fields matter when
163 * ENABLE is 0 so a simple register write is easier than a 163 * ENABLE is 0 so a simple register write is easier than a
164 * read-modify-write via t4_set_reg_field().) 164 * read-modify-write via t4_set_reg_field().)
165 */ 165 */
166 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0); 166 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
167} 167}
168 168
169/* 169/*
@@ -188,8 +188,8 @@ static void t4_report_fw_error(struct adapter *adap)
188 }; 188 };
189 u32 pcie_fw; 189 u32 pcie_fw;
190 190
191 pcie_fw = t4_read_reg(adap, MA_PCIE_FW); 191 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
192 if (pcie_fw & PCIE_FW_ERR) 192 if (pcie_fw & PCIE_FW_ERR_F)
193 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", 193 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
194 reason[PCIE_FW_EVAL_G(pcie_fw)]); 194 reason[PCIE_FW_EVAL_G(pcie_fw)]);
195} 195}
@@ -506,13 +506,13 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
506 * the address is relative to BAR0. 506 * the address is relative to BAR0.
507 */ 507 */
508 mem_reg = t4_read_reg(adap, 508 mem_reg = t4_read_reg(adap,
509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
510 win)); 510 win));
511 mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10); 511 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
512 mem_base = GET_PCIEOFST(mem_reg) << 10; 512 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
513 if (is_t4(adap->params.chip)) 513 if (is_t4(adap->params.chip))
514 mem_base -= adap->t4_bar0; 514 mem_base -= adap->t4_bar0;
515 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn); 515 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);
516 516
517 /* Calculate our initial PCI-E Memory Window Position and Offset into 517 /* Calculate our initial PCI-E Memory Window Position and Offset into
518 * that Window. 518 * that Window.
@@ -525,10 +525,10 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
525 * attempt to use the new value.) 525 * attempt to use the new value.)
526 */ 526 */
527 t4_write_reg(adap, 527 t4_write_reg(adap,
528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win), 528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
529 pos | win_pf); 529 pos | win_pf);
530 t4_read_reg(adap, 530 t4_read_reg(adap,
531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
532 532
533 /* Transfer data to/from the adapter as long as there's an integral 533 /* Transfer data to/from the adapter as long as there's an integral
534 * number of 32-bit transfers to complete. 534 * number of 32-bit transfers to complete.
@@ -553,11 +553,11 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
553 pos += mem_aperture; 553 pos += mem_aperture;
554 offset = 0; 554 offset = 0;
555 t4_write_reg(adap, 555 t4_write_reg(adap,
556 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 556 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
557 win), pos | win_pf); 557 win), pos | win_pf);
558 t4_read_reg(adap, 558 t4_read_reg(adap,
559 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 559 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
560 win)); 560 win));
561 } 561 }
562 } 562 }
563 563
@@ -1366,95 +1366,97 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1366static void pcie_intr_handler(struct adapter *adapter) 1366static void pcie_intr_handler(struct adapter *adapter)
1367{ 1367{
1368 static const struct intr_info sysbus_intr_info[] = { 1368 static const struct intr_info sysbus_intr_info[] = {
1369 { RNPP, "RXNP array parity error", -1, 1 }, 1369 { RNPP_F, "RXNP array parity error", -1, 1 },
1370 { RPCP, "RXPC array parity error", -1, 1 }, 1370 { RPCP_F, "RXPC array parity error", -1, 1 },
1371 { RCIP, "RXCIF array parity error", -1, 1 }, 1371 { RCIP_F, "RXCIF array parity error", -1, 1 },
1372 { RCCP, "Rx completions control array parity error", -1, 1 }, 1372 { RCCP_F, "Rx completions control array parity error", -1, 1 },
1373 { RFTP, "RXFT array parity error", -1, 1 }, 1373 { RFTP_F, "RXFT array parity error", -1, 1 },
1374 { 0 } 1374 { 0 }
1375 }; 1375 };
1376 static const struct intr_info pcie_port_intr_info[] = { 1376 static const struct intr_info pcie_port_intr_info[] = {
1377 { TPCP, "TXPC array parity error", -1, 1 }, 1377 { TPCP_F, "TXPC array parity error", -1, 1 },
1378 { TNPP, "TXNP array parity error", -1, 1 }, 1378 { TNPP_F, "TXNP array parity error", -1, 1 },
1379 { TFTP, "TXFT array parity error", -1, 1 }, 1379 { TFTP_F, "TXFT array parity error", -1, 1 },
1380 { TCAP, "TXCA array parity error", -1, 1 }, 1380 { TCAP_F, "TXCA array parity error", -1, 1 },
1381 { TCIP, "TXCIF array parity error", -1, 1 }, 1381 { TCIP_F, "TXCIF array parity error", -1, 1 },
1382 { RCAP, "RXCA array parity error", -1, 1 }, 1382 { RCAP_F, "RXCA array parity error", -1, 1 },
1383 { OTDD, "outbound request TLP discarded", -1, 1 }, 1383 { OTDD_F, "outbound request TLP discarded", -1, 1 },
1384 { RDPE, "Rx data parity error", -1, 1 }, 1384 { RDPE_F, "Rx data parity error", -1, 1 },
1385 { TDUE, "Tx uncorrectable data error", -1, 1 }, 1385 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
1386 { 0 } 1386 { 0 }
1387 }; 1387 };
1388 static const struct intr_info pcie_intr_info[] = { 1388 static const struct intr_info pcie_intr_info[] = {
1389 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 1389 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
1390 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 1390 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
1391 { MSIDATAPERR, "MSI data parity error", -1, 1 }, 1391 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
1392 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 1392 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
1393 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 1393 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
1394 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 1394 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
1395 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 1395 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
1396 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 1396 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
1397 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 1397 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
1398 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 1398 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
1399 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 1399 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
1400 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 1400 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
1401 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 1401 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
1402 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 1402 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
1403 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 1403 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
1404 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 1404 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
1405 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 1405 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
1406 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 1406 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
1407 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 1407 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
1408 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 1408 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
1409 { FIDPERR, "PCI FID parity error", -1, 1 }, 1409 { FIDPERR_F, "PCI FID parity error", -1, 1 },
1410 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 1410 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
1411 { MATAGPERR, "PCI MA tag parity error", -1, 1 }, 1411 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
1412 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 1412 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
1413 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 1413 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
1414 { RXWRPERR, "PCI Rx write parity error", -1, 1 }, 1414 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
1415 { RPLPERR, "PCI replay buffer parity error", -1, 1 }, 1415 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
1416 { PCIESINT, "PCI core secondary fault", -1, 1 }, 1416 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
1417 { PCIEPINT, "PCI core primary fault", -1, 1 }, 1417 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
1418 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 }, 1418 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
1419 -1, 0 },
1419 { 0 } 1420 { 0 }
1420 }; 1421 };
1421 1422
1422 static struct intr_info t5_pcie_intr_info[] = { 1423 static struct intr_info t5_pcie_intr_info[] = {
1423 { MSTGRPPERR, "Master Response Read Queue parity error", 1424 { MSTGRPPERR_F, "Master Response Read Queue parity error",
1424 -1, 1 }, 1425 -1, 1 },
1425 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 1426 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
1426 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 1427 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
1427 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 1428 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
1428 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 1429 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
1429 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 1430 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
1430 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 1431 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
1431 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 1432 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
1432 -1, 1 }, 1433 -1, 1 },
1433 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 1434 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
1434 -1, 1 }, 1435 -1, 1 },
1435 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 1436 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
1436 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 1437 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
1437 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 1438 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
1438 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 1439 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
1439 { DREQWRPERR, "PCI DMA channel write request parity error", 1440 { DREQWRPERR_F, "PCI DMA channel write request parity error",
1440 -1, 1 }, 1441 -1, 1 },
1441 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 1442 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
1442 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 1443 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
1443 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 1444 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
1444 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 1445 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
1445 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 1446 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
1446 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 1447 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
1447 { FIDPERR, "PCI FID parity error", -1, 1 }, 1448 { FIDPERR_F, "PCI FID parity error", -1, 1 },
1448 { VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 1449 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
1449 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 1450 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
1450 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 1451 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
1451 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 1452 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
1452 -1, 1 }, 1453 -1, 1 },
1453 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 }, 1454 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
1454 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 1455 -1, 1 },
1455 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 1456 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
1456 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 1457 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
1457 { READRSPERR, "Outbound read error", -1, 0 }, 1458 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1459 { READRSPERR_F, "Outbound read error", -1, 0 },
1458 { 0 } 1460 { 0 }
1459 }; 1461 };
1460 1462
@@ -1462,15 +1464,15 @@ static void pcie_intr_handler(struct adapter *adapter)
1462 1464
1463 if (is_t4(adapter->params.chip)) 1465 if (is_t4(adapter->params.chip))
1464 fat = t4_handle_intr_status(adapter, 1466 fat = t4_handle_intr_status(adapter,
1465 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 1467 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
1466 sysbus_intr_info) + 1468 sysbus_intr_info) +
1467 t4_handle_intr_status(adapter, 1469 t4_handle_intr_status(adapter,
1468 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 1470 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
1469 pcie_port_intr_info) + 1471 pcie_port_intr_info) +
1470 t4_handle_intr_status(adapter, PCIE_INT_CAUSE, 1472 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
1471 pcie_intr_info); 1473 pcie_intr_info);
1472 else 1474 else
1473 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE, 1475 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
1474 t5_pcie_intr_info); 1476 t5_pcie_intr_info);
1475 1477
1476 if (fat) 1478 if (fat)
@@ -1590,7 +1592,7 @@ static void cim_intr_handler(struct adapter *adapter)
1590 1592
1591 int fat; 1593 int fat;
1592 1594
1593 if (t4_read_reg(adapter, MA_PCIE_FW) & PCIE_FW_ERR) 1595 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
1594 t4_report_fw_error(adapter); 1596 t4_report_fw_error(adapter);
1595 1597
1596 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE, 1598 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
@@ -2750,9 +2752,9 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
2750 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 2752 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2751 }; 2753 };
2752 static const u32 sge_regs[] = { 2754 static const u32 sge_regs[] = {
2753 SGE_DEBUG_DATA_LOW_INDEX_2, 2755 SGE_DEBUG_DATA_LOW_INDEX_2_A,
2754 SGE_DEBUG_DATA_LOW_INDEX_3, 2756 SGE_DEBUG_DATA_LOW_INDEX_3_A,
2755 SGE_DEBUG_DATA_HIGH_INDEX_10, 2757 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
2756 }; 2758 };
2757 const char **sge_idma_decode; 2759 const char **sge_idma_decode;
2758 int sge_idma_decode_nstates; 2760 int sge_idma_decode_nstates;
@@ -2819,7 +2821,7 @@ retry:
2819 if (ret < 0) { 2821 if (ret < 0) {
2820 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 2822 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2821 goto retry; 2823 goto retry;
2822 if (t4_read_reg(adap, MA_PCIE_FW) & PCIE_FW_ERR) 2824 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
2823 t4_report_fw_error(adap); 2825 t4_report_fw_error(adap);
2824 return ret; 2826 return ret;
2825 } 2827 }
@@ -2869,8 +2871,8 @@ retry:
2869 * timeout ... and then retry if we haven't exhausted 2871 * timeout ... and then retry if we haven't exhausted
2870 * our retries ... 2872 * our retries ...
2871 */ 2873 */
2872 pcie_fw = t4_read_reg(adap, MA_PCIE_FW); 2874 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
2873 if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) { 2875 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
2874 if (waiting <= 0) { 2876 if (waiting <= 0) {
2875 if (retries-- > 0) 2877 if (retries-- > 0)
2876 goto retry; 2878 goto retry;
@@ -2885,9 +2887,9 @@ retry:
2885 * report errors preferentially. 2887 * report errors preferentially.
2886 */ 2888 */
2887 if (state) { 2889 if (state) {
2888 if (pcie_fw & PCIE_FW_ERR) 2890 if (pcie_fw & PCIE_FW_ERR_F)
2889 *state = DEV_STATE_ERR; 2891 *state = DEV_STATE_ERR;
2890 else if (pcie_fw & PCIE_FW_INIT) 2892 else if (pcie_fw & PCIE_FW_INIT_F)
2891 *state = DEV_STATE_INIT; 2893 *state = DEV_STATE_INIT;
2892 } 2894 }
2893 2895
@@ -2897,7 +2899,7 @@ retry:
2897 * for our caller. 2899 * for our caller.
2898 */ 2900 */
2899 if (master_mbox == PCIE_FW_MASTER_M && 2901 if (master_mbox == PCIE_FW_MASTER_M &&
2900 (pcie_fw & PCIE_FW_MASTER_VLD)) 2902 (pcie_fw & PCIE_FW_MASTER_VLD_F))
2901 master_mbox = PCIE_FW_MASTER_G(pcie_fw); 2903 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
2902 break; 2904 break;
2903 } 2905 }
@@ -3006,7 +3008,7 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3006 */ 3008 */
3007 if (ret == 0 || force) { 3009 if (ret == 0 || force) {
3008 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST); 3010 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
3009 t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 3011 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
3010 PCIE_FW_HALT_F); 3012 PCIE_FW_HALT_F);
3011 } 3013 }
3012 3014
@@ -3046,7 +3048,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3046 * doing it automatically, we need to clear the PCIE_FW.HALT 3048 * doing it automatically, we need to clear the PCIE_FW.HALT
3047 * bit. 3049 * bit.
3048 */ 3050 */
3049 t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 0); 3051 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
3050 3052
3051 /* 3053 /*
3052 * If we've been given a valid mailbox, first try to get the 3054 * If we've been given a valid mailbox, first try to get the
@@ -3070,7 +3072,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3070 3072
3071 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0); 3073 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
3072 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 3074 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3073 if (!(t4_read_reg(adap, PCIE_FW) & PCIE_FW_HALT_F)) 3075 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
3074 return 0; 3076 return 0;
3075 msleep(100); 3077 msleep(100);
3076 ms += 100; 3078 ms += 100;
@@ -4146,7 +4148,7 @@ int t4_init_sge_params(struct adapter *adapter)
4146 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn); 4148 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);
4147 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); 4149 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
4148 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 4150 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
4149 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF); 4151 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
4150 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 4152 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
4151 4153
4152 return 0; 4154 return 0;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 29c09113c13b..9b7382448019 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -369,196 +369,424 @@
369#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) 369#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
370#define ENABLE_DROP_F ENABLE_DROP_V(1U) 370#define ENABLE_DROP_F ENABLE_DROP_V(1U)
371 371
372#define SGE_TIMER_VALUE_0_AND_1 0x10b8 372#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
373#define TIMERVALUE0_MASK 0xffff0000U 373
374#define TIMERVALUE0_SHIFT 16 374#define TIMERVALUE0_S 16
375#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 375#define TIMERVALUE0_M 0xffffU
376#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 376#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
377#define TIMERVALUE1_MASK 0x0000ffffU 377#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
378#define TIMERVALUE1_SHIFT 0 378
379#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 379#define TIMERVALUE1_S 0
380#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 380#define TIMERVALUE1_M 0xffffU
381 381#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
382#define SGE_TIMER_VALUE_2_AND_3 0x10bc 382#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
383#define TIMERVALUE2_MASK 0xffff0000U 383
384#define TIMERVALUE2_SHIFT 16 384#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
385#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) 385
386#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) 386#define TIMERVALUE2_S 16
387#define TIMERVALUE3_MASK 0x0000ffffU 387#define TIMERVALUE2_M 0xffffU
388#define TIMERVALUE3_SHIFT 0 388#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
389#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) 389#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
390#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) 390
391 391#define TIMERVALUE3_S 0
392#define SGE_TIMER_VALUE_4_AND_5 0x10c0 392#define TIMERVALUE3_M 0xffffU
393#define TIMERVALUE4_MASK 0xffff0000U 393#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
394#define TIMERVALUE4_SHIFT 16 394#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
395#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) 395
396#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) 396#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
397#define TIMERVALUE5_MASK 0x0000ffffU 397
398#define TIMERVALUE5_SHIFT 0 398#define TIMERVALUE4_S 16
399#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) 399#define TIMERVALUE4_M 0xffffU
400#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) 400#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
401 401#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
402#define SGE_DEBUG_INDEX 0x10cc 402
403#define SGE_DEBUG_DATA_HIGH 0x10d0 403#define TIMERVALUE5_S 0
404#define SGE_DEBUG_DATA_LOW 0x10d4 404#define TIMERVALUE5_M 0xffffU
405#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 405#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
406#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc 406#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
407#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 407
408#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 408#define SGE_DEBUG_INDEX_A 0x10cc
409#define SGE_DEBUG_DATA_HIGH_A 0x10d0
410#define SGE_DEBUG_DATA_LOW_A 0x10d4
411
412#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
413#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
414#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
415
416#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
409#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8 417#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
410 418
411#define S_HP_INT_THRESH 28 419#define HP_INT_THRESH_S 28
412#define M_HP_INT_THRESH 0xfU 420#define HP_INT_THRESH_M 0xfU
413#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 421#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
414#define S_LP_INT_THRESH_T5 18 422
415#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) 423#define HP_COUNT_S 16
416#define M_LP_COUNT_T5 0x3ffffU 424#define HP_COUNT_M 0x7ffU
417#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) 425#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
418#define M_HP_COUNT 0x7ffU 426
419#define S_HP_COUNT 16 427#define LP_INT_THRESH_S 12
420#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 428#define LP_INT_THRESH_M 0xfU
421#define S_LP_INT_THRESH 12 429#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
422#define M_LP_INT_THRESH 0xfU 430
423#define M_LP_INT_THRESH_T5 0xfffU 431#define LP_COUNT_S 0
424#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 432#define LP_COUNT_M 0x7ffU
425#define M_LP_COUNT 0x7ffU 433#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
426#define S_LP_COUNT 0 434
427#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 435#define LP_INT_THRESH_T5_S 18
428#define A_SGE_DBFIFO_STATUS 0x10a4 436#define LP_INT_THRESH_T5_M 0xfffU
429 437#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
430#define SGE_STAT_TOTAL 0x10e4 438
431#define SGE_STAT_MATCH 0x10e8 439#define LP_COUNT_T5_S 0
432 440#define LP_COUNT_T5_M 0x3ffffU
433#define SGE_STAT_CFG 0x10ec 441#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
434#define S_STATSOURCE_T5 9 442
435#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 443#define SGE_DOORBELL_CONTROL_A 0x10a8
436 444
437#define SGE_DBFIFO_STATUS2 0x1118 445#define SGE_STAT_TOTAL_A 0x10e4
438#define M_HP_COUNT_T5 0x3ffU 446#define SGE_STAT_MATCH_A 0x10e8
439#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) 447#define SGE_STAT_CFG_A 0x10ec
440#define S_HP_INT_THRESH_T5 10 448
441#define M_HP_INT_THRESH_T5 0xfU 449#define STATSOURCE_T5_S 9
442#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) 450#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
443 451
444#define S_ENABLE_DROP 13 452#define SGE_DBFIFO_STATUS2_A 0x1118
445#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 453
446#define F_ENABLE_DROP V_ENABLE_DROP(1U) 454#define HP_INT_THRESH_T5_S 10
447#define S_DROPPED_DB 0 455#define HP_INT_THRESH_T5_M 0xfU
448#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 456#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
449#define F_DROPPED_DB V_DROPPED_DB(1U) 457
450#define A_SGE_DOORBELL_CONTROL 0x10a8 458#define HP_COUNT_T5_S 0
451 459#define HP_COUNT_T5_M 0x3ffU
452#define A_SGE_CTXT_CMD 0x11fc 460#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
453#define A_SGE_DBQ_CTXT_BADDR 0x1084 461
454 462#define ENABLE_DROP_S 13
455#define PCIE_PF_CFG 0x40 463#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
456#define AIVEC(x) ((x) << 4) 464#define ENABLE_DROP_F ENABLE_DROP_V(1U)
457#define AIVEC_MASK 0x3ffU 465
458 466#define DROPPED_DB_S 0
459#define PCIE_PF_CLI 0x44 467#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
460#define PCIE_INT_CAUSE 0x3004 468#define DROPPED_DB_F DROPPED_DB_V(1U)
461#define UNXSPLCPLERR 0x20000000U 469
462#define PCIEPINT 0x10000000U 470#define SGE_CTXT_CMD_A 0x11fc
463#define PCIESINT 0x08000000U 471#define SGE_DBQ_CTXT_BADDR_A 0x1084
464#define RPLPERR 0x04000000U 472
465#define RXWRPERR 0x02000000U 473/* registers for module PCIE */
466#define RXCPLPERR 0x01000000U 474#define PCIE_PF_CFG_A 0x40
467#define PIOTAGPERR 0x00800000U 475
468#define MATAGPERR 0x00400000U 476#define AIVEC_S 4
469#define INTXCLRPERR 0x00200000U 477#define AIVEC_M 0x3ffU
470#define FIDPERR 0x00100000U 478#define AIVEC_V(x) ((x) << AIVEC_S)
471#define CFGSNPPERR 0x00080000U 479
472#define HRSPPERR 0x00040000U 480#define PCIE_PF_CLI_A 0x44
473#define HREQPERR 0x00020000U 481#define PCIE_INT_CAUSE_A 0x3004
474#define HCNTPERR 0x00010000U 482
475#define DRSPPERR 0x00008000U 483#define UNXSPLCPLERR_S 29
476#define DREQPERR 0x00004000U 484#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
477#define DCNTPERR 0x00002000U 485#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
478#define CRSPPERR 0x00001000U 486
479#define CREQPERR 0x00000800U 487#define PCIEPINT_S 28
480#define CCNTPERR 0x00000400U 488#define PCIEPINT_V(x) ((x) << PCIEPINT_S)
481#define TARTAGPERR 0x00000200U 489#define PCIEPINT_F PCIEPINT_V(1U)
482#define PIOREQPERR 0x00000100U 490
483#define PIOCPLPERR 0x00000080U 491#define PCIESINT_S 27
484#define MSIXDIPERR 0x00000040U 492#define PCIESINT_V(x) ((x) << PCIESINT_S)
485#define MSIXDATAPERR 0x00000020U 493#define PCIESINT_F PCIESINT_V(1U)
486#define MSIXADDRHPERR 0x00000010U 494
487#define MSIXADDRLPERR 0x00000008U 495#define RPLPERR_S 26
488#define MSIDATAPERR 0x00000004U 496#define RPLPERR_V(x) ((x) << RPLPERR_S)
489#define MSIADDRHPERR 0x00000002U 497#define RPLPERR_F RPLPERR_V(1U)
490#define MSIADDRLPERR 0x00000001U 498
491 499#define RXWRPERR_S 25
492#define READRSPERR 0x20000000U 500#define RXWRPERR_V(x) ((x) << RXWRPERR_S)
493#define TRGT1GRPPERR 0x10000000U 501#define RXWRPERR_F RXWRPERR_V(1U)
494#define IPSOTPERR 0x08000000U 502
495#define IPRXDATAGRPPERR 0x02000000U 503#define RXCPLPERR_S 24
496#define IPRXHDRGRPPERR 0x01000000U 504#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
497#define MAGRPPERR 0x00400000U 505#define RXCPLPERR_F RXCPLPERR_V(1U)
498#define VFIDPERR 0x00200000U 506
499#define HREQWRPERR 0x00010000U 507#define PIOTAGPERR_S 23
500#define DREQWRPERR 0x00002000U 508#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
501#define MSTTAGQPERR 0x00000400U 509#define PIOTAGPERR_F PIOTAGPERR_V(1U)
502#define PIOREQGRPPERR 0x00000100U 510
503#define PIOCPLGRPPERR 0x00000080U 511#define MATAGPERR_S 22
504#define MSIXSTIPERR 0x00000004U 512#define MATAGPERR_V(x) ((x) << MATAGPERR_S)
505#define MSTTIMEOUTPERR 0x00000002U 513#define MATAGPERR_F MATAGPERR_V(1U)
506#define MSTGRPPERR 0x00000001U 514
507 515#define INTXCLRPERR_S 21
508#define PCIE_NONFAT_ERR 0x3010 516#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
509#define PCIE_CFG_SPACE_REQ 0x3060 517#define INTXCLRPERR_F INTXCLRPERR_V(1U)
510#define PCIE_CFG_SPACE_DATA 0x3064 518
511#define PCIE_MEM_ACCESS_BASE_WIN 0x3068 519#define FIDPERR_S 20
512#define S_PCIEOFST 10 520#define FIDPERR_V(x) ((x) << FIDPERR_S)
513#define M_PCIEOFST 0x3fffffU 521#define FIDPERR_F FIDPERR_V(1U)
514#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 522
515#define PCIEOFST_MASK 0xfffffc00U 523#define CFGSNPPERR_S 19
516#define BIR_MASK 0x00000300U 524#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
517#define BIR_SHIFT 8 525#define CFGSNPPERR_F CFGSNPPERR_V(1U)
518#define BIR(x) ((x) << BIR_SHIFT) 526
519#define WINDOW_MASK 0x000000ffU 527#define HRSPPERR_S 18
520#define WINDOW_SHIFT 0 528#define HRSPPERR_V(x) ((x) << HRSPPERR_S)
521#define WINDOW(x) ((x) << WINDOW_SHIFT) 529#define HRSPPERR_F HRSPPERR_V(1U)
522#define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK) 530
523#define PCIE_MEM_ACCESS_OFFSET 0x306c 531#define HREQPERR_S 17
524#define ENABLE (1U << 30) 532#define HREQPERR_V(x) ((x) << HREQPERR_S)
525#define FUNCTION(x) ((x) << 12) 533#define HREQPERR_F HREQPERR_V(1U)
526#define F_LOCALCFG (1U << 28) 534
527 535#define HCNTPERR_S 16
528#define S_PFNUM 0 536#define HCNTPERR_V(x) ((x) << HCNTPERR_S)
529#define V_PFNUM(x) ((x) << S_PFNUM) 537#define HCNTPERR_F HCNTPERR_V(1U)
530 538
531#define PCIE_FW 0x30b8 539#define DRSPPERR_S 15
532#define PCIE_FW_ERR 0x80000000U 540#define DRSPPERR_V(x) ((x) << DRSPPERR_S)
533#define PCIE_FW_INIT 0x40000000U 541#define DRSPPERR_F DRSPPERR_V(1U)
534#define PCIE_FW_HALT 0x20000000U 542
535#define PCIE_FW_MASTER_VLD 0x00008000U 543#define DREQPERR_S 14
536#define PCIE_FW_MASTER(x) ((x) << 12) 544#define DREQPERR_V(x) ((x) << DREQPERR_S)
537#define PCIE_FW_MASTER_MASK 0x7 545#define DREQPERR_F DREQPERR_V(1U)
538#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) 546
539 547#define DCNTPERR_S 13
540#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 548#define DCNTPERR_V(x) ((x) << DCNTPERR_S)
541#define RNPP 0x80000000U 549#define DCNTPERR_F DCNTPERR_V(1U)
542#define RPCP 0x20000000U 550
543#define RCIP 0x08000000U 551#define CRSPPERR_S 12
544#define RCCP 0x04000000U 552#define CRSPPERR_V(x) ((x) << CRSPPERR_S)
545#define RFTP 0x00800000U 553#define CRSPPERR_F CRSPPERR_V(1U)
546#define PTRP 0x00100000U 554
547 555#define CREQPERR_S 11
548#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 556#define CREQPERR_V(x) ((x) << CREQPERR_S)
549#define TPCP 0x40000000U 557#define CREQPERR_F CREQPERR_V(1U)
550#define TNPP 0x20000000U 558
551#define TFTP 0x10000000U 559#define CCNTPERR_S 10
552#define TCAP 0x08000000U 560#define CCNTPERR_V(x) ((x) << CCNTPERR_S)
553#define TCIP 0x04000000U 561#define CCNTPERR_F CCNTPERR_V(1U)
554#define RCAP 0x02000000U 562
555#define PLUP 0x00800000U 563#define TARTAGPERR_S 9
556#define PLDN 0x00400000U 564#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
557#define OTDD 0x00200000U 565#define TARTAGPERR_F TARTAGPERR_V(1U)
558#define GTRP 0x00100000U 566
559#define RDPE 0x00040000U 567#define PIOREQPERR_S 8
560#define TDCE 0x00020000U 568#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
561#define TDUE 0x00010000U 569#define PIOREQPERR_F PIOREQPERR_V(1U)
570
571#define PIOCPLPERR_S 7
572#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
573#define PIOCPLPERR_F PIOCPLPERR_V(1U)
574
575#define MSIXDIPERR_S 6
576#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
577#define MSIXDIPERR_F MSIXDIPERR_V(1U)
578
579#define MSIXDATAPERR_S 5
580#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
581#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
582
583#define MSIXADDRHPERR_S 4
584#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
585#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
586
587#define MSIXADDRLPERR_S 3
588#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
589#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
590
591#define MSIDATAPERR_S 2
592#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
593#define MSIDATAPERR_F MSIDATAPERR_V(1U)
594
595#define MSIADDRHPERR_S 1
596#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
597#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
598
599#define MSIADDRLPERR_S 0
600#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
601#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
602
603#define READRSPERR_S 29
604#define READRSPERR_V(x) ((x) << READRSPERR_S)
605#define READRSPERR_F READRSPERR_V(1U)
606
607#define TRGT1GRPPERR_S 28
608#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
609#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
610
611#define IPSOTPERR_S 27
612#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
613#define IPSOTPERR_F IPSOTPERR_V(1U)
614
615#define IPRETRYPERR_S 26
616#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
617#define IPRETRYPERR_F IPRETRYPERR_V(1U)
618
619#define IPRXDATAGRPPERR_S 25
620#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
621#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
622
623#define IPRXHDRGRPPERR_S 24
624#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
625#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
626
627#define MAGRPPERR_S 22
628#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
629#define MAGRPPERR_F MAGRPPERR_V(1U)
630
631#define VFIDPERR_S 21
632#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
633#define VFIDPERR_F VFIDPERR_V(1U)
634
635#define HREQWRPERR_S 16
636#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
637#define HREQWRPERR_F HREQWRPERR_V(1U)
638
639#define DREQWRPERR_S 13
640#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
641#define DREQWRPERR_F DREQWRPERR_V(1U)
642
643#define CREQRDPERR_S 11
644#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
645#define CREQRDPERR_F CREQRDPERR_V(1U)
646
647#define MSTTAGQPERR_S 10
648#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
649#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
650
651#define PIOREQGRPPERR_S 8
652#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
653#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
654
655#define PIOCPLGRPPERR_S 7
656#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
657#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
658
659#define MSIXSTIPERR_S 2
660#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
661#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
662
663#define MSTTIMEOUTPERR_S 1
664#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
665#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
666
667#define MSTGRPPERR_S 0
668#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
669#define MSTGRPPERR_F MSTGRPPERR_V(1U)
670
671#define PCIE_NONFAT_ERR_A 0x3010
672#define PCIE_CFG_SPACE_REQ_A 0x3060
673#define PCIE_CFG_SPACE_DATA_A 0x3064
674#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
675
676#define PCIEOFST_S 10
677#define PCIEOFST_M 0x3fffffU
678#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
679
680#define BIR_S 8
681#define BIR_M 0x3U
682#define BIR_V(x) ((x) << BIR_S)
683#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
684
685#define WINDOW_S 0
686#define WINDOW_M 0xffU
687#define WINDOW_V(x) ((x) << WINDOW_S)
688#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
689
690#define PCIE_MEM_ACCESS_OFFSET_A 0x306c
691
692#define ENABLE_S 30
693#define ENABLE_V(x) ((x) << ENABLE_S)
694#define ENABLE_F ENABLE_V(1U)
695
696#define LOCALCFG_S 28
697#define LOCALCFG_V(x) ((x) << LOCALCFG_S)
698#define LOCALCFG_F LOCALCFG_V(1U)
699
700#define FUNCTION_S 12
701#define FUNCTION_V(x) ((x) << FUNCTION_S)
702
703#define REGISTER_S 0
704#define REGISTER_V(x) ((x) << REGISTER_S)
705
706#define PFNUM_S 0
707#define PFNUM_V(x) ((x) << PFNUM_S)
708
709#define PCIE_FW_A 0x30b8
710
711#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
712
713#define RNPP_S 31
714#define RNPP_V(x) ((x) << RNPP_S)
715#define RNPP_F RNPP_V(1U)
716
717#define RPCP_S 29
718#define RPCP_V(x) ((x) << RPCP_S)
719#define RPCP_F RPCP_V(1U)
720
721#define RCIP_S 27
722#define RCIP_V(x) ((x) << RCIP_S)
723#define RCIP_F RCIP_V(1U)
724
725#define RCCP_S 26
726#define RCCP_V(x) ((x) << RCCP_S)
727#define RCCP_F RCCP_V(1U)
728
729#define RFTP_S 23
730#define RFTP_V(x) ((x) << RFTP_S)
731#define RFTP_F RFTP_V(1U)
732
733#define PTRP_S 20
734#define PTRP_V(x) ((x) << PTRP_S)
735#define PTRP_F PTRP_V(1U)
736
737#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
738
739#define TPCP_S 30
740#define TPCP_V(x) ((x) << TPCP_S)
741#define TPCP_F TPCP_V(1U)
742
743#define TNPP_S 29
744#define TNPP_V(x) ((x) << TNPP_S)
745#define TNPP_F TNPP_V(1U)
746
747#define TFTP_S 28
748#define TFTP_V(x) ((x) << TFTP_S)
749#define TFTP_F TFTP_V(1U)
750
751#define TCAP_S 27
752#define TCAP_V(x) ((x) << TCAP_S)
753#define TCAP_F TCAP_V(1U)
754
755#define TCIP_S 26
756#define TCIP_V(x) ((x) << TCIP_S)
757#define TCIP_F TCIP_V(1U)
758
759#define RCAP_S 25
760#define RCAP_V(x) ((x) << RCAP_S)
761#define RCAP_F RCAP_V(1U)
762
763#define PLUP_S 23
764#define PLUP_V(x) ((x) << PLUP_S)
765#define PLUP_F PLUP_V(1U)
766
767#define PLDN_S 22
768#define PLDN_V(x) ((x) << PLDN_S)
769#define PLDN_F PLDN_V(1U)
770
771#define OTDD_S 21
772#define OTDD_V(x) ((x) << OTDD_S)
773#define OTDD_F OTDD_V(1U)
774
775#define GTRP_S 20
776#define GTRP_V(x) ((x) << GTRP_S)
777#define GTRP_F GTRP_V(1U)
778
779#define RDPE_S 18
780#define RDPE_V(x) ((x) << RDPE_S)
781#define RDPE_F RDPE_V(1U)
782
783#define TDCE_S 17
784#define TDCE_V(x) ((x) << TDCE_S)
785#define TDCE_F TDCE_V(1U)
786
787#define TDUE_S 16
788#define TDUE_V(x) ((x) << TDUE_S)
789#define TDUE_F TDUE_V(1U)
562 790
563#define MC_INT_CAUSE 0x7518 791#define MC_INT_CAUSE 0x7518
564#define MC_P_INT_CAUSE 0x41318 792#define MC_P_INT_CAUSE 0x41318
@@ -663,7 +891,6 @@
663#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 891#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
664#define MEM_WRAP_CLIENT_NUM_SHIFT 0 892#define MEM_WRAP_CLIENT_NUM_SHIFT 0
665#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 893#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
666#define MA_PCIE_FW 0x30b8
667#define MA_PARITY_ERROR_STATUS 0x77f4 894#define MA_PARITY_ERROR_STATUS 0x77f4
668#define MA_PARITY_ERROR_STATUS2 0x7804 895#define MA_PARITY_ERROR_STATUS2 0x7804
669 896
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index 769968644853..ecf7459f8217 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -78,4 +78,8 @@
78#define SGE_UDB_GTS 20 78#define SGE_UDB_GTS 20
79#define SGE_UDB_WCDOORBELL 64 79#define SGE_UDB_WCDOORBELL 64
80 80
81/* PCI-E definitions */
82#define WINDOW_SHIFT_X 10
83#define PCIEOFST_SHIFT_X 10
84
81#endif /* __T4_VALUES_H__ */ 85#endif /* __T4_VALUES_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
index b645e33bbc8f..aa9f9cd7a3c7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
@@ -2294,17 +2294,17 @@ static int adap_init0(struct adapter *adapter)
2294 * threshold values from the SGE parameters. 2294 * threshold values from the SGE parameters.
2295 */ 2295 */
2296 s->timer_val[0] = core_ticks_to_us(adapter, 2296 s->timer_val[0] = core_ticks_to_us(adapter,
2297 TIMERVALUE0_GET(sge_params->sge_timer_value_0_and_1)); 2297 TIMERVALUE0_G(sge_params->sge_timer_value_0_and_1));
2298 s->timer_val[1] = core_ticks_to_us(adapter, 2298 s->timer_val[1] = core_ticks_to_us(adapter,
2299 TIMERVALUE1_GET(sge_params->sge_timer_value_0_and_1)); 2299 TIMERVALUE1_G(sge_params->sge_timer_value_0_and_1));
2300 s->timer_val[2] = core_ticks_to_us(adapter, 2300 s->timer_val[2] = core_ticks_to_us(adapter,
2301 TIMERVALUE0_GET(sge_params->sge_timer_value_2_and_3)); 2301 TIMERVALUE0_G(sge_params->sge_timer_value_2_and_3));
2302 s->timer_val[3] = core_ticks_to_us(adapter, 2302 s->timer_val[3] = core_ticks_to_us(adapter,
2303 TIMERVALUE1_GET(sge_params->sge_timer_value_2_and_3)); 2303 TIMERVALUE1_G(sge_params->sge_timer_value_2_and_3));
2304 s->timer_val[4] = core_ticks_to_us(adapter, 2304 s->timer_val[4] = core_ticks_to_us(adapter,
2305 TIMERVALUE0_GET(sge_params->sge_timer_value_4_and_5)); 2305 TIMERVALUE0_G(sge_params->sge_timer_value_4_and_5));
2306 s->timer_val[5] = core_ticks_to_us(adapter, 2306 s->timer_val[5] = core_ticks_to_us(adapter,
2307 TIMERVALUE1_GET(sge_params->sge_timer_value_4_and_5)); 2307 TIMERVALUE1_G(sge_params->sge_timer_value_4_and_5));
2308 2308
2309 s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold); 2309 s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold);
2310 s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold); 2310 s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold);
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
index 6929d1f13c8f..fa60f714e972 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
@@ -537,11 +537,11 @@ int t4vf_get_sge_params(struct adapter *adapter)
537 params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) | 537 params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
538 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A)); 538 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
539 params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) | 539 params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
540 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1)); 540 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
541 params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) | 541 params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
542 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3)); 542 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
543 params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) | 543 params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
544 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5)); 544 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
545 v = t4vf_query_params(adapter, 7, params, vals); 545 v = t4vf_query_params(adapter, 7, params, vals);
546 if (v) 546 if (v)
547 return v; 547 return v;
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c
index 890d93ac2066..04ec5867de43 100644
--- a/drivers/scsi/csiostor/csio_hw.c
+++ b/drivers/scsi/csiostor/csio_hw.c
@@ -959,8 +959,8 @@ retry:
959 * timeout ... and then retry if we haven't exhausted 959 * timeout ... and then retry if we haven't exhausted
960 * our retries ... 960 * our retries ...
961 */ 961 */
962 pcie_fw = csio_rd_reg32(hw, PCIE_FW); 962 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
963 if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) { 963 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
964 if (waiting <= 0) { 964 if (waiting <= 0) {
965 if (retries-- > 0) 965 if (retries-- > 0)
966 goto retry; 966 goto retry;
@@ -976,10 +976,10 @@ retry:
976 * report errors preferentially. 976 * report errors preferentially.
977 */ 977 */
978 if (state) { 978 if (state) {
979 if (pcie_fw & PCIE_FW_ERR) { 979 if (pcie_fw & PCIE_FW_ERR_F) {
980 *state = CSIO_DEV_STATE_ERR; 980 *state = CSIO_DEV_STATE_ERR;
981 rv = -ETIMEDOUT; 981 rv = -ETIMEDOUT;
982 } else if (pcie_fw & PCIE_FW_INIT) 982 } else if (pcie_fw & PCIE_FW_INIT_F)
983 *state = CSIO_DEV_STATE_INIT; 983 *state = CSIO_DEV_STATE_INIT;
984 } 984 }
985 985
@@ -988,9 +988,9 @@ retry:
988 * there's not a valid Master PF, grab its identity 988 * there's not a valid Master PF, grab its identity
989 * for our caller. 989 * for our caller.
990 */ 990 */
991 if (mpfn == PCIE_FW_MASTER_MASK && 991 if (mpfn == PCIE_FW_MASTER_M &&
992 (pcie_fw & PCIE_FW_MASTER_VLD)) 992 (pcie_fw & PCIE_FW_MASTER_VLD_F))
993 mpfn = PCIE_FW_MASTER_GET(pcie_fw); 993 mpfn = PCIE_FW_MASTER_G(pcie_fw);
994 break; 994 break;
995 } 995 }
996 hw->flags &= ~CSIO_HWF_MASTER; 996 hw->flags &= ~CSIO_HWF_MASTER;
@@ -1156,7 +1156,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1156 * If a legitimate mailbox is provided, issue a RESET command 1156 * If a legitimate mailbox is provided, issue a RESET command
1157 * with a HALT indication. 1157 * with a HALT indication.
1158 */ 1158 */
1159 if (mbox <= PCIE_FW_MASTER_MASK) { 1159 if (mbox <= PCIE_FW_MASTER_M) {
1160 struct csio_mb *mbp; 1160 struct csio_mb *mbp;
1161 1161
1162 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1162 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
@@ -1194,7 +1194,8 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1194 */ 1194 */
1195 if (retval == 0 || force) { 1195 if (retval == 0 || force) {
1196 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST); 1196 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST);
1197 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, PCIE_FW_HALT); 1197 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
1198 PCIE_FW_HALT_F);
1198 } 1199 }
1199 1200
1200 /* 1201 /*
@@ -1234,7 +1235,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1234 * doing it automatically, we need to clear the PCIE_FW.HALT 1235 * doing it automatically, we need to clear the PCIE_FW.HALT
1235 * bit. 1236 * bit.
1236 */ 1237 */
1237 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, 0); 1238 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
1238 1239
1239 /* 1240 /*
1240 * If we've been given a valid mailbox, first try to get the 1241 * If we've been given a valid mailbox, first try to get the
@@ -1243,7 +1244,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1243 * valid mailbox or the RESET command failed, fall back to 1244 * valid mailbox or the RESET command failed, fall back to
1244 * hitting the chip with a hammer. 1245 * hitting the chip with a hammer.
1245 */ 1246 */
1246 if (mbox <= PCIE_FW_MASTER_MASK) { 1247 if (mbox <= PCIE_FW_MASTER_M) {
1247 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1248 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
1248 msleep(100); 1249 msleep(100);
1249 if (csio_do_reset(hw, true) == 0) 1250 if (csio_do_reset(hw, true) == 0)
@@ -1257,7 +1258,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1257 1258
1258 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1259 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
1259 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 1260 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
1260 if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT)) 1261 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
1261 return 0; 1262 return 0;
1262 msleep(100); 1263 msleep(100);
1263 ms += 100; 1264 ms += 100;
@@ -2237,11 +2238,11 @@ csio_hw_intr_enable(struct csio_hw *hw)
2237 * by FW, so do nothing for INTX. 2238 * by FW, so do nothing for INTX.
2238 */ 2239 */
2239 if (hw->intr_mode == CSIO_IM_MSIX) 2240 if (hw->intr_mode == CSIO_IM_MSIX)
2240 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2241 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2241 AIVEC(AIVEC_MASK), vec); 2242 AIVEC_V(AIVEC_M), vec);
2242 else if (hw->intr_mode == CSIO_IM_MSI) 2243 else if (hw->intr_mode == CSIO_IM_MSI)
2243 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2244 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2244 AIVEC(AIVEC_MASK), 0); 2245 AIVEC_V(AIVEC_M), 0);
2245 2246
2246 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE)); 2247 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE));
2247 2248
diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h
index 3bc9cf48575d..01986623b2bd 100644
--- a/drivers/scsi/csiostor/csio_hw_chip.h
+++ b/drivers/scsi/csiostor/csio_hw_chip.h
@@ -71,10 +71,10 @@ static inline int csio_is_t5(uint16_t chip)
71 71
72#define CSIO_HW_LP_INT_THRESH(hw, val) \ 72#define CSIO_HW_LP_INT_THRESH(hw, val) \
73 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \ 73 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \
74 (V_LP_INT_THRESH_T5(val))) 74 (LP_INT_THRESH_T5_V(val)))
75 75
76#define CSIO_HW_M_LP_INT_THRESH(hw) \ 76#define CSIO_HW_M_LP_INT_THRESH(hw) \
77 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (M_LP_INT_THRESH_T5)) 77 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
78 78
79#define CSIO_MAC_INT_CAUSE_REG(hw, port) \ 79#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
80 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \ 80 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
diff --git a/drivers/scsi/csiostor/csio_hw_t4.c b/drivers/scsi/csiostor/csio_hw_t4.c
index 95d831857640..d0dac67e4a80 100644
--- a/drivers/scsi/csiostor/csio_hw_t4.c
+++ b/drivers/scsi/csiostor/csio_hw_t4.c
@@ -96,11 +96,11 @@ csio_t4_set_mem_win(struct csio_hw *hw, uint32_t win)
96 * back MA register to ensure that changes propagate before we attempt 96 * back MA register to ensure that changes propagate before we attempt
97 * to use the new values.) 97 * to use the new values.)
98 */ 98 */
99 csio_wr_reg32(hw, mem_win_base | BIR(0) | 99 csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
100 WINDOW(ilog2(MEMWIN_APERTURE) - 10), 100 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
101 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 101 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
102 csio_rd_reg32(hw, 102 csio_rd_reg32(hw,
103 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 103 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
104 return 0; 104 return 0;
105} 105}
106 106
@@ -111,69 +111,69 @@ static void
111csio_t4_pcie_intr_handler(struct csio_hw *hw) 111csio_t4_pcie_intr_handler(struct csio_hw *hw)
112{ 112{
113 static struct intr_info sysbus_intr_info[] = { 113 static struct intr_info sysbus_intr_info[] = {
114 { RNPP, "RXNP array parity error", -1, 1 }, 114 { RNPP_F, "RXNP array parity error", -1, 1 },
115 { RPCP, "RXPC array parity error", -1, 1 }, 115 { RPCP_F, "RXPC array parity error", -1, 1 },
116 { RCIP, "RXCIF array parity error", -1, 1 }, 116 { RCIP_F, "RXCIF array parity error", -1, 1 },
117 { RCCP, "Rx completions control array parity error", -1, 1 }, 117 { RCCP_F, "Rx completions control array parity error", -1, 1 },
118 { RFTP, "RXFT array parity error", -1, 1 }, 118 { RFTP_F, "RXFT array parity error", -1, 1 },
119 { 0, NULL, 0, 0 } 119 { 0, NULL, 0, 0 }
120 }; 120 };
121 static struct intr_info pcie_port_intr_info[] = { 121 static struct intr_info pcie_port_intr_info[] = {
122 { TPCP, "TXPC array parity error", -1, 1 }, 122 { TPCP_F, "TXPC array parity error", -1, 1 },
123 { TNPP, "TXNP array parity error", -1, 1 }, 123 { TNPP_F, "TXNP array parity error", -1, 1 },
124 { TFTP, "TXFT array parity error", -1, 1 }, 124 { TFTP_F, "TXFT array parity error", -1, 1 },
125 { TCAP, "TXCA array parity error", -1, 1 }, 125 { TCAP_F, "TXCA array parity error", -1, 1 },
126 { TCIP, "TXCIF array parity error", -1, 1 }, 126 { TCIP_F, "TXCIF array parity error", -1, 1 },
127 { RCAP, "RXCA array parity error", -1, 1 }, 127 { RCAP_F, "RXCA array parity error", -1, 1 },
128 { OTDD, "outbound request TLP discarded", -1, 1 }, 128 { OTDD_F, "outbound request TLP discarded", -1, 1 },
129 { RDPE, "Rx data parity error", -1, 1 }, 129 { RDPE_F, "Rx data parity error", -1, 1 },
130 { TDUE, "Tx uncorrectable data error", -1, 1 }, 130 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
131 { 0, NULL, 0, 0 } 131 { 0, NULL, 0, 0 }
132 }; 132 };
133 133
134 static struct intr_info pcie_intr_info[] = { 134 static struct intr_info pcie_intr_info[] = {
135 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 135 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
136 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 136 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
137 { MSIDATAPERR, "MSI data parity error", -1, 1 }, 137 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
138 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 138 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
139 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 139 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
140 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 140 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
141 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 141 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
142 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 142 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
143 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 143 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
144 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 144 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
145 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 145 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
146 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 146 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
147 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 147 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
148 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 148 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
149 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 149 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
150 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 150 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
151 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 151 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
152 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 152 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
153 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 153 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
154 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 154 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
155 { FIDPERR, "PCI FID parity error", -1, 1 }, 155 { FIDPERR_F, "PCI FID parity error", -1, 1 },
156 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 156 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
157 { MATAGPERR, "PCI MA tag parity error", -1, 1 }, 157 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
158 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 158 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
159 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 159 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
160 { RXWRPERR, "PCI Rx write parity error", -1, 1 }, 160 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
161 { RPLPERR, "PCI replay buffer parity error", -1, 1 }, 161 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
162 { PCIESINT, "PCI core secondary fault", -1, 1 }, 162 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
163 { PCIEPINT, "PCI core primary fault", -1, 1 }, 163 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
164 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 164 { UNXSPLCPLERR_F, "PCI unexpected split completion error", -1,
165 0 }, 165 0 },
166 { 0, NULL, 0, 0 } 166 { 0, NULL, 0, 0 }
167 }; 167 };
168 168
169 int fat; 169 int fat;
170 fat = csio_handle_intr_status(hw, 170 fat = csio_handle_intr_status(hw,
171 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 171 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
172 sysbus_intr_info) + 172 sysbus_intr_info) +
173 csio_handle_intr_status(hw, 173 csio_handle_intr_status(hw,
174 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 174 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
175 pcie_port_intr_info) + 175 pcie_port_intr_info) +
176 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info); 176 csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
177 if (fat) 177 if (fat)
178 csio_hw_fatal_err(hw); 178 csio_hw_fatal_err(hw);
179} 179}
@@ -329,9 +329,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
329 * the address is relative to BAR0. 329 * the address is relative to BAR0.
330 */ 330 */
331 mem_reg = csio_rd_reg32(hw, 331 mem_reg = csio_rd_reg32(hw,
332 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 332 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
333 mem_aperture = 1 << (WINDOW(mem_reg) + 10); 333 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
334 mem_base = GET_PCIEOFST(mem_reg) << 10; 334 mem_base = PCIEOFST_G(mem_reg) << 10;
335 335
336 bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0); 336 bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
337 bar0 &= PCI_BASE_ADDRESS_MEM_MASK; 337 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
@@ -356,9 +356,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
356 * before we attempt to use the new value. 356 * before we attempt to use the new value.
357 */ 357 */
358 csio_wr_reg32(hw, pos, 358 csio_wr_reg32(hw, pos,
359 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 359 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
360 csio_rd_reg32(hw, 360 csio_rd_reg32(hw,
361 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 361 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
362 362
363 while (offset < mem_aperture && len > 0) { 363 while (offset < mem_aperture && len > 0) {
364 if (dir) 364 if (dir)
diff --git a/drivers/scsi/csiostor/csio_hw_t5.c b/drivers/scsi/csiostor/csio_hw_t5.c
index 66e180a58718..99a7dcafc178 100644
--- a/drivers/scsi/csiostor/csio_hw_t5.c
+++ b/drivers/scsi/csiostor/csio_hw_t5.c
@@ -56,11 +56,11 @@ csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
56 * back MA register to ensure that changes propagate before we attempt 56 * back MA register to ensure that changes propagate before we attempt
57 * to use the new values.) 57 * to use the new values.)
58 */ 58 */
59 csio_wr_reg32(hw, mem_win_base | BIR(0) | 59 csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
60 WINDOW(ilog2(MEMWIN_APERTURE) - 10), 60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
62 csio_rd_reg32(hw, 62 csio_rd_reg32(hw,
63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
64 64
65 return 0; 65 return 0;
66} 66}
@@ -72,74 +72,74 @@ static void
72csio_t5_pcie_intr_handler(struct csio_hw *hw) 72csio_t5_pcie_intr_handler(struct csio_hw *hw)
73{ 73{
74 static struct intr_info sysbus_intr_info[] = { 74 static struct intr_info sysbus_intr_info[] = {
75 { RNPP, "RXNP array parity error", -1, 1 }, 75 { RNPP_F, "RXNP array parity error", -1, 1 },
76 { RPCP, "RXPC array parity error", -1, 1 }, 76 { RPCP_F, "RXPC array parity error", -1, 1 },
77 { RCIP, "RXCIF array parity error", -1, 1 }, 77 { RCIP_F, "RXCIF array parity error", -1, 1 },
78 { RCCP, "Rx completions control array parity error", -1, 1 }, 78 { RCCP_F, "Rx completions control array parity error", -1, 1 },
79 { RFTP, "RXFT array parity error", -1, 1 }, 79 { RFTP_F, "RXFT array parity error", -1, 1 },
80 { 0, NULL, 0, 0 } 80 { 0, NULL, 0, 0 }
81 }; 81 };
82 static struct intr_info pcie_port_intr_info[] = { 82 static struct intr_info pcie_port_intr_info[] = {
83 { TPCP, "TXPC array parity error", -1, 1 }, 83 { TPCP_F, "TXPC array parity error", -1, 1 },
84 { TNPP, "TXNP array parity error", -1, 1 }, 84 { TNPP_F, "TXNP array parity error", -1, 1 },
85 { TFTP, "TXFT array parity error", -1, 1 }, 85 { TFTP_F, "TXFT array parity error", -1, 1 },
86 { TCAP, "TXCA array parity error", -1, 1 }, 86 { TCAP_F, "TXCA array parity error", -1, 1 },
87 { TCIP, "TXCIF array parity error", -1, 1 }, 87 { TCIP_F, "TXCIF array parity error", -1, 1 },
88 { RCAP, "RXCA array parity error", -1, 1 }, 88 { RCAP_F, "RXCA array parity error", -1, 1 },
89 { OTDD, "outbound request TLP discarded", -1, 1 }, 89 { OTDD_F, "outbound request TLP discarded", -1, 1 },
90 { RDPE, "Rx data parity error", -1, 1 }, 90 { RDPE_F, "Rx data parity error", -1, 1 },
91 { TDUE, "Tx uncorrectable data error", -1, 1 }, 91 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
92 { 0, NULL, 0, 0 } 92 { 0, NULL, 0, 0 }
93 }; 93 };
94 94
95 static struct intr_info pcie_intr_info[] = { 95 static struct intr_info pcie_intr_info[] = {
96 { MSTGRPPERR, "Master Response Read Queue parity error", 96 { MSTGRPPERR_F, "Master Response Read Queue parity error",
97 -1, 1 }, 97 -1, 1 },
98 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 98 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
99 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 99 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
100 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 100 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
101 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 101 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
102 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 102 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
103 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 103 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
104 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 104 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
105 -1, 1 }, 105 -1, 1 },
106 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 106 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
107 -1, 1 }, 107 -1, 1 },
108 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 108 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
109 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 109 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
110 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 110 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
111 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 111 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
112 { DREQWRPERR, "PCI DMA channel write request parity error", 112 { DREQWRPERR_F, "PCI DMA channel write request parity error",
113 -1, 1 }, 113 -1, 1 },
114 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 114 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
115 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 115 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
116 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 116 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
117 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 117 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
118 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 118 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
119 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 119 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
120 { FIDPERR, "PCI FID parity error", -1, 1 }, 120 { FIDPERR_F, "PCI FID parity error", -1, 1 },
121 { VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 121 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
122 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 122 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
123 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 123 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
124 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 124 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
125 -1, 1 }, 125 -1, 1 },
126 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 126 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
127 -1, 1 }, 127 -1, 1 },
128 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 128 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
129 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 129 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
130 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 130 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
131 { READRSPERR, "Outbound read error", -1, 0 }, 131 { READRSPERR_F, "Outbound read error", -1, 0 },
132 { 0, NULL, 0, 0 } 132 { 0, NULL, 0, 0 }
133 }; 133 };
134 134
135 int fat; 135 int fat;
136 fat = csio_handle_intr_status(hw, 136 fat = csio_handle_intr_status(hw,
137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
138 sysbus_intr_info) + 138 sysbus_intr_info) +
139 csio_handle_intr_status(hw, 139 csio_handle_intr_status(hw,
140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
141 pcie_port_intr_info) + 141 pcie_port_intr_info) +
142 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info); 142 csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
143 if (fat) 143 if (fat)
144 csio_hw_fatal_err(hw); 144 csio_hw_fatal_err(hw);
145} 145}
@@ -320,13 +320,13 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
320 * the address is relative to BAR0. 320 * the address is relative to BAR0.
321 */ 321 */
322 mem_reg = csio_rd_reg32(hw, 322 mem_reg = csio_rd_reg32(hw,
323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
324 mem_aperture = 1 << (WINDOW(mem_reg) + 10); 324 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
325 mem_base = GET_PCIEOFST(mem_reg) << 10; 325 mem_base = PCIEOFST_G(mem_reg) << 10;
326 326
327 start = addr & ~(mem_aperture-1); 327 start = addr & ~(mem_aperture-1);
328 offset = addr - start; 328 offset = addr - start;
329 win_pf = V_PFNUM(hw->pfn); 329 win_pf = PFNUM_V(hw->pfn);
330 330
331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n", 331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
332 mem_reg, mem_aperture); 332 mem_reg, mem_aperture);
@@ -344,9 +344,9 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
344 * before we attempt to use the new value. 344 * before we attempt to use the new value.
345 */ 345 */
346 csio_wr_reg32(hw, pos | win_pf, 346 csio_wr_reg32(hw, pos | win_pf,
347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
348 csio_rd_reg32(hw, 348 csio_rd_reg32(hw,
349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
350 350
351 while (offset < mem_aperture && len > 0) { 351 while (offset < mem_aperture && len > 0) {
352 if (dir) 352 if (dir)
diff --git a/drivers/scsi/csiostor/csio_isr.c b/drivers/scsi/csiostor/csio_isr.c
index a8c748a35f9c..2fb71c6c3b37 100644
--- a/drivers/scsi/csiostor/csio_isr.c
+++ b/drivers/scsi/csiostor/csio_isr.c
@@ -317,7 +317,7 @@ csio_fcoe_isr(int irq, void *dev_id)
317 317
318 /* Disable the interrupt for this PCI function. */ 318 /* Disable the interrupt for this PCI function. */
319 if (hw->intr_mode == CSIO_IM_INTX) 319 if (hw->intr_mode == CSIO_IM_INTX)
320 csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI)); 320 csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A));
321 321
322 /* 322 /*
323 * The read in the following function will flush the 323 * The read in the following function will flush the
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c
index 221433f75ee6..12697c6f2519 100644
--- a/drivers/scsi/csiostor/csio_wr.c
+++ b/drivers/scsi/csiostor/csio_wr.c
@@ -1412,22 +1412,22 @@ csio_wr_get_sge(struct csio_hw *hw)
1412 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++) 1412 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
1413 csio_get_flbuf_size(hw, sge, i); 1413 csio_get_flbuf_size(hw, sge, i);
1414 1414
1415 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1); 1415 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A);
1416 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3); 1416 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A);
1417 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5); 1417 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A);
1418 1418
1419 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw, 1419 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
1420 TIMERVALUE0_GET(timer_value_0_and_1)); 1420 TIMERVALUE0_G(timer_value_0_and_1));
1421 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw, 1421 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
1422 TIMERVALUE1_GET(timer_value_0_and_1)); 1422 TIMERVALUE1_G(timer_value_0_and_1));
1423 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw, 1423 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
1424 TIMERVALUE2_GET(timer_value_2_and_3)); 1424 TIMERVALUE2_G(timer_value_2_and_3));
1425 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw, 1425 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
1426 TIMERVALUE3_GET(timer_value_2_and_3)); 1426 TIMERVALUE3_G(timer_value_2_and_3));
1427 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw, 1427 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
1428 TIMERVALUE4_GET(timer_value_4_and_5)); 1428 TIMERVALUE4_G(timer_value_4_and_5));
1429 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw, 1429 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
1430 TIMERVALUE5_GET(timer_value_4_and_5)); 1430 TIMERVALUE5_G(timer_value_4_and_5));
1431 1431
1432 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A); 1432 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A);
1433 sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); 1433 sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
@@ -1513,19 +1513,19 @@ csio_wr_set_sge(struct csio_hw *hw)
1513 SGE_INGRESS_RX_THRESHOLD_A); 1513 SGE_INGRESS_RX_THRESHOLD_A);
1514 1514
1515 csio_wr_reg32(hw, 1515 csio_wr_reg32(hw,
1516 TIMERVALUE0(csio_us_to_core_ticks(hw, sge->timer_val[0])) | 1516 TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
1517 TIMERVALUE1(csio_us_to_core_ticks(hw, sge->timer_val[1])), 1517 TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),
1518 SGE_TIMER_VALUE_0_AND_1); 1518 SGE_TIMER_VALUE_0_AND_1_A);
1519 1519
1520 csio_wr_reg32(hw, 1520 csio_wr_reg32(hw,
1521 TIMERVALUE2(csio_us_to_core_ticks(hw, sge->timer_val[2])) | 1521 TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
1522 TIMERVALUE3(csio_us_to_core_ticks(hw, sge->timer_val[3])), 1522 TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),
1523 SGE_TIMER_VALUE_2_AND_3); 1523 SGE_TIMER_VALUE_2_AND_3_A);
1524 1524
1525 csio_wr_reg32(hw, 1525 csio_wr_reg32(hw,
1526 TIMERVALUE4(csio_us_to_core_ticks(hw, sge->timer_val[4])) | 1526 TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
1527 TIMERVALUE5(csio_us_to_core_ticks(hw, sge->timer_val[5])), 1527 TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),
1528 SGE_TIMER_VALUE_4_AND_5); 1528 SGE_TIMER_VALUE_4_AND_5_A);
1529 1529
1530 csio_init_intr_coalesce_parms(hw); 1530 csio_init_intr_coalesce_parms(hw);
1531} 1531}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 22:40:16 -0500