diff options
author | Paul Walmsley <paul@pwsan.com> | 2010-12-21 17:30:56 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2010-12-21 22:56:50 -0500 |
commit | f0611a5c220e50dec65041b10bd2fe9484f061a6 (patch) | |
tree | f94ba2787f721a38ad57d22638c5561318d31f26 | |
parent | 59fb659b065f52fcc2deed293cfbfc58f890376c (diff) |
OMAP3: PRM/CM: separate CM context save/restore; remove PRM context save/restore
The OMAP3 PRM module is in the WKUP powerdomain, which is always
powered when the chip is powered, so it shouldn't be necessary to save
and restore those PRM registers. Remove the PRM register save/restore
code, which should save several microseconds during off-mode
entry/exit, since PRM register accesses are relatively slow.
While doing so, move the CM register save/restore code into
CM-specific code. The CM module has been distinct from the PRM module
since 2430.
This patch includes some minor changes to pm34xx.c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/cm2xxx_3xxx.c | 296 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm2xxx_3xxx.h | 7 | ||||
-rw-r--r-- | arch/arm/mach-omap2/pm34xx.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prcm.c | 375 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm2xxx_3xxx.c | 1 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/prcm.h | 3 |
6 files changed, 304 insertions, 382 deletions
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 5978ce426ec5..1c98dfc93a83 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c | |||
@@ -29,7 +29,6 @@ static const u8 cm_idlest_offs[] = { | |||
29 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 | 29 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 |
30 | }; | 30 | }; |
31 | 31 | ||
32 | |||
33 | u32 cm_read_mod_reg(s16 module, u16 idx) | 32 | u32 cm_read_mod_reg(s16 module, u16 idx) |
34 | { | 33 | { |
35 | return __raw_readl(cm_base + module + idx); | 34 | return __raw_readl(cm_base + module + idx); |
@@ -97,3 +96,298 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | |||
97 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | 96 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
98 | } | 97 | } |
99 | 98 | ||
99 | /* | ||
100 | * Context save/restore code - OMAP3 only | ||
101 | */ | ||
102 | #ifdef CONFIG_ARCH_OMAP3 | ||
103 | struct omap3_cm_regs { | ||
104 | u32 iva2_cm_clksel1; | ||
105 | u32 iva2_cm_clksel2; | ||
106 | u32 cm_sysconfig; | ||
107 | u32 sgx_cm_clksel; | ||
108 | u32 dss_cm_clksel; | ||
109 | u32 cam_cm_clksel; | ||
110 | u32 per_cm_clksel; | ||
111 | u32 emu_cm_clksel; | ||
112 | u32 emu_cm_clkstctrl; | ||
113 | u32 pll_cm_autoidle2; | ||
114 | u32 pll_cm_clksel4; | ||
115 | u32 pll_cm_clksel5; | ||
116 | u32 pll_cm_clken2; | ||
117 | u32 cm_polctrl; | ||
118 | u32 iva2_cm_fclken; | ||
119 | u32 iva2_cm_clken_pll; | ||
120 | u32 core_cm_fclken1; | ||
121 | u32 core_cm_fclken3; | ||
122 | u32 sgx_cm_fclken; | ||
123 | u32 wkup_cm_fclken; | ||
124 | u32 dss_cm_fclken; | ||
125 | u32 cam_cm_fclken; | ||
126 | u32 per_cm_fclken; | ||
127 | u32 usbhost_cm_fclken; | ||
128 | u32 core_cm_iclken1; | ||
129 | u32 core_cm_iclken2; | ||
130 | u32 core_cm_iclken3; | ||
131 | u32 sgx_cm_iclken; | ||
132 | u32 wkup_cm_iclken; | ||
133 | u32 dss_cm_iclken; | ||
134 | u32 cam_cm_iclken; | ||
135 | u32 per_cm_iclken; | ||
136 | u32 usbhost_cm_iclken; | ||
137 | u32 iva2_cm_autoidle2; | ||
138 | u32 mpu_cm_autoidle2; | ||
139 | u32 iva2_cm_clkstctrl; | ||
140 | u32 mpu_cm_clkstctrl; | ||
141 | u32 core_cm_clkstctrl; | ||
142 | u32 sgx_cm_clkstctrl; | ||
143 | u32 dss_cm_clkstctrl; | ||
144 | u32 cam_cm_clkstctrl; | ||
145 | u32 per_cm_clkstctrl; | ||
146 | u32 neon_cm_clkstctrl; | ||
147 | u32 usbhost_cm_clkstctrl; | ||
148 | u32 core_cm_autoidle1; | ||
149 | u32 core_cm_autoidle2; | ||
150 | u32 core_cm_autoidle3; | ||
151 | u32 wkup_cm_autoidle; | ||
152 | u32 dss_cm_autoidle; | ||
153 | u32 cam_cm_autoidle; | ||
154 | u32 per_cm_autoidle; | ||
155 | u32 usbhost_cm_autoidle; | ||
156 | u32 sgx_cm_sleepdep; | ||
157 | u32 dss_cm_sleepdep; | ||
158 | u32 cam_cm_sleepdep; | ||
159 | u32 per_cm_sleepdep; | ||
160 | u32 usbhost_cm_sleepdep; | ||
161 | u32 cm_clkout_ctrl; | ||
162 | }; | ||
163 | |||
164 | static struct omap3_cm_regs cm_context; | ||
165 | |||
166 | void omap3_cm_save_context(void) | ||
167 | { | ||
168 | cm_context.iva2_cm_clksel1 = | ||
169 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); | ||
170 | cm_context.iva2_cm_clksel2 = | ||
171 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); | ||
172 | cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); | ||
173 | cm_context.sgx_cm_clksel = | ||
174 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); | ||
175 | cm_context.dss_cm_clksel = | ||
176 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); | ||
177 | cm_context.cam_cm_clksel = | ||
178 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); | ||
179 | cm_context.per_cm_clksel = | ||
180 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); | ||
181 | cm_context.emu_cm_clksel = | ||
182 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | ||
183 | cm_context.emu_cm_clkstctrl = | ||
184 | cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); | ||
185 | cm_context.pll_cm_autoidle2 = | ||
186 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | ||
187 | cm_context.pll_cm_clksel4 = | ||
188 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); | ||
189 | cm_context.pll_cm_clksel5 = | ||
190 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); | ||
191 | cm_context.pll_cm_clken2 = | ||
192 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); | ||
193 | cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); | ||
194 | cm_context.iva2_cm_fclken = | ||
195 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
196 | cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, | ||
197 | OMAP3430_CM_CLKEN_PLL); | ||
198 | cm_context.core_cm_fclken1 = | ||
199 | cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | ||
200 | cm_context.core_cm_fclken3 = | ||
201 | cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); | ||
202 | cm_context.sgx_cm_fclken = | ||
203 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); | ||
204 | cm_context.wkup_cm_fclken = | ||
205 | cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); | ||
206 | cm_context.dss_cm_fclken = | ||
207 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); | ||
208 | cm_context.cam_cm_fclken = | ||
209 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); | ||
210 | cm_context.per_cm_fclken = | ||
211 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); | ||
212 | cm_context.usbhost_cm_fclken = | ||
213 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
214 | cm_context.core_cm_iclken1 = | ||
215 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); | ||
216 | cm_context.core_cm_iclken2 = | ||
217 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); | ||
218 | cm_context.core_cm_iclken3 = | ||
219 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); | ||
220 | cm_context.sgx_cm_iclken = | ||
221 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); | ||
222 | cm_context.wkup_cm_iclken = | ||
223 | cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); | ||
224 | cm_context.dss_cm_iclken = | ||
225 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); | ||
226 | cm_context.cam_cm_iclken = | ||
227 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); | ||
228 | cm_context.per_cm_iclken = | ||
229 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); | ||
230 | cm_context.usbhost_cm_iclken = | ||
231 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
232 | cm_context.iva2_cm_autoidle2 = | ||
233 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
234 | cm_context.mpu_cm_autoidle2 = | ||
235 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | ||
236 | cm_context.iva2_cm_clkstctrl = | ||
237 | cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); | ||
238 | cm_context.mpu_cm_clkstctrl = | ||
239 | cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); | ||
240 | cm_context.core_cm_clkstctrl = | ||
241 | cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); | ||
242 | cm_context.sgx_cm_clkstctrl = | ||
243 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); | ||
244 | cm_context.dss_cm_clkstctrl = | ||
245 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); | ||
246 | cm_context.cam_cm_clkstctrl = | ||
247 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); | ||
248 | cm_context.per_cm_clkstctrl = | ||
249 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); | ||
250 | cm_context.neon_cm_clkstctrl = | ||
251 | cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); | ||
252 | cm_context.usbhost_cm_clkstctrl = | ||
253 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | ||
254 | cm_context.core_cm_autoidle1 = | ||
255 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | ||
256 | cm_context.core_cm_autoidle2 = | ||
257 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); | ||
258 | cm_context.core_cm_autoidle3 = | ||
259 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); | ||
260 | cm_context.wkup_cm_autoidle = | ||
261 | cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); | ||
262 | cm_context.dss_cm_autoidle = | ||
263 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); | ||
264 | cm_context.cam_cm_autoidle = | ||
265 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); | ||
266 | cm_context.per_cm_autoidle = | ||
267 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
268 | cm_context.usbhost_cm_autoidle = | ||
269 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
270 | cm_context.sgx_cm_sleepdep = | ||
271 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); | ||
272 | cm_context.dss_cm_sleepdep = | ||
273 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); | ||
274 | cm_context.cam_cm_sleepdep = | ||
275 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); | ||
276 | cm_context.per_cm_sleepdep = | ||
277 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); | ||
278 | cm_context.usbhost_cm_sleepdep = | ||
279 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
280 | cm_context.cm_clkout_ctrl = | ||
281 | cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
282 | } | ||
283 | |||
284 | void omap3_cm_restore_context(void) | ||
285 | { | ||
286 | cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, | ||
287 | CM_CLKSEL1); | ||
288 | cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | ||
289 | CM_CLKSEL2); | ||
290 | __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); | ||
291 | cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, | ||
292 | CM_CLKSEL); | ||
293 | cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | ||
294 | CM_CLKSEL); | ||
295 | cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | ||
296 | CM_CLKSEL); | ||
297 | cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, | ||
298 | CM_CLKSEL); | ||
299 | cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | ||
300 | CM_CLKSEL1); | ||
301 | cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | ||
302 | OMAP2_CM_CLKSTCTRL); | ||
303 | cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, | ||
304 | CM_AUTOIDLE2); | ||
305 | cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, | ||
306 | OMAP3430ES2_CM_CLKSEL4); | ||
307 | cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, | ||
308 | OMAP3430ES2_CM_CLKSEL5); | ||
309 | cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, | ||
310 | OMAP3430ES2_CM_CLKEN2); | ||
311 | __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); | ||
312 | cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, | ||
313 | CM_FCLKEN); | ||
314 | cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | ||
315 | OMAP3430_CM_CLKEN_PLL); | ||
316 | cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); | ||
317 | cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, | ||
318 | OMAP3430ES2_CM_FCLKEN3); | ||
319 | cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | ||
320 | CM_FCLKEN); | ||
321 | cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | ||
322 | cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | ||
323 | CM_FCLKEN); | ||
324 | cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | ||
325 | CM_FCLKEN); | ||
326 | cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, | ||
327 | CM_FCLKEN); | ||
328 | cm_write_mod_reg(cm_context.usbhost_cm_fclken, | ||
329 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
330 | cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); | ||
331 | cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); | ||
332 | cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); | ||
333 | cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | ||
334 | CM_ICLKEN); | ||
335 | cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | ||
336 | cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | ||
337 | CM_ICLKEN); | ||
338 | cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | ||
339 | CM_ICLKEN); | ||
340 | cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, | ||
341 | CM_ICLKEN); | ||
342 | cm_write_mod_reg(cm_context.usbhost_cm_iclken, | ||
343 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
344 | cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, | ||
345 | CM_AUTOIDLE2); | ||
346 | cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | ||
347 | cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | ||
348 | OMAP2_CM_CLKSTCTRL); | ||
349 | cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, | ||
350 | OMAP2_CM_CLKSTCTRL); | ||
351 | cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, | ||
352 | OMAP2_CM_CLKSTCTRL); | ||
353 | cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | ||
354 | OMAP2_CM_CLKSTCTRL); | ||
355 | cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | ||
356 | OMAP2_CM_CLKSTCTRL); | ||
357 | cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | ||
358 | OMAP2_CM_CLKSTCTRL); | ||
359 | cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | ||
360 | OMAP2_CM_CLKSTCTRL); | ||
361 | cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | ||
362 | OMAP2_CM_CLKSTCTRL); | ||
363 | cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, | ||
364 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | ||
365 | cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, | ||
366 | CM_AUTOIDLE1); | ||
367 | cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, | ||
368 | CM_AUTOIDLE2); | ||
369 | cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, | ||
370 | CM_AUTOIDLE3); | ||
371 | cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); | ||
372 | cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | ||
373 | CM_AUTOIDLE); | ||
374 | cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | ||
375 | CM_AUTOIDLE); | ||
376 | cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, | ||
377 | CM_AUTOIDLE); | ||
378 | cm_write_mod_reg(cm_context.usbhost_cm_autoidle, | ||
379 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
380 | cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | ||
381 | OMAP3430_CM_SLEEPDEP); | ||
382 | cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | ||
383 | OMAP3430_CM_SLEEPDEP); | ||
384 | cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | ||
385 | OMAP3430_CM_SLEEPDEP); | ||
386 | cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | ||
387 | OMAP3430_CM_SLEEPDEP); | ||
388 | cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, | ||
389 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
390 | cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
391 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
392 | } | ||
393 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 5e572112be06..ce2582c1441b 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h | |||
@@ -128,4 +128,11 @@ extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); | |||
128 | /* CM_IDLEST_GFX */ | 128 | /* CM_IDLEST_GFX */ |
129 | #define OMAP_ST_GFX_MASK (1 << 0) | 129 | #define OMAP_ST_GFX_MASK (1 << 0) |
130 | 130 | ||
131 | |||
132 | /* Function prototypes */ | ||
133 | # ifndef __ASSEMBLER__ | ||
134 | extern void omap3_cm_save_context(void); | ||
135 | extern void omap3_cm_restore_context(void); | ||
136 | # endif | ||
137 | |||
131 | #endif | 138 | #endif |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7e500d892804..cfff321c747e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -424,7 +424,7 @@ void omap_sram_idle(void) | |||
424 | omap_uart_prepare_idle(1); | 424 | omap_uart_prepare_idle(1); |
425 | if (core_next_state == PWRDM_POWER_OFF) { | 425 | if (core_next_state == PWRDM_POWER_OFF) { |
426 | omap3_core_save_context(); | 426 | omap3_core_save_context(); |
427 | omap3_prcm_save_context(); | 427 | omap3_cm_save_context(); |
428 | } | 428 | } |
429 | } | 429 | } |
430 | 430 | ||
@@ -464,7 +464,7 @@ void omap_sram_idle(void) | |||
464 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); | 464 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
465 | if (core_prev_state == PWRDM_POWER_OFF) { | 465 | if (core_prev_state == PWRDM_POWER_OFF) { |
466 | omap3_core_restore_context(); | 466 | omap3_core_restore_context(); |
467 | omap3_prcm_restore_context(); | 467 | omap3_cm_restore_context(); |
468 | omap3_sram_restore_context(); | 468 | omap3_sram_restore_context(); |
469 | omap2_sms_restore_context(); | 469 | omap2_sms_restore_context(); |
470 | } | 470 | } |
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 171c710c8221..dd95cbbdecc7 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
@@ -43,85 +43,6 @@ void __iomem *cm2_base; | |||
43 | 43 | ||
44 | #define MAX_MODULE_ENABLE_WAIT 100000 | 44 | #define MAX_MODULE_ENABLE_WAIT 100000 |
45 | 45 | ||
46 | struct omap3_prcm_regs { | ||
47 | u32 iva2_cm_clksel1; | ||
48 | u32 iva2_cm_clksel2; | ||
49 | u32 cm_sysconfig; | ||
50 | u32 sgx_cm_clksel; | ||
51 | u32 dss_cm_clksel; | ||
52 | u32 cam_cm_clksel; | ||
53 | u32 per_cm_clksel; | ||
54 | u32 emu_cm_clksel; | ||
55 | u32 emu_cm_clkstctrl; | ||
56 | u32 pll_cm_autoidle2; | ||
57 | u32 pll_cm_clksel4; | ||
58 | u32 pll_cm_clksel5; | ||
59 | u32 pll_cm_clken2; | ||
60 | u32 cm_polctrl; | ||
61 | u32 iva2_cm_fclken; | ||
62 | u32 iva2_cm_clken_pll; | ||
63 | u32 core_cm_fclken1; | ||
64 | u32 core_cm_fclken3; | ||
65 | u32 sgx_cm_fclken; | ||
66 | u32 wkup_cm_fclken; | ||
67 | u32 dss_cm_fclken; | ||
68 | u32 cam_cm_fclken; | ||
69 | u32 per_cm_fclken; | ||
70 | u32 usbhost_cm_fclken; | ||
71 | u32 core_cm_iclken1; | ||
72 | u32 core_cm_iclken2; | ||
73 | u32 core_cm_iclken3; | ||
74 | u32 sgx_cm_iclken; | ||
75 | u32 wkup_cm_iclken; | ||
76 | u32 dss_cm_iclken; | ||
77 | u32 cam_cm_iclken; | ||
78 | u32 per_cm_iclken; | ||
79 | u32 usbhost_cm_iclken; | ||
80 | u32 iva2_cm_autiidle2; | ||
81 | u32 mpu_cm_autoidle2; | ||
82 | u32 iva2_cm_clkstctrl; | ||
83 | u32 mpu_cm_clkstctrl; | ||
84 | u32 core_cm_clkstctrl; | ||
85 | u32 sgx_cm_clkstctrl; | ||
86 | u32 dss_cm_clkstctrl; | ||
87 | u32 cam_cm_clkstctrl; | ||
88 | u32 per_cm_clkstctrl; | ||
89 | u32 neon_cm_clkstctrl; | ||
90 | u32 usbhost_cm_clkstctrl; | ||
91 | u32 core_cm_autoidle1; | ||
92 | u32 core_cm_autoidle2; | ||
93 | u32 core_cm_autoidle3; | ||
94 | u32 wkup_cm_autoidle; | ||
95 | u32 dss_cm_autoidle; | ||
96 | u32 cam_cm_autoidle; | ||
97 | u32 per_cm_autoidle; | ||
98 | u32 usbhost_cm_autoidle; | ||
99 | u32 sgx_cm_sleepdep; | ||
100 | u32 dss_cm_sleepdep; | ||
101 | u32 cam_cm_sleepdep; | ||
102 | u32 per_cm_sleepdep; | ||
103 | u32 usbhost_cm_sleepdep; | ||
104 | u32 cm_clkout_ctrl; | ||
105 | u32 prm_clkout_ctrl; | ||
106 | u32 sgx_pm_wkdep; | ||
107 | u32 dss_pm_wkdep; | ||
108 | u32 cam_pm_wkdep; | ||
109 | u32 per_pm_wkdep; | ||
110 | u32 neon_pm_wkdep; | ||
111 | u32 usbhost_pm_wkdep; | ||
112 | u32 core_pm_mpugrpsel1; | ||
113 | u32 iva2_pm_ivagrpsel1; | ||
114 | u32 core_pm_mpugrpsel3; | ||
115 | u32 core_pm_ivagrpsel3; | ||
116 | u32 wkup_pm_mpugrpsel; | ||
117 | u32 wkup_pm_ivagrpsel; | ||
118 | u32 per_pm_mpugrpsel; | ||
119 | u32 per_pm_ivagrpsel; | ||
120 | u32 wkup_pm_wken; | ||
121 | }; | ||
122 | |||
123 | static struct omap3_prcm_regs prcm_context; | ||
124 | |||
125 | u32 omap_prcm_get_reset_sources(void) | 46 | u32 omap_prcm_get_reset_sources(void) |
126 | { | 47 | { |
127 | /* XXX This presumably needs modification for 34XX */ | 48 | /* XXX This presumably needs modification for 34XX */ |
@@ -238,299 +159,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | |||
238 | WARN_ON(!cm2_base); | 159 | WARN_ON(!cm2_base); |
239 | } | 160 | } |
240 | } | 161 | } |
241 | |||
242 | #ifdef CONFIG_ARCH_OMAP3 | ||
243 | void omap3_prcm_save_context(void) | ||
244 | { | ||
245 | prcm_context.iva2_cm_clksel1 = | ||
246 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); | ||
247 | prcm_context.iva2_cm_clksel2 = | ||
248 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); | ||
249 | prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); | ||
250 | prcm_context.sgx_cm_clksel = | ||
251 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); | ||
252 | prcm_context.dss_cm_clksel = | ||
253 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); | ||
254 | prcm_context.cam_cm_clksel = | ||
255 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); | ||
256 | prcm_context.per_cm_clksel = | ||
257 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); | ||
258 | prcm_context.emu_cm_clksel = | ||
259 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | ||
260 | prcm_context.emu_cm_clkstctrl = | ||
261 | cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); | ||
262 | prcm_context.pll_cm_autoidle2 = | ||
263 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | ||
264 | prcm_context.pll_cm_clksel4 = | ||
265 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); | ||
266 | prcm_context.pll_cm_clksel5 = | ||
267 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); | ||
268 | prcm_context.pll_cm_clken2 = | ||
269 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); | ||
270 | prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); | ||
271 | prcm_context.iva2_cm_fclken = | ||
272 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
273 | prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, | ||
274 | OMAP3430_CM_CLKEN_PLL); | ||
275 | prcm_context.core_cm_fclken1 = | ||
276 | cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | ||
277 | prcm_context.core_cm_fclken3 = | ||
278 | cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); | ||
279 | prcm_context.sgx_cm_fclken = | ||
280 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); | ||
281 | prcm_context.wkup_cm_fclken = | ||
282 | cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); | ||
283 | prcm_context.dss_cm_fclken = | ||
284 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); | ||
285 | prcm_context.cam_cm_fclken = | ||
286 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); | ||
287 | prcm_context.per_cm_fclken = | ||
288 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); | ||
289 | prcm_context.usbhost_cm_fclken = | ||
290 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
291 | prcm_context.core_cm_iclken1 = | ||
292 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); | ||
293 | prcm_context.core_cm_iclken2 = | ||
294 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); | ||
295 | prcm_context.core_cm_iclken3 = | ||
296 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); | ||
297 | prcm_context.sgx_cm_iclken = | ||
298 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); | ||
299 | prcm_context.wkup_cm_iclken = | ||
300 | cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); | ||
301 | prcm_context.dss_cm_iclken = | ||
302 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); | ||
303 | prcm_context.cam_cm_iclken = | ||
304 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); | ||
305 | prcm_context.per_cm_iclken = | ||
306 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); | ||
307 | prcm_context.usbhost_cm_iclken = | ||
308 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
309 | prcm_context.iva2_cm_autiidle2 = | ||
310 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
311 | prcm_context.mpu_cm_autoidle2 = | ||
312 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | ||
313 | prcm_context.iva2_cm_clkstctrl = | ||
314 | cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); | ||
315 | prcm_context.mpu_cm_clkstctrl = | ||
316 | cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); | ||
317 | prcm_context.core_cm_clkstctrl = | ||
318 | cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); | ||
319 | prcm_context.sgx_cm_clkstctrl = | ||
320 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, | ||
321 | OMAP2_CM_CLKSTCTRL); | ||
322 | prcm_context.dss_cm_clkstctrl = | ||
323 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); | ||
324 | prcm_context.cam_cm_clkstctrl = | ||
325 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); | ||
326 | prcm_context.per_cm_clkstctrl = | ||
327 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); | ||
328 | prcm_context.neon_cm_clkstctrl = | ||
329 | cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); | ||
330 | prcm_context.usbhost_cm_clkstctrl = | ||
331 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | ||
332 | OMAP2_CM_CLKSTCTRL); | ||
333 | prcm_context.core_cm_autoidle1 = | ||
334 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | ||
335 | prcm_context.core_cm_autoidle2 = | ||
336 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); | ||
337 | prcm_context.core_cm_autoidle3 = | ||
338 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); | ||
339 | prcm_context.wkup_cm_autoidle = | ||
340 | cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); | ||
341 | prcm_context.dss_cm_autoidle = | ||
342 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); | ||
343 | prcm_context.cam_cm_autoidle = | ||
344 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); | ||
345 | prcm_context.per_cm_autoidle = | ||
346 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
347 | prcm_context.usbhost_cm_autoidle = | ||
348 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
349 | prcm_context.sgx_cm_sleepdep = | ||
350 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); | ||
351 | prcm_context.dss_cm_sleepdep = | ||
352 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); | ||
353 | prcm_context.cam_cm_sleepdep = | ||
354 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); | ||
355 | prcm_context.per_cm_sleepdep = | ||
356 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); | ||
357 | prcm_context.usbhost_cm_sleepdep = | ||
358 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
359 | prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, | ||
360 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
361 | prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
362 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
363 | prcm_context.sgx_pm_wkdep = | ||
364 | prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); | ||
365 | prcm_context.dss_pm_wkdep = | ||
366 | prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); | ||
367 | prcm_context.cam_pm_wkdep = | ||
368 | prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); | ||
369 | prcm_context.per_pm_wkdep = | ||
370 | prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); | ||
371 | prcm_context.neon_pm_wkdep = | ||
372 | prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); | ||
373 | prcm_context.usbhost_pm_wkdep = | ||
374 | prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
375 | prcm_context.core_pm_mpugrpsel1 = | ||
376 | prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); | ||
377 | prcm_context.iva2_pm_ivagrpsel1 = | ||
378 | prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); | ||
379 | prcm_context.core_pm_mpugrpsel3 = | ||
380 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); | ||
381 | prcm_context.core_pm_ivagrpsel3 = | ||
382 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | ||
383 | prcm_context.wkup_pm_mpugrpsel = | ||
384 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | ||
385 | prcm_context.wkup_pm_ivagrpsel = | ||
386 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | ||
387 | prcm_context.per_pm_mpugrpsel = | ||
388 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | ||
389 | prcm_context.per_pm_ivagrpsel = | ||
390 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | ||
391 | prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); | ||
392 | return; | ||
393 | } | ||
394 | |||
395 | void omap3_prcm_restore_context(void) | ||
396 | { | ||
397 | cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, | ||
398 | CM_CLKSEL1); | ||
399 | cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | ||
400 | CM_CLKSEL2); | ||
401 | __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); | ||
402 | cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, | ||
403 | CM_CLKSEL); | ||
404 | cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | ||
405 | CM_CLKSEL); | ||
406 | cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | ||
407 | CM_CLKSEL); | ||
408 | cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD, | ||
409 | CM_CLKSEL); | ||
410 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | ||
411 | CM_CLKSEL1); | ||
412 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | ||
413 | OMAP2_CM_CLKSTCTRL); | ||
414 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, | ||
415 | CM_AUTOIDLE2); | ||
416 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, | ||
417 | OMAP3430ES2_CM_CLKSEL4); | ||
418 | cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, | ||
419 | OMAP3430ES2_CM_CLKSEL5); | ||
420 | cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, | ||
421 | OMAP3430ES2_CM_CLKEN2); | ||
422 | __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); | ||
423 | cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, | ||
424 | CM_FCLKEN); | ||
425 | cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | ||
426 | OMAP3430_CM_CLKEN_PLL); | ||
427 | cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); | ||
428 | cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD, | ||
429 | OMAP3430ES2_CM_FCLKEN3); | ||
430 | cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | ||
431 | CM_FCLKEN); | ||
432 | cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | ||
433 | cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | ||
434 | CM_FCLKEN); | ||
435 | cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | ||
436 | CM_FCLKEN); | ||
437 | cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD, | ||
438 | CM_FCLKEN); | ||
439 | cm_write_mod_reg(prcm_context.usbhost_cm_fclken, | ||
440 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
441 | cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); | ||
442 | cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); | ||
443 | cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); | ||
444 | cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | ||
445 | CM_ICLKEN); | ||
446 | cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | ||
447 | cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | ||
448 | CM_ICLKEN); | ||
449 | cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | ||
450 | CM_ICLKEN); | ||
451 | cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD, | ||
452 | CM_ICLKEN); | ||
453 | cm_write_mod_reg(prcm_context.usbhost_cm_iclken, | ||
454 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
455 | cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, | ||
456 | CM_AUTOIDLE2); | ||
457 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | ||
458 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | ||
459 | OMAP2_CM_CLKSTCTRL); | ||
460 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, | ||
461 | OMAP2_CM_CLKSTCTRL); | ||
462 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, | ||
463 | OMAP2_CM_CLKSTCTRL); | ||
464 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | ||
465 | OMAP2_CM_CLKSTCTRL); | ||
466 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | ||
467 | OMAP2_CM_CLKSTCTRL); | ||
468 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | ||
469 | OMAP2_CM_CLKSTCTRL); | ||
470 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | ||
471 | OMAP2_CM_CLKSTCTRL); | ||
472 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | ||
473 | OMAP2_CM_CLKSTCTRL); | ||
474 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, | ||
475 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | ||
476 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, | ||
477 | CM_AUTOIDLE1); | ||
478 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, | ||
479 | CM_AUTOIDLE2); | ||
480 | cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD, | ||
481 | CM_AUTOIDLE3); | ||
482 | cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); | ||
483 | cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | ||
484 | CM_AUTOIDLE); | ||
485 | cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | ||
486 | CM_AUTOIDLE); | ||
487 | cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD, | ||
488 | CM_AUTOIDLE); | ||
489 | cm_write_mod_reg(prcm_context.usbhost_cm_autoidle, | ||
490 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
491 | cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | ||
492 | OMAP3430_CM_SLEEPDEP); | ||
493 | cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | ||
494 | OMAP3430_CM_SLEEPDEP); | ||
495 | cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | ||
496 | OMAP3430_CM_SLEEPDEP); | ||
497 | cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | ||
498 | OMAP3430_CM_SLEEPDEP); | ||
499 | cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep, | ||
500 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
501 | cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
502 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
503 | prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
504 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
505 | prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD, | ||
506 | PM_WKDEP); | ||
507 | prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD, | ||
508 | PM_WKDEP); | ||
509 | prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD, | ||
510 | PM_WKDEP); | ||
511 | prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD, | ||
512 | PM_WKDEP); | ||
513 | prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD, | ||
514 | PM_WKDEP); | ||
515 | prm_write_mod_reg(prcm_context.usbhost_pm_wkdep, | ||
516 | OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
517 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD, | ||
518 | OMAP3430_PM_MPUGRPSEL1); | ||
519 | prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD, | ||
520 | OMAP3430_PM_IVAGRPSEL1); | ||
521 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD, | ||
522 | OMAP3430ES2_PM_MPUGRPSEL3); | ||
523 | prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD, | ||
524 | OMAP3430ES2_PM_IVAGRPSEL3); | ||
525 | prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD, | ||
526 | OMAP3430_PM_MPUGRPSEL); | ||
527 | prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD, | ||
528 | OMAP3430_PM_IVAGRPSEL); | ||
529 | prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD, | ||
530 | OMAP3430_PM_MPUGRPSEL); | ||
531 | prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD, | ||
532 | OMAP3430_PM_IVAGRPSEL); | ||
533 | prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN); | ||
534 | return; | ||
535 | } | ||
536 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 064b52a3e202..3e1d36c83fc4 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c | |||
@@ -154,4 +154,3 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) | |||
154 | 154 | ||
155 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | 155 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; |
156 | } | 156 | } |
157 | |||
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 3769fc6eca29..d059a05bc457 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h | |||
@@ -31,9 +31,6 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, | |||
31 | #define START_PADCONF_SAVE 0x2 | 31 | #define START_PADCONF_SAVE 0x2 |
32 | #define PADCONF_SAVE_DONE 0x1 | 32 | #define PADCONF_SAVE_DONE 0x1 |
33 | 33 | ||
34 | void omap3_prcm_save_context(void); | ||
35 | void omap3_prcm_restore_context(void); | ||
36 | |||
37 | u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); | 34 | u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); |
38 | u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); | 35 | u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); |
39 | 36 | ||