diff options
author | Vineet Gupta <vgupta@synopsys.com> | 2014-03-07 07:38:11 -0500 |
---|---|---|
committer | Vineet Gupta <vgupta@synopsys.com> | 2014-06-03 05:44:48 -0400 |
commit | ef680cdc24376f394841a3f19b3a7ef6d57a009d (patch) | |
tree | d70faaeb25f0109b051d675e3ca02641785cbe34 | |
parent | e87a850b9c92be6a8cf5735c516ec864d65f24dd (diff) |
ARC: Disable caches in early boot if so configured
Requested-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r-- | arch/arc/include/asm/cache.h | 27 | ||||
-rw-r--r-- | arch/arc/kernel/head.S | 38 | ||||
-rw-r--r-- | arch/arc/mm/cache_arc700.c | 106 |
3 files changed, 87 insertions, 84 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 2fd3162ec4df..c1d3d2da1191 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h | |||
@@ -55,4 +55,31 @@ extern void read_decode_cache_bcr(void); | |||
55 | 55 | ||
56 | #endif /* !__ASSEMBLY__ */ | 56 | #endif /* !__ASSEMBLY__ */ |
57 | 57 | ||
58 | /* Instruction cache related Auxiliary registers */ | ||
59 | #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ | ||
60 | #define ARC_REG_IC_IVIC 0x10 | ||
61 | #define ARC_REG_IC_CTRL 0x11 | ||
62 | #define ARC_REG_IC_IVIL 0x19 | ||
63 | #if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4) | ||
64 | #define ARC_REG_IC_PTAG 0x1E | ||
65 | #endif | ||
66 | |||
67 | /* Bit val in IC_CTRL */ | ||
68 | #define IC_CTRL_CACHE_DISABLE 0x1 | ||
69 | |||
70 | /* Data cache related Auxiliary registers */ | ||
71 | #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ | ||
72 | #define ARC_REG_DC_IVDC 0x47 | ||
73 | #define ARC_REG_DC_CTRL 0x48 | ||
74 | #define ARC_REG_DC_IVDL 0x4A | ||
75 | #define ARC_REG_DC_FLSH 0x4B | ||
76 | #define ARC_REG_DC_FLDL 0x4C | ||
77 | #if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4) | ||
78 | #define ARC_REG_DC_PTAG 0x5C | ||
79 | #endif | ||
80 | |||
81 | /* Bit val in DC_CTRL */ | ||
82 | #define DC_CTRL_INV_MODE_FLUSH 0x40 | ||
83 | #define DC_CTRL_FLUSH_STATUS 0x100 | ||
84 | |||
58 | #endif /* _ASM_CACHE_H */ | 85 | #endif /* _ASM_CACHE_H */ |
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S index 4ad04915dc6b..07a58f2d3077 100644 --- a/arch/arc/kernel/head.S +++ b/arch/arc/kernel/head.S | |||
@@ -12,10 +12,42 @@ | |||
12 | * to skip certain things during boot on simulator | 12 | * to skip certain things during boot on simulator |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/linkage.h> | ||
15 | #include <asm/asm-offsets.h> | 16 | #include <asm/asm-offsets.h> |
16 | #include <asm/entry.h> | 17 | #include <asm/entry.h> |
17 | #include <linux/linkage.h> | ||
18 | #include <asm/arcregs.h> | 18 | #include <asm/arcregs.h> |
19 | #include <asm/cache.h> | ||
20 | |||
21 | .macro CPU_EARLY_SETUP | ||
22 | |||
23 | ; Setting up Vectror Table (in case exception happens in early boot | ||
24 | sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] | ||
25 | |||
26 | ; Disable I-cache/D-cache if kernel so configured | ||
27 | lr r5, [ARC_REG_IC_BCR] | ||
28 | breq r5, 0, 1f ; I$ doesn't exist | ||
29 | lr r5, [ARC_REG_IC_CTRL] | ||
30 | #ifdef CONFIG_ARC_HAS_ICACHE | ||
31 | bclr r5, r5, 0 ; 0 - Enable, 1 is Disable | ||
32 | #else | ||
33 | bset r5, r5, 0 ; I$ exists, but is not used | ||
34 | #endif | ||
35 | sr r5, [ARC_REG_IC_CTRL] | ||
36 | |||
37 | 1: | ||
38 | lr r5, [ARC_REG_DC_BCR] | ||
39 | breq r5, 0, 1f ; D$ doesn't exist | ||
40 | lr r5, [ARC_REG_DC_CTRL] | ||
41 | bclr r5, r5, 6 ; Invalidate (discard w/o wback) | ||
42 | #ifdef CONFIG_ARC_HAS_DCACHE | ||
43 | bclr r5, r5, 0 ; Enable (+Inv) | ||
44 | #else | ||
45 | bset r5, r5, 0 ; Disable (+Inv) | ||
46 | #endif | ||
47 | sr r5, [ARC_REG_DC_CTRL] | ||
48 | |||
49 | 1: | ||
50 | .endm | ||
19 | 51 | ||
20 | .cpu A7 | 52 | .cpu A7 |
21 | 53 | ||
@@ -27,7 +59,7 @@ stext: | |||
27 | ; Don't clobber r0-r2 yet. It might have bootloader provided info | 59 | ; Don't clobber r0-r2 yet. It might have bootloader provided info |
28 | ;------------------------------------------------------------------- | 60 | ;------------------------------------------------------------------- |
29 | 61 | ||
30 | sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] | 62 | CPU_EARLY_SETUP |
31 | 63 | ||
32 | #ifdef CONFIG_SMP | 64 | #ifdef CONFIG_SMP |
33 | ; Ensure Boot (Master) proceeds. Others wait in platform dependent way | 65 | ; Ensure Boot (Master) proceeds. Others wait in platform dependent way |
@@ -90,7 +122,7 @@ stext: | |||
90 | 122 | ||
91 | first_lines_of_secondary: | 123 | first_lines_of_secondary: |
92 | 124 | ||
93 | sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] | 125 | CPU_EARLY_SETUP |
94 | 126 | ||
95 | ; setup per-cpu idle task as "current" on this CPU | 127 | ; setup per-cpu idle task as "current" on this CPU |
96 | ld r0, [@secondary_idle_tsk] | 128 | ld r0, [@secondary_idle_tsk] |
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c index 23c3832e6d9f..1f676c4794e0 100644 --- a/arch/arc/mm/cache_arc700.c +++ b/arch/arc/mm/cache_arc700.c | |||
@@ -73,33 +73,6 @@ | |||
73 | #include <asm/cachectl.h> | 73 | #include <asm/cachectl.h> |
74 | #include <asm/setup.h> | 74 | #include <asm/setup.h> |
75 | 75 | ||
76 | /* Instruction cache related Auxiliary registers */ | ||
77 | #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ | ||
78 | #define ARC_REG_IC_IVIC 0x10 | ||
79 | #define ARC_REG_IC_CTRL 0x11 | ||
80 | #define ARC_REG_IC_IVIL 0x19 | ||
81 | #if (CONFIG_ARC_MMU_VER > 2) | ||
82 | #define ARC_REG_IC_PTAG 0x1E | ||
83 | #endif | ||
84 | |||
85 | /* Bit val in IC_CTRL */ | ||
86 | #define IC_CTRL_CACHE_DISABLE 0x1 | ||
87 | |||
88 | /* Data cache related Auxiliary registers */ | ||
89 | #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ | ||
90 | #define ARC_REG_DC_IVDC 0x47 | ||
91 | #define ARC_REG_DC_CTRL 0x48 | ||
92 | #define ARC_REG_DC_IVDL 0x4A | ||
93 | #define ARC_REG_DC_FLSH 0x4B | ||
94 | #define ARC_REG_DC_FLDL 0x4C | ||
95 | #if (CONFIG_ARC_MMU_VER > 2) | ||
96 | #define ARC_REG_DC_PTAG 0x5C | ||
97 | #endif | ||
98 | |||
99 | /* Bit val in DC_CTRL */ | ||
100 | #define DC_CTRL_INV_MODE_FLUSH 0x40 | ||
101 | #define DC_CTRL_FLUSH_STATUS 0x100 | ||
102 | |||
103 | char *arc_cache_mumbojumbo(int c, char *buf, int len) | 76 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
104 | { | 77 | { |
105 | int n = 0; | 78 | int n = 0; |
@@ -168,72 +141,43 @@ void read_decode_cache_bcr(void) | |||
168 | */ | 141 | */ |
169 | void arc_cache_init(void) | 142 | void arc_cache_init(void) |
170 | { | 143 | { |
171 | unsigned int cpu = smp_processor_id(); | 144 | unsigned int __maybe_unused cpu = smp_processor_id(); |
172 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | 145 | struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc; |
173 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | ||
174 | unsigned int dcache_does_alias, temp; | ||
175 | char str[256]; | 146 | char str[256]; |
176 | 147 | ||
177 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | 148 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); |
178 | 149 | ||
179 | if (!ic->ver) | ||
180 | goto chk_dc; | ||
181 | |||
182 | #ifdef CONFIG_ARC_HAS_ICACHE | 150 | #ifdef CONFIG_ARC_HAS_ICACHE |
183 | /* 1. Confirm some of I-cache params which Linux assumes */ | 151 | ic = &cpuinfo_arc700[cpu].icache; |
184 | if (ic->line_len != L1_CACHE_BYTES) | 152 | if (ic->ver) { |
185 | panic("Cache H/W doesn't match kernel Config"); | 153 | if (ic->line_len != L1_CACHE_BYTES) |
186 | 154 | panic("ICache line [%d] != kernel Config [%d]", | |
187 | if (ic->ver != CONFIG_ARC_MMU_VER) | 155 | ic->line_len, L1_CACHE_BYTES); |
188 | panic("Cache ver doesn't match MMU ver\n"); | 156 | |
189 | #endif | 157 | if (ic->ver != CONFIG_ARC_MMU_VER) |
190 | 158 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", | |
191 | /* Enable/disable I-Cache */ | 159 | ic->ver, CONFIG_ARC_MMU_VER); |
192 | temp = read_aux_reg(ARC_REG_IC_CTRL); | 160 | } |
193 | |||
194 | #ifdef CONFIG_ARC_HAS_ICACHE | ||
195 | temp &= ~IC_CTRL_CACHE_DISABLE; | ||
196 | #else | ||
197 | temp |= IC_CTRL_CACHE_DISABLE; | ||
198 | #endif | 161 | #endif |
199 | 162 | ||
200 | write_aux_reg(ARC_REG_IC_CTRL, temp); | ||
201 | |||
202 | chk_dc: | ||
203 | if (!dc->ver) | ||
204 | return; | ||
205 | |||
206 | #ifdef CONFIG_ARC_HAS_DCACHE | 163 | #ifdef CONFIG_ARC_HAS_DCACHE |
207 | if (dc->line_len != L1_CACHE_BYTES) | 164 | dc = &cpuinfo_arc700[cpu].dcache; |
208 | panic("Cache H/W doesn't match kernel Config"); | 165 | if (dc->ver) { |
166 | unsigned int dcache_does_alias; | ||
209 | 167 | ||
210 | /* check for D-Cache aliasing */ | 168 | if (dc->line_len != L1_CACHE_BYTES) |
211 | dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; | 169 | panic("DCache line [%d] != kernel Config [%d]", |
170 | dc->line_len, L1_CACHE_BYTES); | ||
212 | 171 | ||
213 | if (dcache_does_alias && !cache_is_vipt_aliasing()) | 172 | /* check for D-Cache aliasing */ |
214 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | 173 | dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; |
215 | else if (!dcache_does_alias && cache_is_vipt_aliasing()) | ||
216 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | ||
217 | #endif | ||
218 | 174 | ||
219 | /* Set the default Invalidate Mode to "simpy discard dirty lines" | 175 | if (dcache_does_alias && !cache_is_vipt_aliasing()) |
220 | * as this is more frequent then flush before invalidate | 176 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
221 | * Ofcourse we toggle this default behviour when desired | 177 | else if (!dcache_does_alias && cache_is_vipt_aliasing()) |
222 | */ | 178 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
223 | temp = read_aux_reg(ARC_REG_DC_CTRL); | 179 | } |
224 | temp &= ~DC_CTRL_INV_MODE_FLUSH; | ||
225 | |||
226 | #ifdef CONFIG_ARC_HAS_DCACHE | ||
227 | /* Enable D-Cache: Clear Bit 0 */ | ||
228 | write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); | ||
229 | #else | ||
230 | /* Flush D cache */ | ||
231 | write_aux_reg(ARC_REG_DC_FLSH, 0x1); | ||
232 | /* Disable D cache */ | ||
233 | write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); | ||
234 | #endif | 180 | #endif |
235 | |||
236 | return; | ||
237 | } | 181 | } |
238 | 182 | ||
239 | #define OP_INV 0x1 | 183 | #define OP_INV 0x1 |