clk: st: STiH407: Support for clockgenA0

The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index cdf23dbd4ad4..d4ef4f479776 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -180,6 +180,18 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
         .ops            = &st_pll1200c32_ops,
 };
 
+static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
+        /* 407 A0 */
+        .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
+        .locked_status  = CLKGEN_FIELD(0x2a0,   0x1,                    24),
+        .ndiv           = CLKGEN_FIELD(0x2a4,   C32_NDIV_MASK,          16),
+        .idf            = CLKGEN_FIELD(0x2a4,   C32_IDF_MASK,           0x0),
+        .num_odfs = 1,
+        .odf            = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,           0) },
+        .odf_gate       = { CLKGEN_FIELD(0x2b4, 0x1,                    6) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
 /**
  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  *
@@ -570,6 +582,10 @@ static struct of_device_id c32_pll_of_match[] = {
                 .compatible = "st,stih416-plls-c32-ddr",
                 .data = &st_pll3200c32_ddr_416,
         },
+        {
+                .compatible = "st,stih407-plls-c32-a0",
+                .data = &st_pll3200c32_407_a0,
+        },
         {}
 };