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authorArnd Bergmann <arnd@arndb.de>2012-05-14 15:14:43 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 15:14:43 -0400
commiteedd52e3c462d5434412fd0b7bc183ed76d3a4a8 (patch)
tree60d239a229673658b38dcb949286ad45a4a89167
parent030caf3f22395d564ee8a4f056a9cb7190a7eed4 (diff)
parentbca10b906f8d2e4f177bff047b9d623941e454f7 (diff)
Merge branch 'exynos/sysmmu' into next/cleanup2
Required as a depdency for the next/cleanup-plat-s3c24xx-s5p branch Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/mach-exynos/Kconfig10
-rw-r--r--arch/arm/mach-exynos/Makefile2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c79
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c11
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c28
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c90
-rw-r--r--arch/arm/mach-exynos/dev-sysmmu.c457
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h25
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h38
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-sysmmu.h28
-rw-r--r--arch/arm/mach-exynos/include/mach/sysmmu.h88
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c1
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c1
-rw-r--r--arch/arm/plat-s5p/Kconfig8
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/sysmmu.c313
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/sysmmu.h95
20 files changed, 529 insertions, 754 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e81c35f936b5..2c35fd404cae 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -85,10 +85,10 @@ config EXYNOS4_SETUP_FIMD0
85 help 85 help
86 Common setup code for FIMD0. 86 Common setup code for FIMD0.
87 87
88config EXYNOS4_DEV_SYSMMU 88config EXYNOS_DEV_SYSMMU
89 bool 89 bool
90 help 90 help
91 Common setup code for SYSTEM MMU in EXYNOS4 91 Common setup code for SYSTEM MMU in EXYNOS platforms
92 92
93config EXYNOS4_DEV_DWMCI 93config EXYNOS4_DEV_DWMCI
94 bool 94 bool
@@ -200,12 +200,12 @@ config MACH_SMDKV310
200 select S3C_DEV_HSMMC2 200 select S3C_DEV_HSMMC2
201 select S3C_DEV_HSMMC3 201 select S3C_DEV_HSMMC3
202 select SAMSUNG_DEV_BACKLIGHT 202 select SAMSUNG_DEV_BACKLIGHT
203 select EXYNOS_DEV_SYSMMU
203 select EXYNOS4_DEV_AHCI 204 select EXYNOS4_DEV_AHCI
204 select SAMSUNG_DEV_KEYPAD 205 select SAMSUNG_DEV_KEYPAD
205 select EXYNOS4_DEV_DMA 206 select EXYNOS4_DEV_DMA
206 select SAMSUNG_DEV_PWM 207 select SAMSUNG_DEV_PWM
207 select EXYNOS4_DEV_USB_OHCI 208 select EXYNOS4_DEV_USB_OHCI
208 select EXYNOS4_DEV_SYSMMU
209 select EXYNOS4_SETUP_FIMD0 209 select EXYNOS4_SETUP_FIMD0
210 select EXYNOS4_SETUP_I2C1 210 select EXYNOS4_SETUP_I2C1
211 select EXYNOS4_SETUP_KEYPAD 211 select EXYNOS4_SETUP_KEYPAD
@@ -224,7 +224,6 @@ config MACH_ARMLEX4210
224 select S3C_DEV_HSMMC3 224 select S3C_DEV_HSMMC3
225 select EXYNOS4_DEV_AHCI 225 select EXYNOS4_DEV_AHCI
226 select EXYNOS4_DEV_DMA 226 select EXYNOS4_DEV_DMA
227 select EXYNOS4_DEV_SYSMMU
228 select EXYNOS4_SETUP_SDHCI 227 select EXYNOS4_SETUP_SDHCI
229 help 228 help
230 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 229 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -251,6 +250,7 @@ config MACH_UNIVERSAL_C210
251 select S5P_DEV_MFC 250 select S5P_DEV_MFC
252 select S5P_DEV_ONENAND 251 select S5P_DEV_ONENAND
253 select S5P_DEV_TV 252 select S5P_DEV_TV
253 select EXYNOS_DEV_SYSMMU
254 select EXYNOS4_DEV_DMA 254 select EXYNOS4_DEV_DMA
255 select EXYNOS4_SETUP_FIMD0 255 select EXYNOS4_SETUP_FIMD0
256 select EXYNOS4_SETUP_I2C1 256 select EXYNOS4_SETUP_I2C1
@@ -322,6 +322,7 @@ config MACH_ORIGEN
322 select S5P_DEV_USB_EHCI 322 select S5P_DEV_USB_EHCI
323 select SAMSUNG_DEV_BACKLIGHT 323 select SAMSUNG_DEV_BACKLIGHT
324 select SAMSUNG_DEV_PWM 324 select SAMSUNG_DEV_PWM
325 select EXYNOS_DEV_SYSMMU
325 select EXYNOS4_DEV_DMA 326 select EXYNOS4_DEV_DMA
326 select EXYNOS4_DEV_USB_OHCI 327 select EXYNOS4_DEV_USB_OHCI
327 select EXYNOS4_SETUP_FIMD0 328 select EXYNOS4_SETUP_FIMD0
@@ -345,6 +346,7 @@ config MACH_SMDK4212
345 select SAMSUNG_DEV_BACKLIGHT 346 select SAMSUNG_DEV_BACKLIGHT
346 select SAMSUNG_DEV_KEYPAD 347 select SAMSUNG_DEV_KEYPAD
347 select SAMSUNG_DEV_PWM 348 select SAMSUNG_DEV_PWM
349 select EXYNOS_DEV_SYSMMU
348 select EXYNOS4_DEV_DMA 350 select EXYNOS4_DEV_DMA
349 select EXYNOS4_SETUP_I2C1 351 select EXYNOS4_SETUP_I2C1
350 select EXYNOS4_SETUP_I2C3 352 select EXYNOS4_SETUP_I2C3
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8631840d1b5e..272625231c73 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,7 +50,7 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
50obj-y += dev-uart.o 50obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 53obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 6efd1e5919fd..bcb7db453145 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -168,7 +168,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); 168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169} 169}
170 170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) 171int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{ 172{
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); 173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174} 174}
@@ -198,6 +198,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); 198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199} 199}
200 200
201int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202{
203 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
204}
205
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 206static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202{ 207{
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 208 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@@ -678,61 +683,55 @@ static struct clk exynos4_init_clocks_off[] = {
678 .enable = exynos4_clk_ip_peril_ctrl, 683 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 14), 684 .ctrlbit = (1 << 14),
680 }, { 685 }, {
681 .name = "SYSMMU_MDMA", 686 .name = SYSMMU_CLOCK_NAME,
687 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
688 .enable = exynos4_clk_ip_mfc_ctrl,
689 .ctrlbit = (1 << 1),
690 }, {
691 .name = SYSMMU_CLOCK_NAME,
692 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
693 .enable = exynos4_clk_ip_mfc_ctrl,
694 .ctrlbit = (1 << 2),
695 }, {
696 .name = SYSMMU_CLOCK_NAME,
697 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
698 .enable = exynos4_clk_ip_tv_ctrl,
699 .ctrlbit = (1 << 4),
700 }, {
701 .name = SYSMMU_CLOCK_NAME,
702 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
703 .enable = exynos4_clk_ip_cam_ctrl,
704 .ctrlbit = (1 << 11),
705 }, {
706 .name = SYSMMU_CLOCK_NAME,
707 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
682 .enable = exynos4_clk_ip_image_ctrl, 708 .enable = exynos4_clk_ip_image_ctrl,
683 .ctrlbit = (1 << 5), 709 .ctrlbit = (1 << 4),
684 }, { 710 }, {
685 .name = "SYSMMU_FIMC0", 711 .name = SYSMMU_CLOCK_NAME,
712 .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
686 .enable = exynos4_clk_ip_cam_ctrl,