diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-03-03 01:18:55 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-03-26 00:08:06 -0400 |
commit | eeb0558e074215656ae11a170059a5f2ce29963f (patch) | |
tree | efdf357c69546c3697226dbf4b76965253d71a12 | |
parent | 6acc09b99d5d8f276a4f9bffc32f0bb0f939c7ca (diff) |
drm/gf104/gr: rename gf104 (nvc4), it came before gf106 (nvc3)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c (renamed from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c) | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c (renamed from drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c) | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/engine/graph.h | 2 |
7 files changed, 23 insertions, 23 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index a4a3dffce105..4c5a61e4277f 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -249,7 +249,7 @@ nouveau-y += core/engine/graph/ctxnv40.o | |||
249 | nouveau-y += core/engine/graph/ctxnv50.o | 249 | nouveau-y += core/engine/graph/ctxnv50.o |
250 | nouveau-y += core/engine/graph/ctxnvc0.o | 250 | nouveau-y += core/engine/graph/ctxnvc0.o |
251 | nouveau-y += core/engine/graph/ctxnvc1.o | 251 | nouveau-y += core/engine/graph/ctxnvc1.o |
252 | nouveau-y += core/engine/graph/ctxnvc3.o | 252 | nouveau-y += core/engine/graph/ctxnvc4.o |
253 | nouveau-y += core/engine/graph/ctxnvc8.o | 253 | nouveau-y += core/engine/graph/ctxnvc8.o |
254 | nouveau-y += core/engine/graph/ctxnvd7.o | 254 | nouveau-y += core/engine/graph/ctxnvd7.o |
255 | nouveau-y += core/engine/graph/ctxnvd9.o | 255 | nouveau-y += core/engine/graph/ctxnvd9.o |
@@ -268,7 +268,7 @@ nouveau-y += core/engine/graph/nv40.o | |||
268 | nouveau-y += core/engine/graph/nv50.o | 268 | nouveau-y += core/engine/graph/nv50.o |
269 | nouveau-y += core/engine/graph/nvc0.o | 269 | nouveau-y += core/engine/graph/nvc0.o |
270 | nouveau-y += core/engine/graph/nvc1.o | 270 | nouveau-y += core/engine/graph/nvc1.o |
271 | nouveau-y += core/engine/graph/nvc3.o | 271 | nouveau-y += core/engine/graph/nvc4.o |
272 | nouveau-y += core/engine/graph/nvc8.o | 272 | nouveau-y += core/engine/graph/nvc8.o |
273 | nouveau-y += core/engine/graph/nvd7.o | 273 | nouveau-y += core/engine/graph/nvd7.o |
274 | nouveau-y += core/engine/graph/nvd9.o | 274 | nouveau-y += core/engine/graph/nvd9.o |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c index 78f4bfd6686f..2075b3027052 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | |||
@@ -112,7 +112,7 @@ nvc0_identify(struct nouveau_device *device) | |||
112 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; | 112 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
113 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; | 113 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
114 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; | 114 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
115 | device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; | 115 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
116 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; | 116 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
117 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; | 117 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
118 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | 118 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
@@ -144,7 +144,7 @@ nvc0_identify(struct nouveau_device *device) | |||
144 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; | 144 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
145 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; | 145 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
146 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; | 146 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
147 | device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; | 147 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
148 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; | 148 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
149 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; | 149 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
150 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | 150 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
@@ -175,7 +175,7 @@ nvc0_identify(struct nouveau_device *device) | |||
175 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; | 175 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
176 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; | 176 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
177 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; | 177 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
178 | device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; | 178 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
179 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; | 179 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
180 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; | 180 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
181 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | 181 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device) | |||
207 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; | 207 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
208 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; | 208 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
209 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; | 209 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
210 | device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; | 210 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
211 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; | 211 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
212 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; | 212 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
213 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | 213 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c index 8f237b3bd8c6..d2734163cae9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "nvc0.h" | 25 | #include "nvc0.h" |
26 | 26 | ||
27 | static struct nvc0_graph_init | 27 | static struct nvc0_graph_init |
28 | nvc3_grctx_init_tpc[] = { | 28 | nvc4_grctx_init_tpc[] = { |
29 | { 0x419818, 1, 0x04, 0x00000000 }, | 29 | { 0x419818, 1, 0x04, 0x00000000 }, |
30 | { 0x41983c, 1, 0x04, 0x00038bc7 }, | 30 | { 0x41983c, 1, 0x04, 0x00038bc7 }, |
31 | { 0x419848, 1, 0x04, 0x00000000 }, | 31 | { 0x419848, 1, 0x04, 0x00000000 }, |
@@ -71,15 +71,15 @@ nvc3_grctx_init_tpc[] = { | |||
71 | }; | 71 | }; |
72 | 72 | ||
73 | struct nvc0_graph_init * | 73 | struct nvc0_graph_init * |
74 | nvc3_grctx_init_gpc[] = { | 74 | nvc4_grctx_init_gpc[] = { |
75 | nvc0_grctx_init_gpc_0, | 75 | nvc0_grctx_init_gpc_0, |
76 | nvc0_grctx_init_gpc_1, | 76 | nvc0_grctx_init_gpc_1, |
77 | nvc3_grctx_init_tpc, | 77 | nvc4_grctx_init_tpc, |
78 | NULL | 78 | NULL |
79 | }; | 79 | }; |
80 | 80 | ||
81 | struct nouveau_oclass * | 81 | struct nouveau_oclass * |
82 | nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { | 82 | nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { |
83 | .base.handle = NV_ENGCTX(GR, 0xc3), | 83 | .base.handle = NV_ENGCTX(GR, 0xc3), |
84 | .base.ofuncs = &(struct nouveau_ofuncs) { | 84 | .base.ofuncs = &(struct nouveau_ofuncs) { |
85 | .ctor = nvc0_graph_context_ctor, | 85 | .ctor = nvc0_graph_context_ctor, |
@@ -93,7 +93,7 @@ nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { | |||
93 | .mods = nvc0_grctx_generate_mods, | 93 | .mods = nvc0_grctx_generate_mods, |
94 | .unkn = nvc0_grctx_generate_unkn, | 94 | .unkn = nvc0_grctx_generate_unkn, |
95 | .hub = nvc0_grctx_init_hub, | 95 | .hub = nvc0_grctx_init_hub, |
96 | .gpc = nvc3_grctx_init_gpc, | 96 | .gpc = nvc4_grctx_init_gpc, |
97 | .icmd = nvc0_grctx_init_icmd, | 97 | .icmd = nvc0_grctx_init_icmd, |
98 | .mthd = nvc0_grctx_init_mthd, | 98 | .mthd = nvc0_grctx_init_mthd, |
99 | }.base; | 99 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h index b0ab6de270b2..1335967fbe74 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | |||
@@ -196,7 +196,7 @@ extern struct nvc0_graph_init nvc0_graph_init_gpc[]; | |||
196 | extern struct nvc0_graph_init nvc0_graph_init_unk88xx[]; | 196 | extern struct nvc0_graph_init nvc0_graph_init_unk88xx[]; |
197 | extern struct nvc0_graph_init nvc0_graph_tpc_0[]; | 197 | extern struct nvc0_graph_init nvc0_graph_tpc_0[]; |
198 | 198 | ||
199 | extern struct nvc0_graph_init nvc3_graph_init_unk58xx[]; | 199 | extern struct nvc0_graph_init nvc4_graph_init_unk58xx[]; |
200 | 200 | ||
201 | extern struct nvc0_graph_init nvd9_graph_init_unk58xx[]; | 201 | extern struct nvc0_graph_init nvd9_graph_init_unk58xx[]; |
202 | extern struct nvc0_graph_init nvd9_graph_init_unk64xx[]; | 202 | extern struct nvc0_graph_init nvd9_graph_init_unk64xx[]; |
@@ -249,7 +249,7 @@ void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); | |||
249 | extern struct nouveau_oclass *nvc1_grctx_oclass; | 249 | extern struct nouveau_oclass *nvc1_grctx_oclass; |
250 | extern struct nvc0_graph_init nvc1_grctx_init_9097[]; | 250 | extern struct nvc0_graph_init nvc1_grctx_init_9097[]; |
251 | 251 | ||
252 | extern struct nouveau_oclass *nvc3_grctx_oclass; | 252 | extern struct nouveau_oclass *nvc4_grctx_oclass; |
253 | 253 | ||
254 | extern struct nouveau_oclass *nvc8_grctx_oclass; | 254 | extern struct nouveau_oclass *nvc8_grctx_oclass; |
255 | extern struct nvc0_graph_init nvc8_grctx_init_9197[]; | 255 | extern struct nvc0_graph_init nvc8_grctx_init_9197[]; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c index bc4a469b86cb..26decd028f75 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c | |||
@@ -118,7 +118,7 @@ nvc1_graph_init_mmio[] = { | |||
118 | nvc0_graph_init_unk44xx, | 118 | nvc0_graph_init_unk44xx, |
119 | nvc0_graph_init_unk78xx, | 119 | nvc0_graph_init_unk78xx, |
120 | nvc0_graph_init_unk60xx, | 120 | nvc0_graph_init_unk60xx, |
121 | nvc3_graph_init_unk58xx, | 121 | nvc4_graph_init_unk58xx, |
122 | nvc0_graph_init_unk80xx, | 122 | nvc0_graph_init_unk80xx, |
123 | nvc1_graph_init_gpc, | 123 | nvc1_graph_init_gpc, |
124 | nvc1_graph_init_tpc, | 124 | nvc1_graph_init_tpc, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c index d44b3b3ee800..1c74d8e5d7ee 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c | |||
@@ -29,7 +29,7 @@ | |||
29 | ******************************************************************************/ | 29 | ******************************************************************************/ |
30 | 30 | ||
31 | struct nvc0_graph_init | 31 | struct nvc0_graph_init |
32 | nvc3_graph_init_unk58xx[] = { | 32 | nvc4_graph_init_unk58xx[] = { |
33 | { 0x405844, 1, 0x04, 0x00ffffff }, | 33 | { 0x405844, 1, 0x04, 0x00ffffff }, |
34 | { 0x405850, 1, 0x04, 0x00000000 }, | 34 | { 0x405850, 1, 0x04, 0x00000000 }, |
35 | { 0x405900, 1, 0x04, 0x00002834 }, | 35 | { 0x405900, 1, 0x04, 0x00002834 }, |
@@ -38,7 +38,7 @@ nvc3_graph_init_unk58xx[] = { | |||
38 | }; | 38 | }; |
39 | 39 | ||
40 | static struct nvc0_graph_init | 40 | static struct nvc0_graph_init |
41 | nvc3_graph_init_tpc[] = { | 41 | nvc4_graph_init_tpc[] = { |
42 | { 0x419d08, 2, 0x04, 0x00000000 }, | 42 | { 0x419d08, 2, 0x04, 0x00000000 }, |
43 | { 0x419d10, 1, 0x04, 0x00000014 }, | 43 | { 0x419d10, 1, 0x04, 0x00000014 }, |
44 | { 0x419ab0, 1, 0x04, 0x00000000 }, | 44 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
@@ -78,23 +78,23 @@ nvc3_graph_init_tpc[] = { | |||
78 | }; | 78 | }; |
79 | 79 | ||
80 | static struct nvc0_graph_init * | 80 | static struct nvc0_graph_init * |
81 | nvc3_graph_init_mmio[] = { | 81 | nvc4_graph_init_mmio[] = { |
82 | nvc0_graph_init_regs, | 82 | nvc0_graph_init_regs, |
83 | nvc0_graph_init_unk40xx, | 83 | nvc0_graph_init_unk40xx, |
84 | nvc0_graph_init_unk44xx, | 84 | nvc0_graph_init_unk44xx, |
85 | nvc0_graph_init_unk78xx, | 85 | nvc0_graph_init_unk78xx, |
86 | nvc0_graph_init_unk60xx, | 86 | nvc0_graph_init_unk60xx, |
87 | nvc3_graph_init_unk58xx, | 87 | nvc4_graph_init_unk58xx, |
88 | nvc0_graph_init_unk80xx, | 88 | nvc0_graph_init_unk80xx, |
89 | nvc0_graph_init_gpc, | 89 | nvc0_graph_init_gpc, |
90 | nvc3_graph_init_tpc, | 90 | nvc4_graph_init_tpc, |
91 | nvc0_graph_init_unk88xx, | 91 | nvc0_graph_init_unk88xx, |
92 | nvc0_graph_tpc_0, | 92 | nvc0_graph_tpc_0, |
93 | NULL | 93 | NULL |
94 | }; | 94 | }; |
95 | 95 | ||
96 | struct nouveau_oclass * | 96 | struct nouveau_oclass * |
97 | nvc3_graph_oclass = &(struct nvc0_graph_oclass) { | 97 | nvc4_graph_oclass = &(struct nvc0_graph_oclass) { |
98 | .base.handle = NV_ENGINE(GR, 0xc3), | 98 | .base.handle = NV_ENGINE(GR, 0xc3), |
99 | .base.ofuncs = &(struct nouveau_ofuncs) { | 99 | .base.ofuncs = &(struct nouveau_ofuncs) { |
100 | .ctor = nvc0_graph_ctor, | 100 | .ctor = nvc0_graph_ctor, |
@@ -102,9 +102,9 @@ nvc3_graph_oclass = &(struct nvc0_graph_oclass) { | |||
102 | .init = nvc0_graph_init, | 102 | .init = nvc0_graph_init, |
103 | .fini = _nouveau_graph_fini, | 103 | .fini = _nouveau_graph_fini, |
104 | }, | 104 | }, |
105 | .cclass = &nvc3_grctx_oclass, | 105 | .cclass = &nvc4_grctx_oclass, |
106 | .sclass = nvc0_graph_sclass, | 106 | .sclass = nvc0_graph_sclass, |
107 | .mmio = nvc3_graph_init_mmio, | 107 | .mmio = nvc4_graph_init_mmio, |
108 | .fecs.ucode = &nvc0_graph_fecs_ucode, | 108 | .fecs.ucode = &nvc0_graph_fecs_ucode, |
109 | .gpccs.ucode = &nvc0_graph_gpccs_ucode, | 109 | .gpccs.ucode = &nvc0_graph_gpccs_ucode, |
110 | }.base; | 110 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h index 97705618de97..05e34840e6e3 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h | |||
@@ -63,7 +63,7 @@ extern struct nouveau_oclass nv40_graph_oclass; | |||
63 | extern struct nouveau_oclass nv50_graph_oclass; | 63 | extern struct nouveau_oclass nv50_graph_oclass; |
64 | extern struct nouveau_oclass *nvc0_graph_oclass; | 64 | extern struct nouveau_oclass *nvc0_graph_oclass; |
65 | extern struct nouveau_oclass *nvc1_graph_oclass; | 65 | extern struct nouveau_oclass *nvc1_graph_oclass; |
66 | extern struct nouveau_oclass *nvc3_graph_oclass; | 66 | extern struct nouveau_oclass *nvc4_graph_oclass; |
67 | extern struct nouveau_oclass *nvc8_graph_oclass; | 67 | extern struct nouveau_oclass *nvc8_graph_oclass; |
68 | extern struct nouveau_oclass *nvd7_graph_oclass; | 68 | extern struct nouveau_oclass *nvd7_graph_oclass; |
69 | extern struct nouveau_oclass *nvd9_graph_oclass; | 69 | extern struct nouveau_oclass *nvd9_graph_oclass; |