diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2014-06-12 00:44:16 -0400 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2014-06-17 06:58:27 -0400 |
commit | ee9141522dcf13f861ed3cef6490c6cbfaafefb9 (patch) | |
tree | e34f6d54141b85c093d8149f86de8a59dba7ffc8 | |
parent | 0d3dbde84a45977cdd7d85115cd5ea1b4ede312e (diff) |
ARM: shmobile: r8a7791: add MSTP10 support on DTSI
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 33 | ||||
-rw-r--r-- | include/dt-bindings/clock/r8a7791-clock.h | 26 |
2 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f3b6219cc09e..380d058e4210 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
@@ -865,6 +865,39 @@ | |||
865 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | 865 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", |
866 | "i2c1", "i2c0"; | 866 | "i2c1", "i2c0"; |
867 | }; | 867 | }; |
868 | mstp10_clks: mstp10_clks@e6150998 { | ||
869 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
870 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | ||
871 | clocks = <&p_clk>, | ||
872 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | ||
873 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | ||
874 | <&p_clk>, | ||
875 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | ||
876 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | ||
877 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | ||
878 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | ||
879 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | ||
880 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; | ||
881 | |||
882 | #clock-cells = <1>; | ||
883 | clock-indices = < | ||
884 | R8A7791_CLK_SSI_ALL | ||
885 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | ||
886 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | ||
887 | R8A7791_CLK_SCU_ALL | ||
888 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | ||
889 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 | ||
890 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | ||
891 | >; | ||
892 | clock-output-names = | ||
893 | "ssi-all", | ||
894 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | ||
895 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | ||
896 | "scu-all", | ||
897 | "scu-dvc1", "scu-dvc0", | ||
898 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | ||
899 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | ||
900 | }; | ||
868 | mstp11_clks: mstp11_clks@e615099c { | 901 | mstp11_clks: mstp11_clks@e615099c { |
869 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 902 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
870 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | 903 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; |
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index b050d18437ce..0410bea2ad1d 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h | |||
@@ -107,6 +107,32 @@ | |||
107 | #define R8A7791_CLK_I2C1 30 | 107 | #define R8A7791_CLK_I2C1 30 |
108 | #define R8A7791_CLK_I2C0 31 | 108 | #define R8A7791_CLK_I2C0 31 |
109 | 109 | ||
110 | /* MSTP10 */ | ||
111 | #define R8A7791_CLK_SSI_ALL 5 | ||
112 | #define R8A7791_CLK_SSI9 6 | ||
113 | #define R8A7791_CLK_SSI8 7 | ||
114 | #define R8A7791_CLK_SSI7 8 | ||
115 | #define R8A7791_CLK_SSI6 9 | ||
116 | #define R8A7791_CLK_SSI5 10 | ||
117 | #define R8A7791_CLK_SSI4 11 | ||
118 | #define R8A7791_CLK_SSI3 12 | ||
119 | #define R8A7791_CLK_SSI2 13 | ||
120 | #define R8A7791_CLK_SSI1 14 | ||
121 | #define R8A7791_CLK_SSI0 15 | ||
122 | #define R8A7791_CLK_SCU_ALL 17 | ||
123 | #define R8A7791_CLK_SCU_DVC1 18 | ||
124 | #define R8A7791_CLK_SCU_DVC0 19 | ||
125 | #define R8A7791_CLK_SCU_SRC9 22 | ||
126 | #define R8A7791_CLK_SCU_SRC8 23 | ||
127 | #define R8A7791_CLK_SCU_SRC7 24 | ||
128 | #define R8A7791_CLK_SCU_SRC6 25 | ||
129 | #define R8A7791_CLK_SCU_SRC5 26 | ||
130 | #define R8A7791_CLK_SCU_SRC4 27 | ||
131 | #define R8A7791_CLK_SCU_SRC3 28 | ||
132 | #define R8A7791_CLK_SCU_SRC2 29 | ||
133 | #define R8A7791_CLK_SCU_SRC1 30 | ||
134 | #define R8A7791_CLK_SCU_SRC0 31 | ||
135 | |||
110 | /* MSTP11 */ | 136 | /* MSTP11 */ |
111 | #define R8A7791_CLK_SCIFA3 6 | 137 | #define R8A7791_CLK_SCIFA3 6 |
112 | #define R8A7791_CLK_SCIFA4 7 | 138 | #define R8A7791_CLK_SCIFA4 7 |