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authorSteven J. Hill <sjhill@mips.com>2012-08-03 11:26:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-10-11 05:05:03 -0400
commitee80f7c73dc1b1f0ba9f82079c9bd1c0d1aedef8 (patch)
treeef49eefa2ae08e015ebe526d10f81c7fe477d610
parentf59a2d22a05272034e856b7a2dd7a3ab7864a2ae (diff)
MIPS: Add detection of DSP ASE Revision 2.
[ralf@linux-mips.org: This patch really only detects the ASE and passes its existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new resources but no resources that would need management by the kernel.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/cpu-features.h4
-rw-r--r--arch/mips/include/asm/cpu.h1
-rw-r--r--arch/mips/include/asm/mipsregs.h1
-rw-r--r--arch/mips/kernel/cpu-probe.c6
-rw-r--r--arch/mips/kernel/proc.c1
5 files changed, 11 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 089125a6ae6a..c507b931b484 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -171,6 +171,10 @@
171#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 171#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
172#endif 172#endif
173 173
174#ifndef cpu_has_dsp2
175#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
176#endif
177
174#ifndef cpu_has_mipsmt 178#ifndef cpu_has_mipsmt
175#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 179#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
176#endif 180#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 7dc0db8b9426..52c4e914f95a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -332,6 +332,7 @@ enum cpu_type_enum {
332#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 332#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
333#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 333#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
334#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 334#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
335#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
335 336
336 337
337#endif /* _ASM_CPU_H */ 338#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 04d7560dfafb..eb742895dcbe 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -592,6 +592,7 @@
592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
595#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
596#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
597 598
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bd2809698e39..b1fb7af3c350 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -142,7 +142,7 @@ int __cpuinitdata mips_dsp_disabled;
142 142
143static int __init dsp_disable(char *s) 143static int __init dsp_disable(char *s)
144{ 144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP; 145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
146 mips_dsp_disabled = 1; 146 mips_dsp_disabled = 1;
147 147
148 return 1; 148 return 1;
@@ -429,6 +429,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
429 c->options |= MIPS_CPU_RIXI; 429 c->options |= MIPS_CPU_RIXI;
430 if (config3 & MIPS_CONF3_DSP) 430 if (config3 & MIPS_CONF3_DSP)
431 c->ases |= MIPS_ASE_DSP; 431 c->ases |= MIPS_ASE_DSP;
432 if (config3 & MIPS_CONF3_DSP2P)
433 c->ases |= MIPS_ASE_DSP2P;
432 if (config3 & MIPS_CONF3_VINT) 434 if (config3 & MIPS_CONF3_VINT)
433 c->options |= MIPS_CPU_VINT; 435 c->options |= MIPS_CPU_VINT;
434 if (config3 & MIPS_CONF3_VEIC) 436 if (config3 & MIPS_CONF3_VEIC)
@@ -1180,7 +1182,7 @@ __cpuinit void cpu_probe(void)
1180 c->options &= ~MIPS_CPU_FPU; 1182 c->options &= ~MIPS_CPU_FPU;
1181 1183
1182 if (mips_dsp_disabled) 1184 if (mips_dsp_disabled)
1183 c->ases &= ~MIPS_ASE_DSP; 1185 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1184 1186
1185 if (c->options & MIPS_CPU_FPU) { 1187 if (c->options & MIPS_CPU_FPU) {
1186 c->fpu_id = cpu_get_fpu_id(); 1188 c->fpu_id = cpu_get_fpu_id();
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 5542817c1b49..35cf2094f9ae 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -70,6 +70,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
70 cpu_has_mips3d ? " mips3d" : "", 70 cpu_has_mips3d ? " mips3d" : "",
71 cpu_has_smartmips ? " smartmips" : "", 71 cpu_has_smartmips ? " smartmips" : "",
72 cpu_has_dsp ? " dsp" : "", 72 cpu_has_dsp ? " dsp" : "",
73 cpu_has_dsp2 ? " dsp2" : "",
73 cpu_has_mipsmt ? " mt" : "" 74 cpu_has_mipsmt ? " mt" : ""
74 ); 75 );
75 seq_printf(m, "shadow register sets\t: %d\n", 76 seq_printf(m, "shadow register sets\t: %d\n",