diff options
author | Padmavathi Venna <padma.v@samsung.com> | 2015-01-13 06:27:41 -0500 |
---|---|---|
committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-01-15 09:11:40 -0500 |
commit | ee74b56ab2f72c088fc5a8ba3797ef6a452d692a (patch) | |
tree | 684418362c9eb12c633ec4eeb645ed452e67482b | |
parent | 9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551 (diff) |
clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r-- | Documentation/devicetree/bindings/clock/exynos7-clock.txt | 5 | ||||
-rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 73 | ||||
-rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 19 |
3 files changed, 95 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt index d0e048c08817..9282f71830b4 100644 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt | |||
@@ -77,6 +77,11 @@ Input clocks for peric1 clock controller: | |||
77 | - sclk_uart1 | 77 | - sclk_uart1 |
78 | - sclk_uart2 | 78 | - sclk_uart2 |
79 | - sclk_uart3 | 79 | - sclk_uart3 |
80 | - sclk_spi0 | ||
81 | - sclk_spi1 | ||
82 | - sclk_spi2 | ||
83 | - sclk_spi3 | ||
84 | - sclk_spi4 | ||
80 | 85 | ||
81 | Input clocks for peris clock controller: | 86 | Input clocks for peris clock controller: |
82 | - fin_pll | 87 | - fin_pll |
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index d01d766b3eab..d40c09d580b8 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c | |||
@@ -177,9 +177,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", | |||
177 | #define MUX_SEL_TOP00 0x0200 | 177 | #define MUX_SEL_TOP00 0x0200 |
178 | #define MUX_SEL_TOP01 0x0204 | 178 | #define MUX_SEL_TOP01 0x0204 |
179 | #define MUX_SEL_TOP03 0x020C | 179 | #define MUX_SEL_TOP03 0x020C |
180 | #define MUX_SEL_TOP0_PERIC1 0x0234 | ||
181 | #define MUX_SEL_TOP0_PERIC2 0x0238 | ||
180 | #define MUX_SEL_TOP0_PERIC3 0x023C | 182 | #define MUX_SEL_TOP0_PERIC3 0x023C |
181 | #define DIV_TOP03 0x060C | 183 | #define DIV_TOP03 0x060C |
184 | #define DIV_TOP0_PERIC1 0x0634 | ||
185 | #define DIV_TOP0_PERIC2 0x0638 | ||
182 | #define DIV_TOP0_PERIC3 0x063C | 186 | #define DIV_TOP0_PERIC3 0x063C |
187 | #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 | ||
188 | #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 | ||
183 | #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C | 189 | #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C |
184 | 190 | ||
185 | /* List of parent clocks for Muxes in CMU_TOP0 */ | 191 | /* List of parent clocks for Muxes in CMU_TOP0 */ |
@@ -205,9 +211,15 @@ static unsigned long top0_clk_regs[] __initdata = { | |||
205 | MUX_SEL_TOP00, | 211 | MUX_SEL_TOP00, |
206 | MUX_SEL_TOP01, | 212 | MUX_SEL_TOP01, |
207 | MUX_SEL_TOP03, | 213 | MUX_SEL_TOP03, |
214 | MUX_SEL_TOP0_PERIC1, | ||
215 | MUX_SEL_TOP0_PERIC2, | ||
208 | MUX_SEL_TOP0_PERIC3, | 216 | MUX_SEL_TOP0_PERIC3, |
209 | DIV_TOP03, | 217 | DIV_TOP03, |
218 | DIV_TOP0_PERIC1, | ||
219 | DIV_TOP0_PERIC2, | ||
210 | DIV_TOP0_PERIC3, | 220 | DIV_TOP0_PERIC3, |
221 | ENABLE_SCLK_TOP0_PERIC1, | ||
222 | ENABLE_SCLK_TOP0_PERIC2, | ||
211 | ENABLE_SCLK_TOP0_PERIC3, | 223 | ENABLE_SCLK_TOP0_PERIC3, |
212 | }; | 224 | }; |
213 | 225 | ||
@@ -229,10 +241,16 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = { | |||
229 | MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), | 241 | MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), |
230 | MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), | 242 | MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), |
231 | 243 | ||
244 | MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), | ||
245 | MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), | ||
246 | |||
247 | MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), | ||
248 | MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), | ||
232 | MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), | 249 | MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), |
233 | MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), | 250 | MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), |
234 | MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), | 251 | MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), |
235 | MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), | 252 | MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), |
253 | MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), | ||
236 | }; | 254 | }; |
237 | 255 | ||
238 | static struct samsung_div_clock top0_div_clks[] __initdata = { | 256 | static struct samsung_div_clock top0_div_clks[] __initdata = { |
@@ -241,13 +259,29 @@ static struct samsung_div_clock top0_div_clks[] __initdata = { | |||
241 | DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", | 259 | DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", |
242 | DIV_TOP03, 20, 6), | 260 | DIV_TOP03, 20, 6), |
243 | 261 | ||
262 | DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), | ||
263 | DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), | ||
264 | |||
265 | DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), | ||
266 | DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), | ||
267 | |||
244 | DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), | 268 | DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), |
245 | DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), | 269 | DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), |
246 | DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), | 270 | DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), |
247 | DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), | 271 | DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), |
272 | DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), | ||
248 | }; | 273 | }; |
249 | 274 | ||
250 | static struct samsung_gate_clock top0_gate_clks[] __initdata = { | 275 | static struct samsung_gate_clock top0_gate_clks[] __initdata = { |
276 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", | ||
277 | ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), | ||
278 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", | ||
279 | ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), | ||
280 | |||
281 | GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", | ||
282 | ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), | ||
283 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", | ||
284 | ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), | ||
251 | GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", | 285 | GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", |
252 | ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), | 286 | ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), |
253 | GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", | 287 | GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", |
@@ -256,6 +290,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = { | |||
256 | ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), | 290 | ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), |
257 | GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", | 291 | GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", |
258 | ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), | 292 | ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), |
293 | GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", | ||
294 | ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), | ||
259 | }; | 295 | }; |
260 | 296 | ||
261 | static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { | 297 | static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { |
@@ -531,6 +567,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np) | |||
531 | /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ | 567 | /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ |
532 | #define MUX_SEL_PERIC10 0x0200 | 568 | #define MUX_SEL_PERIC10 0x0200 |
533 | #define MUX_SEL_PERIC11 0x0204 | 569 | #define MUX_SEL_PERIC11 0x0204 |
570 | #define MUX_SEL_PERIC12 0x0208 | ||
534 | #define ENABLE_PCLK_PERIC1 0x0900 | 571 | #define ENABLE_PCLK_PERIC1 0x0900 |
535 | #define ENABLE_SCLK_PERIC10 0x0A00 | 572 | #define ENABLE_SCLK_PERIC10 0x0A00 |
536 | 573 | ||
@@ -542,10 +579,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; | |||
542 | PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; | 579 | PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; |
543 | PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; | 580 | PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; |
544 | PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; | 581 | PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; |
582 | PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; | ||
583 | PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; | ||
584 | PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; | ||
585 | PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; | ||
586 | PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; | ||
545 | 587 | ||
546 | static unsigned long peric1_clk_regs[] __initdata = { | 588 | static unsigned long peric1_clk_regs[] __initdata = { |
547 | MUX_SEL_PERIC10, | 589 | MUX_SEL_PERIC10, |
548 | MUX_SEL_PERIC11, | 590 | MUX_SEL_PERIC11, |
591 | MUX_SEL_PERIC12, | ||
549 | ENABLE_PCLK_PERIC1, | 592 | ENABLE_PCLK_PERIC1, |
550 | ENABLE_SCLK_PERIC10, | 593 | ENABLE_SCLK_PERIC10, |
551 | }; | 594 | }; |
@@ -554,6 +597,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = { | |||
554 | MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, | 597 | MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, |
555 | MUX_SEL_PERIC10, 0, 1), | 598 | MUX_SEL_PERIC10, 0, 1), |
556 | 599 | ||
600 | MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, | ||
601 | MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), | ||
602 | MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, | ||
603 | MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), | ||
604 | MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, | ||
605 | MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), | ||
606 | MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, | ||
607 | MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), | ||
608 | MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, | ||
609 | MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), | ||
557 | MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, | 610 | MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, |
558 | MUX_SEL_PERIC11, 20, 1), | 611 | MUX_SEL_PERIC11, 20, 1), |
559 | MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, | 612 | MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, |
@@ -579,6 +632,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = { | |||
579 | ENABLE_PCLK_PERIC1, 10, 0, 0), | 632 | ENABLE_PCLK_PERIC1, 10, 0, 0), |
580 | GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", | 633 | GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", |
581 | ENABLE_PCLK_PERIC1, 11, 0, 0), | 634 | ENABLE_PCLK_PERIC1, 11, 0, 0), |
635 | GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", | ||
636 | ENABLE_PCLK_PERIC1, 12, 0, 0), | ||
637 | GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", | ||
638 | ENABLE_PCLK_PERIC1, 13, 0, 0), | ||
639 | GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", | ||
640 | ENABLE_PCLK_PERIC1, 14, 0, 0), | ||
641 | GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", | ||
642 | ENABLE_PCLK_PERIC1, 15, 0, 0), | ||
643 | GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", | ||
644 | ENABLE_PCLK_PERIC1, 16, 0, 0), | ||
582 | 645 | ||
583 | GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", | 646 | GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", |
584 | ENABLE_SCLK_PERIC10, 9, 0, 0), | 647 | ENABLE_SCLK_PERIC10, 9, 0, 0), |
@@ -586,6 +649,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = { | |||
586 | ENABLE_SCLK_PERIC10, 10, 0, 0), | 649 | ENABLE_SCLK_PERIC10, 10, 0, 0), |
587 | GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", | 650 | GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", |
588 | ENABLE_SCLK_PERIC10, 11, 0, 0), | 651 | ENABLE_SCLK_PERIC10, 11, 0, 0), |
652 | GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", | ||
653 | ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), | ||
654 | GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", | ||
655 | ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), | ||
656 | GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", | ||
657 | ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), | ||
658 | GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", | ||
659 | ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), | ||
660 | GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", | ||
661 | ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), | ||
589 | }; | 662 | }; |
590 | 663 | ||
591 | static struct samsung_cmu_info peric1_cmu_info __initdata = { | 664 | static struct samsung_cmu_info peric1_cmu_info __initdata = { |
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 05e2a47bcb96..75c5888068b2 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h | |||
@@ -28,7 +28,12 @@ | |||
28 | #define CLK_SCLK_UART1 4 | 28 | #define CLK_SCLK_UART1 4 |
29 | #define CLK_SCLK_UART2 5 | 29 | #define CLK_SCLK_UART2 5 |
30 | #define CLK_SCLK_UART3 6 | 30 | #define CLK_SCLK_UART3 6 |
31 | #define TOP0_NR_CLK 7 | 31 | #define CLK_SCLK_SPI0 7 |
32 | #define CLK_SCLK_SPI1 8 | ||
33 | #define CLK_SCLK_SPI2 9 | ||
34 | #define CLK_SCLK_SPI3 10 | ||
35 | #define CLK_SCLK_SPI4 11 | ||
36 | #define TOP0_NR_CLK 12 | ||
32 | 37 | ||
33 | /* TOP1 */ | 38 | /* TOP1 */ |
34 | #define DOUT_ACLK_FSYS1_200 1 | 39 | #define DOUT_ACLK_FSYS1_200 1 |
@@ -72,7 +77,17 @@ | |||
72 | #define PCLK_HSI2C6 9 | 77 | #define PCLK_HSI2C6 9 |
73 | #define PCLK_HSI2C7 10 | 78 | #define PCLK_HSI2C7 10 |
74 | #define PCLK_HSI2C8 11 | 79 | #define PCLK_HSI2C8 11 |
75 | #define PERIC1_NR_CLK 12 | 80 | #define PCLK_SPI0 12 |
81 | #define PCLK_SPI1 13 | ||
82 | #define PCLK_SPI2 14 | ||
83 | #define PCLK_SPI3 15 | ||
84 | #define PCLK_SPI4 16 | ||
85 | #define SCLK_SPI0 17 | ||
86 | #define SCLK_SPI1 18 | ||
87 | #define SCLK_SPI2 19 | ||
88 | #define SCLK_SPI3 20 | ||
89 | #define SCLK_SPI4 21 | ||
90 | #define PERIC1_NR_CLK 22 | ||
76 | 91 | ||
77 | /* PERIS */ | 92 | /* PERIS */ |
78 | #define PCLK_CHIPID 1 | 93 | #define PCLK_CHIPID 1 |