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authorLiam Girdwood <liam.r.girdwood@linux.intel.com>2014-07-30 08:05:44 -0400
committerMark Brown <broonie@linaro.org>2014-07-30 08:16:58 -0400
commitee4a6ce6cd74a9eace247656c5b109f31c73ab8d (patch)
treea4d93c0a641a66a0ed4e6ef6071f7a46faf531aa
parentafdb74fd708fb4330485212f76a70b91967b1f70 (diff)
ASoC: Intel: Fix naming of HMDC register macros.
HMDC is the correct naming for this register. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--sound/soc/intel/sst-dsp.h8
-rw-r--r--sound/soc/intel/sst-haswell-dsp.c6
2 files changed, 7 insertions, 7 deletions
diff --git a/sound/soc/intel/sst-dsp.h b/sound/soc/intel/sst-dsp.h
index 967fb32c981d..21a85eb196f1 100644
--- a/sound/soc/intel/sst-dsp.h
+++ b/sound/soc/intel/sst-dsp.h
@@ -52,7 +52,7 @@
52#define SST_CLKCTL 0x78 52#define SST_CLKCTL 0x78
53#define SST_CSR2 0x80 53#define SST_CSR2 0x80
54#define SST_LTRC 0xE0 54#define SST_LTRC 0xE0
55#define SST_HDMC 0xE8 55#define SST_HMDC 0xE8
56 56
57#define SST_SHIM_BEGIN SST_CSR 57#define SST_SHIM_BEGIN SST_CSR
58#define SST_SHIM_END SST_HDMC 58#define SST_SHIM_END SST_HDMC
@@ -122,9 +122,9 @@
122/* LTRC */ 122/* LTRC */
123#define SST_LTRC_VAL(x) (x << 0) 123#define SST_LTRC_VAL(x) (x << 0)
124 124
125/* HDMC */ 125/* HMDC */
126#define SST_HDMC_HDDA0(x) (x << 0) 126#define SST_HMDC_HDDA0(x) (x << 0)
127#define SST_HDMC_HDDA1(x) (x << 7) 127#define SST_HMDC_HDDA1(x) (x << 7)
128 128
129 129
130/* SST Vendor Defined Registers and bits */ 130/* SST Vendor Defined Registers and bits */
diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c
index 7b8ad9923fe4..0e1dde8c35e6 100644
--- a/sound/soc/intel/sst-haswell-dsp.c
+++ b/sound/soc/intel/sst-haswell-dsp.c
@@ -269,9 +269,9 @@ static void hsw_boot(struct sst_dsp *sst)
269 SST_CSR2_SDFD_SSP1); 269 SST_CSR2_SDFD_SSP1);
270 270
271 /* enable DMA engine 0,1 all channels to access host memory */ 271 /* enable DMA engine 0,1 all channels to access host memory */
272 sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC, 272 sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
273 SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff), 273 SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
274 SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff)); 274 SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));
275 275
276 /* disable all clock gating */ 276 /* disable all clock gating */
277 writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2); 277 writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);