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authorAlex Deucher <alexander.deucher@amd.com>2013-09-27 18:22:15 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-10-09 17:13:44 -0400
commitee0fec312a1c4e26f255955da942562cd8908a4b (patch)
tree6df7e03aa20bbd9c215d60d5deab5c5a3f3dc39f
parente7d12c2f98ae1e68c7298e5028048d150fa553a1 (diff)
drm/radeon: use hw generated CTS/N values for audio
Use the hw generated values rather than calculating them in the driver. There may be some older r6xx asics where this doesn't work correctly. This remains to be seen. See bug: https://bugs.freedesktop.org/show_bug.cgi?id=69675 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c3
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c3
2 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index f71ce390aebe..f815c20640bd 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -288,8 +288,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
289 289
290 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 290 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
291 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 291 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
292 HDMI_ACR_SOURCE); /* select SW CTS value */
293 292
294 evergreen_hdmi_update_ACR(encoder, mode->clock); 293 evergreen_hdmi_update_ACR(encoder, mode->clock);
295 294
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 567703fdfbf1..e2ae1c237fb4 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -451,8 +451,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
451 } 451 }
452 452
453 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 453 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
454 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 454 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
455 HDMI0_ACR_SOURCE); /* select SW CTS value */
456 455
457 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 456 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
458 HDMI0_NULL_SEND | /* send null packets when required */ 457 HDMI0_NULL_SEND | /* send null packets when required */