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authorRabin Vincent <rabin@rab.in>2015-03-09 13:48:25 -0400
committerJesper Nilsson <jespern@axis.com>2015-03-25 06:03:40 -0400
commitedfb6d5f1a05627204d1640ba527312dc8ea745a (patch)
tree3dbf6f9196eada18a6091351091f365149bc0a8a
parented9fd3ff0251783cb3943e71aac398b9064efae6 (diff)
CRISv32: use MMIO clocksource
Use a generic MMIO clocksource and get rid of some lines of code. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
-rw-r--r--arch/cris/Kconfig1
-rw-r--r--arch/cris/arch-v32/kernel/time.c25
2 files changed, 5 insertions, 21 deletions
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 366dc83019a5..bd920ccbef6f 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -55,6 +55,7 @@ config CRIS
55 select IRQ_DOMAIN if ETRAX_ARCH_V32 55 select IRQ_DOMAIN if ETRAX_ARCH_V32
56 select OF if ETRAX_ARCH_V32 56 select OF if ETRAX_ARCH_V32
57 select OF_EARLY_FLATTREE if ETRAX_ARCH_V32 57 select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
58 select CLKSRC_MMIO if ETRAX_ARCH_V32
58 select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32 59 select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
59 60
60config HZ 61config HZ
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index 77e241d6fa3d..7c802121c0c3 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -39,27 +39,6 @@
39 39
40#define CRISV32_TIMER_FREQ (100000000lu) 40#define CRISV32_TIMER_FREQ (100000000lu)
41 41
42/* Register the continuos readonly timer available in FS and ARTPEC-3. */
43static cycle_t read_cont_rotime(struct clocksource *cs)
44{
45 return (u32)REG_RD(timer, regi_timer0, r_time);
46}
47
48static struct clocksource cont_rotime = {
49 .name = "crisv32_rotime",
50 .rating = 300,
51 .read = read_cont_rotime,
52 .mask = CLOCKSOURCE_MASK(32),
53 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
54};
55
56static int __init etrax_init_cont_rotime(void)
57{
58 clocksource_register_khz(&cont_rotime, 100000);
59 return 0;
60}
61arch_initcall(etrax_init_cont_rotime);
62
63unsigned long timer_regs[NR_CPUS] = 42unsigned long timer_regs[NR_CPUS] =
64{ 43{
65 regi_timer0, 44 regi_timer0,
@@ -296,6 +275,10 @@ void __init time_init(void)
296 275
297 crisv32_timer_init(); 276 crisv32_timer_init();
298 277
278 clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
279 "crisv32-timer", CRISV32_TIMER_FREQ,
280 300, 32, clocksource_mmio_readl_up);
281
299 crisv32_clockevent.cpumask = cpu_possible_mask; 282 crisv32_clockevent.cpumask = cpu_possible_mask;
300 crisv32_clockevent.irq = irq; 283 crisv32_clockevent.irq = irq;
301 284