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authorLaxman Dewangan <ldewangan@nvidia.com>2012-11-14 10:39:28 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2012-11-21 10:07:47 -0500
commitedd7eabc85e2f8d76a933b9639bebfe7f98861e4 (patch)
treeaedbc16b600b10177948bbca30cbe692e4a61146
parentdbc4849db33307c72951e4bd4935fbb8d1fc7b8d (diff)
mfd: Add TI TPS80031 mfd core driver
TPS80031/ TPS80032 Fully Integrated Power Management with Power Path and Battery Charger. The device provides five configurable step-down converters, 11 general purpose LDOs, USB OTG Module, ADC, RTC, 2 PWM, System Voltage Regulator/Battery Charger with Power Path from USB, 32K clock generator. Add the mfd core driver for TPS80031/TPS80032. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat
-rw-r--r--drivers/mfd/Kconfig14
-rw-r--r--drivers/mfd/Makefile1
-rw-r--r--drivers/mfd/tps80031.c573
-rw-r--r--include/linux/mfd/tps80031.h637
4 files changed, 1225 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 59359a7a2493..ca633df7c330 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -265,6 +265,20 @@ config MFD_TPS65912_SPI
265 If you say yes here you get support for the TPS65912 series of 265 If you say yes here you get support for the TPS65912 series of
266 PM chips with SPI interface. 266 PM chips with SPI interface.
267 267
268config MFD_TPS80031
269 bool "TI TPS80031/TPS80032 Power Management chips"
270 depends on I2C=y && GENERIC_HARDIRQS
271 select MFD_CORE
272 select REGMAP_I2C
273 select IRQ_DOMAIN
274 help
275 If you say yes here you get support for the Texas Instruments
276 TPS80031/ TPS80032 Fully Integrated Power Management with Power
277 Path and Battery Charger. The device provides five configurable
278 step-down converters, 11 general purpose LDOs, USB OTG Module,
279 ADC, RTC, 2 PWM, System Voltage Regulator/Battery Charger with
280 Power Path from USB, 32K clock generator.
281
268config MENELAUS 282config MENELAUS
269 bool "Texas Instruments TWL92330/Menelaus PM chip" 283 bool "Texas Instruments TWL92330/Menelaus PM chip"
270 depends on I2C=y && ARCH_OMAP2 284 depends on I2C=y && ARCH_OMAP2
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 1c3ee7c76906..8072460e99d2 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -61,6 +61,7 @@ tps65912-objs := tps65912-core.o tps65912-irq.o
61obj-$(CONFIG_MFD_TPS65912) += tps65912.o 61obj-$(CONFIG_MFD_TPS65912) += tps65912.o
62obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o 62obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o
63obj-$(CONFIG_MFD_TPS65912_SPI) += tps65912-spi.o 63obj-$(CONFIG_MFD_TPS65912_SPI) += tps65912-spi.o
64obj-$(CONFIG_MFD_TPS80031) += tps80031.o
64obj-$(CONFIG_MENELAUS) += menelaus.o 65obj-$(CONFIG_MENELAUS) += menelaus.o
65 66
66obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o 67obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o
diff --git a/drivers/mfd/tps80031.c b/drivers/mfd/tps80031.c
new file mode 100644
index 000000000000..f64005efa6fa
--- /dev/null
+++ b/drivers/mfd/tps80031.c
@@ -0,0 +1,573 @@
1/*
2 * tps80031.c -- TI TPS80031/TPS80032 mfd core driver.
3 *
4 * MFD core driver for TI TPS80031/TPS80032 Fully Integrated
5 * Power Management with Power Path and Battery Charger
6 *
7 * Copyright (c) 2012, NVIDIA Corporation.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
16 * whether express or implied; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
23 * 02111-1307, USA
24 */
25
26#include <linux/err.h>
27#include <linux/i2c.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/irq.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/tps80031.h>
33#include <linux/module.h>
34#include <linux/pm.h>
35#include <linux/regmap.h>
36#include <linux/slab.h>
37
38static struct resource tps80031_rtc_resources[] = {
39 {
40 .start = TPS80031_INT_RTC_ALARM,
41 .end = TPS80031_INT_RTC_ALARM,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46/* TPS80031 sub mfd devices */
47static struct mfd_cell tps80031_cell[] = {
48 {
49 .name = "tps80031-pmic",
50 },
51 {
52 .name = "tps80031-clock",
53 },
54 {
55 .name = "tps80031-rtc",
56 .num_resources = ARRAY_SIZE(tps80031_rtc_resources),
57 .resources = tps80031_rtc_resources,
58 },
59 {
60 .name = "tps80031-gpadc",
61 },
62 {
63 .name = "tps80031-fuel-gauge",
64 },
65 {
66 .name = "tps80031-charger",
67 },
68};
69
70static int tps80031_slave_address[TPS80031_NUM_SLAVES] = {
71 TPS80031_I2C_ID0_ADDR,
72 TPS80031_I2C_ID1_ADDR,
73 TPS80031_I2C_ID2_ADDR,
74 TPS80031_I2C_ID3_ADDR,
75};
76
77struct tps80031_pupd_data {
78 u8 reg;
79 u8 pullup_bit;
80 u8 pulldown_bit;
81};
82
83#define TPS80031_IRQ(_reg, _mask) \
84 { \
85 .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
86 TPS80031_INT_MSK_LINE_A, \
87 .mask = BIT(_mask), \
88 }
89
90static const struct regmap_irq tps80031_main_irqs[] = {
91 [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0),
92 [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1),
93 [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2),
94 [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3),
95 [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4),
96 [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5),
97 [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6),
98 [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7),
99 [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
100 [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
101 [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
102 [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
103 [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
104 [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
105 [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
106 [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
107 [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0),
108 [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1),
109 [TPS80031_INT_ID] = TPS80031_IRQ(C, 2),
110 [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3),
111 [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4),
112 [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5),
113 [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6),
114 [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7),
115};
116
117static struct regmap_irq_chip tps80031_irq_chip = {
118 .name = "tps80031",
119 .irqs = tps80031_main_irqs,
120 .num_irqs = ARRAY_SIZE(tps80031_main_irqs),
121 .num_regs = 3,
122 .status_base = TPS80031_INT_STS_A,
123 .mask_base = TPS80031_INT_MSK_LINE_A,
124};
125
126#define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \
127 { \
128 .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
129 .pulldown_bit = _pulldown_bit, \
130 .pullup_bit = _pullup_bit, \
131 }
132
133static const struct tps80031_pupd_data tps80031_pupds[] = {
134 [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)),
135 [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)),
136 [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)),
137 [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)),
138 [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)),
139 [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)),
140 [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0),
141 [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)),
142 [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)),
143 [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)),
144 [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0),
145 [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)),
146 [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)),
147 [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)),
148 [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)),
149};
150static struct tps80031 *tps80031_power_off_dev;
151
152int tps80031_ext_power_req_config(struct device *dev,
153 unsigned long ext_ctrl_flag, int preq_bit,
154 int state_reg_add, int trans_reg_add)
155{
156 u8 res_ass_reg = 0;
157 int preq_mask_bit = 0;
158 int ret;
159
160 if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ))
161 return 0;
162
163 if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) {
164 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
165 preq_mask_bit = 5;
166 } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) {
167 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
168 preq_mask_bit = 6;
169 } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) {
170 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
171 preq_mask_bit = 7;
172 }
173
174 /* Configure REQ_ASS registers */
175 ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg,
176 BIT(preq_bit & 0x7));
177 if (ret < 0) {
178 dev_err(dev, "reg 0x%02x setbit failed, err = %d\n",
179 res_ass_reg, ret);
180 return ret;
181 }
182
183 /* Unmask the PREQ */
184 ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1,
185 TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
186 if (ret < 0) {
187 dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n",
188 TPS80031_PHOENIX_MSK_TRANSITION, ret);
189 return ret;
190 }
191
192 /* Switch regulator control to resource now */
193 if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 |
194 TPS80031_PWR_REQ_INPUT_PREQ3)) {
195 ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add,
196 0x0, TPS80031_STATE_MASK);
197 if (ret < 0)
198 dev_err(dev, "reg 0x%02x update failed, err = %d\n",
199 state_reg_add, ret);
200 } else {
201 ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add,
202 TPS80031_TRANS_SLEEP_OFF,
203 TPS80031_TRANS_SLEEP_MASK);
204 if (ret < 0)
205 dev_err(dev, "reg 0x%02x update failed, err = %d\n",
206 trans_reg_add, ret);
207 }
208 return ret;
209}
210EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
211
212static void tps80031_power_off(void)
213{
214 dev_info(tps80031_power_off_dev->dev, "switching off PMU\n");
215 tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1,
216 TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF);
217}
218
219static void tps80031_pupd_init(struct tps80031 *tps80031,
220 struct tps80031_platform_data *pdata)
221{
222 struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
223 int data_size = pdata->pupd_init_data_size;
224 int i;
225
226 for (i = 0; i < data_size; ++i) {
227 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
228 const struct tps80031_pupd_data *pupd =
229 &tps80031_pupds[pupd_init->input_pin];
230 u8 update_value = 0;
231 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
232
233 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
234 update_value = pupd->pulldown_bit;
235 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
236 update_value = pupd->pullup_bit;
237
238 tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg,
239 update_value, update_mask);
240 }
241}
242
243static int tps80031_init_ext_control(struct tps80031 *tps80031,
244 struct tps80031_platform_data *pdata)
245{
246 struct device *dev = tps80031->dev;
247 int ret;
248 int i;
249
250 /* Clear all external control for this rail */
251 for (i = 0; i < 9; ++i) {
252 ret = tps80031_write(dev, TPS80031_SLAVE_ID1,
253 TPS80031_PREQ1_RES_ASS_A + i, 0);
254 if (ret < 0) {
255 dev_err(dev, "reg 0x%02x write failed, err = %d\n",
256 TPS80031_PREQ1_RES_ASS_A + i, ret);
257 return ret;
258 }
259 }
260
261 /* Mask the PREQ */
262 ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1,
263 TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
264 if (ret < 0) {
265 dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n",
266 TPS80031_PHOENIX_MSK_TRANSITION, ret);
267 return ret;
268 }
269 return ret;
270}
271
272static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
273 int irq_base)
274{
275 struct device *dev = tps80031->dev;
276 int i, ret;
277
278 /*
279 * The MASK register used for updating status register when
280 * interrupt occurs and LINE register used to pass the status
281 * to actual interrupt line. As per datasheet:
282 * When INT_MSK_LINE [i] is set to 1, the associated interrupt
283 * number i is INT line masked, which means that no interrupt is
284 * generated on the INT line.
285 * When INT_MSK_LINE [i] is set to 0, the associated interrupt
286 * number i is line enabled: An interrupt is generated on the
287 * INT line.
288 * In any case, the INT_STS [i] status bit may or may not be updated,
289 * only linked to the INT_MSK_STS [i] configuration register bit.
290 *
291 * When INT_MSK_STS [i] is set to 1, the associated interrupt number
292 * i is status masked, which means that no interrupt is stored in
293 * the INT_STS[i] status bit. Note that no interrupt number i is
294 * generated on the INT line, even if the INT_MSK_LINE [i] register
295 * bit is set to 0.
296 * When INT_MSK_STS [i] is set to 0, the associated interrupt number i
297 * is status enabled: An interrupt status is updated in the INT_STS [i]
298 * register. The interrupt may or may not be generated on the INT line,
299 * depending on the INT_MSK_LINE [i] configuration register bit.
300 */
301 for (i = 0; i < 3; i++)
302 tps80031_write(dev, TPS80031_SLAVE_ID2,
303 TPS80031_INT_MSK_STS_A + i, 0x00);
304
305 ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq,
306 IRQF_ONESHOT, irq_base,
307 &tps80031_irq_chip, &tps80031->irq_data);
308 if (ret < 0) {
309 dev_err(dev, "add irq failed, err = %d\n", ret);
310 return ret;
311 }
312 return ret;
313}
314
315static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
316{
317 switch (reg) {
318 case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE:
319 return true;
320 default:
321 return false;
322 }
323}
324
325static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
326{
327 switch (reg) {
328 case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG:
329 case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7:
330 case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG:
331 case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
332 case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST:
333 case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
334 case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
335 case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
336 case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
337 case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
338 case TPS80031_BACKUP_REG:
339 return true;
340 default:
341 return false;
342 }
343}
344
345static bool is_volatile_reg_id1(struct device *dev, unsigned int reg)
346{
347 switch (reg) {
348 case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
349 case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
350 case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
351 case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
352 case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
353 case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
354 return true;
355 default:
356 return false;
357 }
358}
359
360static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
361{
362 switch (reg) {
363 case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION:
364 case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1:
365 case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB:
366 case TPS80031_TOGGLE1 ... TPS80031_VIBMODE:
367 case TPS80031_PWM1ON ... TPS80031_PWM2OFF:
368 case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11:
369 case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C:
370 case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2:
371 return true;
372 default:
373 return false;
374 }
375}
376
377static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
378{
379 switch (reg) {
380 case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18:
381 return true;
382 default:
383 return false;
384 }
385}
386
387static const struct regmap_config tps80031_regmap_configs[] = {
388 {
389 .reg_bits = 8,
390 .val_bits = 8,
391 .writeable_reg = rd_wr_reg_id0,
392 .readable_reg = rd_wr_reg_id0,
393 .max_register = TPS80031_MAX_REGISTER,
394 },
395 {
396 .reg_bits = 8,
397 .val_bits = 8,
398 .writeable_reg = rd_wr_reg_id1,
399 .readable_reg = rd_wr_reg_id1,
400 .volatile_reg = is_volatile_reg_id1,
401 .max_register = TPS80031_MAX_REGISTER,
402 },
403 {
404 .reg_bits = 8,
405 .val_bits = 8,
406 .writeable_reg = rd_wr_reg_id2,
407 .readable_reg = rd_wr_reg_id2,
408 .max_register = TPS80031_MAX_REGISTER,
409 },
410 {
411 .reg_bits = 8,
412 .val_bits = 8,
413 .writeable_reg = rd_wr_reg_id3,
414 .readable_reg = rd_wr_reg_id3,
415 .max_register = TPS80031_MAX_REGISTER,
416 },
417};
418
419static int __devinit tps80031_probe(struct i2c_client *client,
420 const struct i2c_device_id *id)
421{
422 struct tps80031_platform_data *pdata = client->dev.platform_data;
423 struct tps80031 *tps80031;
424 int ret;
425 uint8_t es_version;
426 uint8_t ep_ver;
427 int i;
428
429 if (!pdata) {
430 dev_err(&client->dev, "tps80031 requires platform data\n");
431 return -EINVAL;
432 }
433
434 tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
435 if (!tps80031) {
436 dev_err(&client->dev, "Malloc failed for tps80031\n");
437 return -ENOMEM;
438 }
439
440 for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
441 if (tps80031_slave_address[i] == client->addr)
442 tps80031->clients[i] = client;
443 else
444 tps80031->clients[i] = i2c_new_dummy(client->adapter,
445 tps80031_slave_address[i]);
446 if (!tps80031->clients[i]) {
447 dev_err(&client->dev, "can't attach client %d\n", i);
448 ret = -ENOMEM;
449 goto fail_client_reg;
450 }
451
452 i2c_set_clientdata(tps80031->clients[i], tps80031);
453 tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i],
454 &tps80031_regmap_configs[i]);
455 if (IS_ERR(tps80031->regmap[i])) {
456 ret = PTR_ERR(tps80031->regmap[i]);
457 dev_err(&client->dev,
458 "regmap %d init failed, err %d\n", i, ret);
459 goto fail_client_reg;
460 }
461 }
462
463 ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
464 TPS80031_JTAGVERNUM, &es_version);
465 if (ret < 0) {
466 dev_err(&client->dev,
467 "Silicon version number read failed: %d\n", ret);
468 goto fail_client_reg;
469 }
470
471 ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
472 TPS80031_EPROM_REV, &ep_ver);
473 if (ret < 0) {
474 dev_err(&client->dev,
475 "Silicon eeprom version read failed: %d\n", ret);
476 goto fail_client_reg;
477 }
478
479 dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
480 es_version, ep_ver);
481 tps80031->es_version = es_version;
482 tps80031->dev = &client->dev;
483 i2c_set_clientdata(client, tps80031);
484 tps80031->chip_info = id->driver_data;
485
486 ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
487 if (ret) {
488 dev_err(&client->dev, "IRQ init failed: %d\n", ret);
489 goto fail_client_reg;
490 }
491
492 tps80031_pupd_init(tps80031, pdata);
493
494 tps80031_init_ext_control(tps80031, pdata);
495
496 ret = mfd_add_devices(tps80031->dev, -1,
497 tps80031_cell, ARRAY_SIZE(tps80031_cell),
498 NULL, 0,
499 regmap_irq_get_domain(tps80031->irq_data));
500 if (ret < 0) {
501 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
502 goto fail_mfd_add;
503 }
504
505 if (pdata->use_power_off && !pm_power_off) {
506 tps80031_power_off_dev = tps80031;
507 pm_power_off = tps80031_power_off;
508 }
509 return 0;
510
511fail_mfd_add:
512 regmap_del_irq_chip(client->irq, tps80031->irq_data);
513
514fail_client_reg:
515 for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
516 if (tps80031->clients[i] && (tps80031->clients[i] != client))
517 i2c_unregister_device(tps80031->clients[i]);
518 }
519 return ret;
520}
521
522static int __devexit tps80031_remove(struct i2c_client *client)
523{
524 struct tps80031 *tps80031 = i2c_get_clientdata(client);
525 int i;
526
527 if (tps80031_power_off_dev == tps80031) {
528 tps80031_power_off_dev = NULL;
529 pm_power_off = NULL;
530 }
531
532 mfd_remove_devices(tps80031->dev);
533
534 regmap_del_irq_chip(client->irq, tps80031->irq_data);
535
536 for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
537 if (tps80031->clients[i] != client)
538 i2c_unregister_device(tps80031->clients[i]);
539 }
540 return 0;
541}
542
543static const struct i2c_device_id tps80031_id_table[] = {
544 { "tps80031", TPS80031 },
545 { "tps80032", TPS80032 },
546};
547MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
548
549static struct i2c_driver tps80031_driver = {
550 .driver = {
551 .name = "tps80031",
552 .owner = THIS_MODULE,
553 },
554 .probe = tps80031_probe,
555 .remove = __devexit_p(tps80031_remove),
556 .id_table = tps80031_id_table,
557};
558
559static int __init tps80031_init(void)
560{
561 return i2c_add_driver(&tps80031_driver);
562}
563subsys_initcall(tps80031_init);
564
565static void __exit tps80031_exit(void)
566{
567 i2c_del_driver(&tps80031_driver);
568}
569module_exit(tps80031_exit);
570
571MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
572MODULE_DESCRIPTION("TPS80031 core driver");
573MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
new file mode 100644
index 000000000000..2c75c9c9318f
--- /dev/null
+++ b/include/linux/mfd/tps80031.h
@@ -0,0 +1,637 @@
1/*
2 * tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver.
3 *
4 * Copyright (c) 2012, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307, USA
21 */
22
23#ifndef __LINUX_MFD_TPS80031_H
24#define __LINUX_MFD_TPS80031_H
25
26#include <linux/device.h>
27#include <linux/regmap.h>
28
29/* Pull-ups/Pull-downs */
30#define TPS80031_CFG_INPUT_PUPD1 0xF0
31#define TPS80031_CFG_INPUT_PUPD2 0xF1
32#define TPS80031_CFG_INPUT_PUPD3 0xF2
33#define TPS80031_CFG_INPUT_PUPD4 0xF3
34#define TPS80031_CFG_LDO_PD1 0xF4
35#define TPS80031_CFG_LDO_PD2 0xF5
36#define TPS80031_CFG_SMPS_PD 0xF6
37
38/* Real Time Clock */
39#define TPS80031_SECONDS_REG 0x00
40#define TPS80031_MINUTES_REG 0x01
41#define TPS80031_HOURS_REG 0x02
42#define TPS80031_DAYS_REG 0x03
43#define TPS80031_MONTHS_REG 0x04
44#define TPS80031_YEARS_REG 0x05
45#define TPS80031_WEEKS_REG 0x06
46#define TPS80031_ALARM_SECONDS_REG 0x08
47#define TPS80031_ALARM_MINUTES_REG 0x09
48#define TPS80031_ALARM_HOURS_REG 0x0A
49#define TPS80031_ALARM_DAYS_REG 0x0B
50#define TPS80031_ALARM_MONTHS_REG 0x0C
51#define TPS80031_ALARM_YEARS_REG 0x0D
52#define TPS80031_RTC_CTRL_REG 0x10
53#define TPS80031_RTC_STATUS_REG 0x11
54#define TPS80031_RTC_INTERRUPTS_REG 0x12
55#define TPS80031_RTC_COMP_LSB_REG 0x13
56#define TPS80031_RTC_COMP_MSB_REG 0x14
57#define TPS80031_RTC_RESET_STATUS_REG 0x16
58
59/*PMC Master Module */
60#define TPS80031_PHOENIX_START_CONDITION 0x1F
61#define TPS80031_PHOENIX_MSK_TRANSITION 0x20
62#define TPS80031_STS_HW_CONDITIONS 0x21
63#define TPS80031_PHOENIX_LAST_TURNOFF_STS 0x22
64#define TPS80031_VSYSMIN_LO_THRESHOLD 0x23
65#define TPS80031_VSYSMIN_HI_THRESHOLD 0x24
66#define TPS80031_PHOENIX_DEV_ON 0x25
67#define TPS80031_STS_PWR_GRP_STATE 0x27
68#define TPS80031_PH_CFG_VSYSLOW 0x28
69#define TPS80031_PH_STS_BOOT 0x29
70#define TPS80031_PHOENIX_SENS_TRANSITION 0x2A
71#define TPS80031_PHOENIX_SEQ_CFG 0x2B
72#define TPS80031_PRIMARY_WATCHDOG_CFG 0X2C
73#define TPS80031_KEY_PRESS_DUR_CFG 0X2D
74#define TPS80031_SMPS_LDO_SHORT_STS 0x2E
75
76/* PMC Slave Module - Broadcast */
77#define TPS80031_BROADCAST_ADDR_ALL 0x31
78#define TPS80031_BROADCAST_ADDR_REF 0x32
79#define TPS80031_BROADCAST_ADDR_PROV 0x33
80#define TPS80031_BROADCAST_ADDR_CLK_RST 0x34
81
82/* PMC Slave Module SMPS Regulators */
83#define TPS80031_SMPS4_CFG_TRANS 0x41
84#define TPS80031_SMPS4_CFG_STATE 0x42
85#define TPS80031_SMPS4_CFG_VOLTAGE 0x44
86#define TPS80031_VIO_CFG_TRANS 0x47
87#define TPS80031_VIO_CFG_STATE 0x48
88#define TPS80031_VIO_CFG_FORCE 0x49
89#define TPS80031_VIO_CFG_VOLTAGE 0x4A
90#define TPS80031_VIO_CFG_STEP 0x48
91#define TPS80031_SMPS1_CFG_TRANS 0x53
92#define TPS80031_SMPS1_CFG_STATE 0x54
93#define TPS80031_SMPS1_CFG_FORCE 0x55
94#define TPS80031_SMPS1_CFG_VOLTAGE 0x56
95#define TPS80031_SMPS1_CFG_STEP 0x57
96#define TPS80031_SMPS2_CFG_TRANS 0x59
97#define TPS80031_SMPS2_CFG_STATE 0x5A
98#define TPS80031_SMPS2_CFG_FORCE 0x5B
99#define TPS80031_SMPS2_CFG_VOLTAGE 0x5C
100#define TPS80031_SMPS2_CFG_STEP 0x5D
101#define TPS80031_SMPS3_CFG_TRANS 0x65
102#define TPS80031_SMPS3_CFG_STATE 0x66
103#define TPS80031_SMPS3_CFG_VOLTAGE 0x68
104
105/* PMC Slave Module LDO Regulators */
106#define TPS80031_VANA_CFG_TRANS 0x81
107#define TPS80031_VANA_CFG_STATE 0x82
108#define TPS80031_VANA_CFG_VOLTAGE 0x83
109#define TPS80031_LDO2_CFG_TRANS 0x85
110#define TPS80031_LDO2_CFG_STATE 0x86
111#define TPS80031_LDO2_CFG_VOLTAGE 0x87
112#define TPS80031_LDO4_CFG_TRANS 0x89
113#define TPS80031_LDO4_CFG_STATE 0x8A
114#define TPS80031_LDO4_CFG_VOLTAGE 0x8B
115#define TPS80031_LDO3_CFG_TRANS 0x8D
116#define TPS80031_LDO3_CFG_STATE 0x8E
117#define TPS80031_LDO3_CFG_VOLTAGE 0x8F
118#define TPS80031_LDO6_CFG_TRANS 0x91
119#define TPS80031_LDO6_CFG_STATE 0x92
120#define TPS80031_LDO6_CFG_VOLTAGE 0x93
121#define TPS80031_LDOLN_CFG_TRANS 0x95
122#define TPS80031_LDOLN_CFG_STATE 0x96
123#define TPS80031_LDOLN_CFG_VOLTAGE 0x97
124#define TPS80031_LDO5_CFG_TRANS 0x99
125#define TPS80031_LDO5_CFG_STATE 0x9A
126#define TPS80031_LDO5_CFG_VOLTAGE 0x9B
127#define TPS80031_LDO1_CFG_TRANS 0x9D
128#define TPS80031_LDO1_CFG_STATE 0x9E
129#define TPS80031_LDO1_CFG_VOLTAGE 0x9F
130#define TPS80031_LDOUSB_CFG_TRANS 0xA1
131#define TPS80031_LDOUSB_CFG_STATE 0xA2
132#define TPS80031_LDOUSB_CFG_VOLTAGE 0xA3
133#define TPS80031_LDO7_CFG_TRANS 0xA5
134#define TPS80031_LDO7_CFG_STATE 0xA6
135#define TPS80031_LDO7_CFG_VOLTAGE 0xA7
136
137/* PMC Slave Module External Control */
138#define TPS80031_REGEN1_CFG_TRANS 0xAE
139#define TPS80031_REGEN1_CFG_STATE 0xAF
140#define TPS80031_REGEN2_CFG_TRANS 0xB1
141#define TPS80031_REGEN2_CFG_STATE 0xB2
142#define TPS80031_SYSEN_CFG_TRANS 0xB4
143#define TPS80031_SYSEN_CFG_STATE 0xB5
144
145/* PMC Slave Module Internal Control */
146#define TPS80031_NRESPWRON_CFG_TRANS 0xB7
147#define TPS80031_NRESPWRON_CFG_STATE 0xB8
148#define TPS80031_CLK32KAO_CFG_TRANS 0xBA
149#define TPS80031_CLK32KAO_CFG_STATE 0xBB
150#define TPS80031_CLK32KG_CFG_TRANS 0xBD
151#define TPS80031_CLK32KG_CFG_STATE 0xBE
152#define TPS80031_CLK32KAUDIO_CFG_TRANS 0xC0
153#define TPS80031_CLK32KAUDIO_CFG_STATE 0xC1
154#define TPS80031_VRTC_CFG_TRANS 0xC3
155#define TPS80031_VRTC_CFG_STATE 0xC4
156#define TPS80031_BIAS_CFG_TRANS 0xC6
157#define TPS80031_BIAS_CFG_STATE 0xC7
158#define TPS80031_VSYSMIN_HI_CFG_TRANS 0xC9
159#define TPS80031_VSYSMIN_HI_CFG_STATE 0xCA
160#define TPS80031_RC6MHZ_CFG_TRANS 0xCC
161#define TPS80031_RC6MHZ_CFG_STATE 0xCD
162#define TPS80031_TMP_CFG_TRANS 0xCF
163#define TPS80031_TMP_CFG_STATE 0xD0
164
165/* PMC Slave Module resources assignment */
166#define TPS80031_PREQ1_RES_ASS_A 0xD7
167#define TPS80031_PREQ1_RES_ASS_B 0xD8
168#define TPS80031_PREQ1_RES_ASS_C 0xD9
169#define TPS80031_PREQ2_RES_ASS_A 0xDA
170#define TPS80031_PREQ2_RES_ASS_B 0xDB
171#define TPS80031_PREQ2_RES_ASS_C 0xDC
172#define TPS80031_PREQ3_RES_ASS_A 0xDD
173#define TPS80031_PREQ3_RES_ASS_B 0xDE
174#define TPS80031_PREQ3_RES_ASS_C 0xDF
175
176/* PMC Slave Module Miscellaneous */
177#define TPS80031_SMPS_OFFSET 0xE0
178#define TPS80031_SMPS_MULT 0xE3
179#define TPS80031_MISC1 0xE4
180#define TPS80031_MISC2 0xE5
181#define TPS80031_BBSPOR_CFG 0xE6
182#define TPS80031_TMP_CFG 0xE7
183
184/* Battery Charging Controller and Indicator LED */
185#define TPS80031_CONTROLLER_CTRL2 0xDA
186#define TPS80031_CONTROLLER_VSEL_COMP 0xDB
187#define TPS80031_CHARGERUSB_VSYSREG 0xDC
188#define TPS80031_CHARGERUSB_VICHRG_PC 0xDD
189#define TPS80031_LINEAR_CHRG_STS 0xDE
190#define TPS80031_CONTROLLER_INT_MASK 0xE0
191#define TPS80031_CONTROLLER_CTRL1 0xE1
192#define TPS80031_CONTROLLER_WDG 0xE2
193#define TPS80031_CONTROLLER_STAT1 0xE3
194#define TPS80031_CHARGERUSB_INT_STATUS 0xE4
195#define TPS80031_CHARGERUSB_INT_MASK 0xE5
196#define TPS80031_CHARGERUSB_STATUS_INT1 0xE6
197#define TPS80031_CHARGERUSB_STATUS_INT2 0xE7
198#define TPS80031_CHARGERUSB_CTRL1 0xE8
199#define TPS80031_CHARGERUSB_CTRL2 0xE9
200#define TPS80031_CHARGERUSB_CTRL3 0xEA
201#define TPS80031_CHARGERUSB_STAT1 0xEB
202#define TPS80031_CHARGERUSB_VOREG 0xEC
203#define TPS80031_CHARGERUSB_VICHRG 0xED
204#define TPS80031_CHARGERUSB_CINLIMIT 0xEE
205#define TPS80031_CHARGERUSB_CTRLLIMIT1 0xEF
206#define TPS80031_CHARGERUSB_CTRLLIMIT2 0xF0
207#define TPS80031_LED_PWM_CTRL1 0xF4
208#define TPS80031_LED_PWM_CTRL2 0xF5
209
210/* USB On-The-Go */
211#define TPS80031_BACKUP_REG 0xFA
212#define TPS80031_USB_VENDOR_ID_LSB 0x00
213#define TPS80031_USB_VENDOR_ID_MSB 0x01
214#define TPS80031_USB_PRODUCT_ID_LSB 0x02
215#define TPS80031_USB_PRODUCT_ID_MSB 0x03
216#define TPS80031_USB_VBUS_CTRL_SET 0x04
217#define TPS80031_USB_VBUS_CTRL_CLR 0x05
218#define TPS80031_USB_ID_CTRL_SET 0x06
219#define TPS80031_USB_ID_CTRL_CLR 0x07
220#define TPS80031_USB_VBUS_INT_SRC 0x08
221#define TPS80031_USB_VBUS_INT_LATCH_SET 0x09
222#define TPS80031_USB_VBUS_INT_LATCH_CLR 0x0A
223#define TPS80031_USB_VBUS_INT_EN_LO_SET 0x0B
224#define TPS80031_USB_VBUS_INT_EN_LO_CLR 0x0C
225#define TPS80031_USB_VBUS_INT_EN_HI_SET 0x0D
226#define TPS80031_USB_VBUS_INT_EN_HI_CLR 0x0E
227#define TPS80031_USB_ID_INT_SRC 0x0F
228#define TPS80031_USB_ID_INT_LATCH_SET 0x10
229#define TPS80031_USB_ID_INT_LATCH_CLR 0x11
230#define TPS80031_USB_ID_INT_EN_LO_SET 0x12
231#define TPS80031_USB_ID_INT_EN_LO_CLR 0x13
232#define TPS80031_USB_ID_INT_EN_HI_SET 0x14
233#define TPS80031_USB_ID_INT_EN_HI_CLR 0x15
234#define TPS80031_USB_OTG_ADP_CTRL 0x16
235#define TPS80031_USB_OTG_ADP_HIGH 0x17
236#define TPS80031_USB_OTG_ADP_LOW 0x18
237#define TPS80031_USB_OTG_ADP_RISE 0x19
238#define TPS80031_USB_OTG_REVISION 0x1A
239
240/* Gas Gauge */
241#define TPS80031_FG_REG_00 0xC0
242#define TPS80031_FG_REG_01 0xC1
243#define TPS80031_FG_REG_02 0xC2
244#define TPS80031_FG_REG_03 0xC3
245#define TPS80031_FG_REG_04 0xC4
246#define TPS80031_FG_REG_05 0xC5
247#define TPS80031_FG_REG_06 0xC6
248#define TPS80031_FG_REG_07 0xC7
249#define TPS80031_FG_REG_08 0xC8
250#define TPS80031_FG_REG_09 0xC9
251#define TPS80031_FG_REG_10 0xCA
252#define TPS80031_FG_REG_11 0xCB
253
254/* General Purpose ADC */
255#define TPS80031_GPADC_CTRL 0x2E
256#define TPS80031_GPADC_CTRL2 0x2F
257#define TPS80031_RTSELECT_LSB 0x32
258#define TPS80031_RTSELECT_ISB 0x33
259#define TPS80031_RTSELECT_MSB 0x34
260#define TPS80031_GPSELECT_ISB 0x35
261#define TPS80031_CTRL_P1 0x36
262#define TPS80031_RTCH0_LSB 0x37
263#define TPS80031_RTCH0_MSB 0x38
264#define TPS80031_RTCH1_LSB 0x39
265#define TPS80031_RTCH1_MSB 0x3A
266#define TPS80031_GPCH0_LSB 0x3B
267#define TPS80031_GPCH0_MSB 0x3C
268
269/* SIM, MMC and Battery Detection */
270#define TPS80031_SIMDEBOUNCING 0xEB
271#define TPS80031_SIMCTRL 0xEC
272#define TPS80031_MMCDEBOUNCING 0xED
273#define TPS80031_MMCCTRL 0xEE
274#define TPS80031_BATDEBOUNCING 0xEF
275
276/* Vibrator Driver and PWMs */
277#define TPS80031_VIBCTRL 0x9B
278#define TPS80031_VIBMODE 0x9C
279#define TPS80031_PWM1ON 0xBA
280#define TPS80031_PWM1OFF 0xBB
281#define TPS80031_PWM2ON 0xBD
282#define TPS80031_PWM2OFF 0xBE
283
284/* Control Interface */
285#define TPS80031_INT_STS_A 0xD0
286#define TPS80031_INT_STS_B 0xD1
287#define TPS80031_INT_STS_C 0xD2
288#define TPS80031_INT_MSK_LINE_A 0xD3
289#define TPS80031_INT_MSK_LINE_B 0xD4
290#define TPS80031_INT_MSK_LINE_C 0xD5
291#define TPS80031_INT_MSK_STS_A 0xD6
292#define TPS80031_INT_MSK_STS_B 0xD7
293#define TPS80031_INT_MSK_STS_C 0xD8
294#define TPS80031_TOGGLE1 0x90
295#define TPS80031_TOGGLE2 0x91
296#define TPS80031_TOGGLE3 0x92
297#define TPS80031_PWDNSTATUS1 0x93
298#define TPS80031_PWDNSTATUS2 0x94
299#define TPS80031_VALIDITY0 0x17
300#define TPS80031_VALIDITY1 0x18
301#define TPS80031_VALIDITY2 0x19
302#define TPS80031_VALIDITY3 0x1A
303#define TPS80031_VALIDITY4 0x1B
304#define TPS80031_VALIDITY5 0x1C
305#define TPS80031_VALIDITY6 0x1D
306#define TPS80031_VALIDITY7 0x1E
307
308/* Version number related register */
309#define TPS80031_JTAGVERNUM 0x87
310#define TPS80031_EPROM_REV 0xDF
311
312/* GPADC Trimming Bits. */
313#define TPS80031_GPADC_TRIM0 0xCC
314#define TPS80031_GPADC_TRIM1 0xCD
315#define TPS80031_GPADC_TRIM2 0xCE
316#define TPS80031_GPADC_TRIM3 0xCF
317#define TPS80031_GPADC_TRIM4 0xD0
318#define TPS80031_GPADC_TRIM5 0xD1
319#define TPS80031_GPADC_TRIM6 0xD2
320#define TPS80031_GPADC_TRIM7 0xD3
321#define TPS80031_GPADC_TRIM8 0xD4
322#define TPS80031_GPADC_TRIM9 0xD5
323#define TPS80031_GPADC_TRIM10 0xD6
324#define TPS80031_GPADC_TRIM11 0xD7
325#define TPS80031_GPADC_TRIM12 0xD8
326#define TPS80031_GPADC_TRIM13 0xD9
327#define TPS80031_GPADC_TRIM14 0xDA
328#define TPS80031_GPADC_TRIM15 0xDB
329#define TPS80031_GPADC_TRIM16 0xDC
330#define TPS80031_GPADC_TRIM17 0xDD
331#define TPS80031_GPADC_TRIM18 0xDE
332
333/* TPS80031_CONTROLLER_STAT1 bit fields */
334#define TPS80031_CONTROLLER_STAT1_BAT_TEMP 0
335#define TPS80031_CONTROLLER_STAT1_BAT_REMOVED 1
336#define TPS80031_CONTROLLER_STAT1_VBUS_DET 2
337#define TPS80031_CONTROLLER_STAT1_VAC_DET 3
338#define TPS80031_CONTROLLER_STAT1_FAULT_WDG 4
339#define TPS80031_CONTROLLER_STAT1_LINCH_GATED 6
340/* TPS80031_CONTROLLER_INT_MASK bit filed */
341#define TPS80031_CONTROLLER_INT_MASK_MVAC_DET 0
342#define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET 1
343#define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP 2
344#define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG 3
345#define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED 4
346#define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED 5
347
348#define TPS80031_CHARGE_CONTROL_SUB_INT_MASK 0x3F
349
350/* TPS80031_PHOENIX_DEV_ON bit field */
351#define TPS80031_DEVOFF 0x1
352
353#define TPS80031_EXT_CONTROL_CFG_TRANS 0
354#define TPS80031_EXT_CONTROL_CFG_STATE 1
355
356/* State register field */
357#define TPS80031_STATE_OFF 0x00
358#define TPS80031_STATE_ON 0x01
359#define TPS80031_STATE_MASK 0x03
360
361/* Trans register field */
362#define TPS80031_TRANS_ACTIVE_OFF 0x00
363#define TPS80031_TRANS_ACTIVE_ON 0x01
364#define TPS80031_TRANS_ACTIVE_MASK 0x03
365#define TPS80031_TRANS_SLEEP_OFF 0x00
366#define TPS80031_TRANS_SLEEP_ON 0x04
367#define TPS80031_TRANS_SLEEP_MASK 0x0C
368#define TPS80031_TRANS_OFF_OFF 0x00
369#define TPS80031_TRANS_OFF_ACTIVE 0x10
370#define TPS80031_TRANS_OFF_MASK 0x30
371
372#define TPS80031_EXT_PWR_REQ (TPS80031_PWR_REQ_INPUT_PREQ1 | \
373 TPS80031_PWR_REQ_INPUT_PREQ2 | \
374 TPS80031_PWR_REQ_INPUT_PREQ3)
375
376/* TPS80031_BBSPOR_CFG bit field */
377#define TPS80031_BBSPOR_CHG_EN 0x8
378#define TPS80031_MAX_REGISTER 0xFF
379
380struct i2c_client;
381
382/* Supported chips */
383enum chips {
384 TPS80031 = 0x00000001,
385 TPS80032 = 0x00000002,
386};
387
388enum {
389 TPS80031_INT_PWRON,
390 TPS80031_INT_RPWRON,
391 TPS80031_INT_SYS_VLOW,
392 TPS80031_INT_RTC_ALARM,
393 TPS80031_INT_RTC_PERIOD,
394 TPS80031_INT_HOT_DIE,
395 TPS80031_INT_VXX_SHORT,
396 TPS80031_INT_SPDURATION,
397 TPS80031_INT_WATCHDOG,
398 TPS80031_INT_BAT,
399 TPS80031_INT_SIM,
400 TPS80031_INT_MMC,
401 TPS80031_INT_RES,
402 TPS80031_INT_GPADC_RT,
403 TPS80031_INT_GPADC_SW2_EOC,
404 TPS80031_INT_CC_AUTOCAL,
405 TPS80031_INT_ID_WKUP,
406 TPS80031_INT_VBUSS_WKUP,
407 TPS80031_INT_ID,
408 TPS80031_INT_VBUS,
409 TPS80031_INT_CHRG_CTRL,
410 TPS80031_INT_EXT_CHRG,
411 TPS80031_INT_INT_CHRG,
412 TPS80031_INT_RES2,
413 TPS80031_INT_BAT_TEMP_OVRANGE,
414 TPS80031_INT_BAT_REMOVED,
415 TPS80031_INT_VBUS_DET,
416 TPS80031_INT_VAC_DET,
417 TPS80031_INT_FAULT_WDG,
418 TPS80031_INT_LINCH_GATED,
419
420 /* Last interrupt id to get the end number */
421 TPS80031_INT_NR,
422};
423
424/* TPS80031 Slave IDs */
425#define TPS80031_NUM_SLAVES 4
426#define TPS80031_SLAVE_ID0 0
427#define TPS80031_SLAVE_ID1 1
428#define TPS80031_SLAVE_ID2 2
429#define TPS80031_SLAVE_ID3 3
430
431/* TPS80031 I2C addresses */
432#define TPS80031_I2C_ID0_ADDR 0x12
433#define TPS80031_I2C_ID1_ADDR 0x48
434#define TPS80031_I2C_ID2_ADDR 0x49
435#define TPS80031_I2C_ID3_ADDR 0x4A
436
437enum {
438 TPS80031_REGULATOR_VIO,
439 TPS80031_REGULATOR_SMPS1,
440 TPS80031_REGULATOR_SMPS2,
441 TPS80031_REGULATOR_SMPS3,
442 TPS80031_REGULATOR_SMPS4,
443 TPS80031_REGULATOR_VANA,
444 TPS80031_REGULATOR_LDO1,
445 TPS80031_REGULATOR_LDO2,
446 TPS80031_REGULATOR_LDO3,
447 TPS80031_REGULATOR_LDO4,
448 TPS80031_REGULATOR_LDO5,
449 TPS80031_REGULATOR_LDO6,
450 TPS80031_REGULATOR_LDO7,
451 TPS80031_REGULATOR_LDOLN,
452 TPS80031_REGULATOR_LDOUSB,
453 TPS80031_REGULATOR_VBUS,
454 TPS80031_REGULATOR_REGEN1,
455 TPS80031_REGULATOR_REGEN2,
456 TPS80031_REGULATOR_SYSEN,
457 TPS80031_REGULATOR_MAX,
458};
459
460/* Different configurations for the rails */
461enum {
462 /* USBLDO input selection */
463 TPS80031_USBLDO_INPUT_VSYS = 0x00000001,
464 TPS80031_USBLDO_INPUT_PMID = 0x00000002,
465
466 /* LDO3 output mode */
467 TPS80031_LDO3_OUTPUT_VIB = 0x00000004,
468
469 /* VBUS configuration */
470 TPS80031_VBUS_DISCHRG_EN_PDN = 0x00000004,
471 TPS80031_VBUS_SW_ONLY = 0x00000008,
472 TPS80031_VBUS_SW_N_ID = 0x00000010,
473};
474
475/* External controls requests */
476enum tps80031_ext_control {
477 TPS80031_PWR_REQ_INPUT_NONE = 0x00000000,
478 TPS80031_PWR_REQ_INPUT_PREQ1 = 0x00000001,
479 TPS80031_PWR_REQ_INPUT_PREQ2 = 0x00000002,
480 TPS80031_PWR_REQ_INPUT_PREQ3 = 0x00000004,
481 TPS80031_PWR_OFF_ON_SLEEP = 0x00000008,
482 TPS80031_PWR_ON_ON_SLEEP = 0x00000010,
483};
484
485enum tps80031_pupd_pins {
486 TPS80031_PREQ1 = 0,
487 TPS80031_PREQ2A,
488 TPS80031_PREQ2B,
489 TPS80031_PREQ2C,
490 TPS80031_PREQ3,
491 TPS80031_NRES_WARM,
492 TPS80031_PWM_FORCE,
493 TPS80031_CHRG_EXT_CHRG_STATZ,
494 TPS80031_SIM,
495 TPS80031_MMC,
496 TPS80031_GPADC_START,
497 TPS80031_DVSI2C_SCL,
498 TPS80031_DVSI2C_SDA,
499 TPS80031_CTLI2C_SCL,
500 TPS80031_CTLI2C_SDA,
501};
502
503enum tps80031_pupd_settings {
504 TPS80031_PUPD_NORMAL,
505 TPS80031_PUPD_PULLDOWN,
506 TPS80031_PUPD_PULLUP,
507};
508
509struct tps80031 {
510 struct device *dev;
511 unsigned long chip_info;
512 int es_version;
513 struct i2c_client *clients[TPS80031_NUM_SLAVES];
514 struct regmap *regmap[TPS80031_NUM_SLAVES];
515 struct regmap_irq_chip_data *irq_data;
516};
517
518struct tps80031_pupd_init_data {
519 int input_pin;
520 int setting;
521};
522
523/*
524 * struct tps80031_regulator_platform_data - tps80031 regulator platform data.
525 *
526 * @reg_init_data: The regulator init data.
527 * @ext_ctrl_flag: External control flag for sleep/power request control.
528 * @config_flags: Configuration flag to configure the rails.
529 * It should be ORed of config enums.
530 */
531
532struct tps80031_regulator_platform_data {
533 struct regulator_init_data *reg_init_data;
534 unsigned int ext_ctrl_flag;
535 unsigned int config_flags;
536};
537
538struct tps80031_platform_data {
539 int irq_base;
540 bool use_power_off;
541 struct tps80031_pupd_init_data *pupd_init_data;
542 int pupd_init_data_size;
543 struct tps80031_regulator_platform_data
544 *regulator_pdata[TPS80031_REGULATOR_MAX];
545};
546
547static inline int tps80031_write(struct device *dev, int sid,
548 int reg, uint8_t val)
549{
550 struct tps80031 *tps80031 = dev_get_drvdata(dev);
551
552 return regmap_write(tps80031->regmap[sid], reg, val);
553}
554
555static inline int tps80031_writes(struct device *dev, int sid, int reg,
556 int len, uint8_t *val)
557{
558 struct tps80031 *tps80031 = dev_get_drvdata(dev);
559
560 return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
561}
562
563static inline int tps80031_read(struct device *dev, int sid,
564 int reg, uint8_t *val)
565{
566 struct tps80031 *tps80031 = dev_get_drvdata(dev);
567 unsigned int ival;
568 int ret;
569
570 ret = regmap_read(tps80031->regmap[sid], reg, &ival);
571 if (ret < 0) {
572 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
573 return ret;
574 }
575
576 *val = ival;
577 return ret;
578}
579
580static inline int tps80031_reads(struct device *dev, int sid,
581 int reg, int len, uint8_t *val)
582{
583 struct tps80031 *tps80031 = dev_get_drvdata(dev);
584
585 return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
586}
587
588static inline int tps80031_set_bits(struct device *dev, int sid,
589 int reg, uint8_t bit_mask)
590{
591 struct tps80031 *tps80031 = dev_get_drvdata(dev);
592
593 return regmap_update_bits(tps80031->regmap[sid], reg,
594 bit_mask, bit_mask);
595}
596
597static inline int tps80031_clr_bits(struct device *dev, int sid,
598 int reg, uint8_t bit_mask)
599{
600 struct tps80031 *tps80031 = dev_get_drvdata(dev);
601
602 return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
603}
604
605static inline int tps80031_update(struct device *dev, int sid,
606 int reg, uint8_t val, uint8_t mask)
607{
608 struct tps80031 *tps80031 = dev_get_drvdata(dev);
609
610 return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
611}
612
613static inline unsigned long tps80031_get_chip_info(struct device *dev)
614{
615 struct tps80031 *tps80031 = dev_get_drvdata(dev);
616
617 return tps80031->chip_info;
618}
619
620static inline int tps80031_get_pmu_version(struct device *dev)
621{
622 struct tps80031 *tps80031 = dev_get_drvdata(dev);
623
624 return tps80031->es_version;
625}
626
627static inline int tps80031_irq_get_virq(struct device *dev, int irq)
628{
629 struct tps80031 *tps80031 = dev_get_drvdata(dev);
630
631 return regmap_irq_get_virq(tps80031->irq_data, irq);
632}
633
634extern int tps80031_ext_power_req_config(struct device *dev,
635 unsigned long ext_ctrl_flag, int preq_bit,
636 int state_reg_add, int trans_reg_add);
637#endif /*__LINUX_MFD_TPS80031_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 17:04:51 -0400